JPS6261535U - - Google Patents
Info
- Publication number
- JPS6261535U JPS6261535U JP15120985U JP15120985U JPS6261535U JP S6261535 U JPS6261535 U JP S6261535U JP 15120985 U JP15120985 U JP 15120985U JP 15120985 U JP15120985 U JP 15120985U JP S6261535 U JPS6261535 U JP S6261535U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- control circuit
- night
- radio receiver
- day
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Description
第１図は本考案の一実施例のブロツク図、第２
図は第１図に示された処理回路１８の動作を説明
するためのフローチヤート、第３図は本考案の他
の実施例のブロツク図、第４図は本考案のさらに
他の実施例のブロツク図である。
１…アンテナ、２，３，６…コイル、４，５…
コンデンサ、７…高周波増幅回路、８…同調回路
、１２…混合回路、１３…局部発振回路、１４…
中間増幅回路、１５…検波回路、１６…低周波増
幅回路、１７…スピーカ、１８…処理回路、１９
…サーチスイツチ、２０…フエイズロツクループ
周波数シンセサイザ、２７…自動利得制御回路、
２８…受信電界強度検出回路、２９…レベル弁別
回路、３０…基準レベル設定回路、３１…時計回
路、３３，４０…トランジスタ、３５…比較回路
。
Fig. 1 is a block diagram of an embodiment of the present invention;
1 is a flowchart for explaining the operation of the processing circuit 18 shown in FIG. 1, FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. 4 is a flowchart of another embodiment of the present invention. It is a block diagram. 1...Antenna, 2,3,6...Coil, 4,5...
Capacitor, 7... High frequency amplifier circuit, 8... Tuning circuit, 12... Mixing circuit, 13... Local oscillation circuit, 14...
Intermediate amplifier circuit, 15... Detection circuit, 16... Low frequency amplifier circuit, 17... Speaker, 18... Processing circuit, 19
... search switch, 20... phase lock loop frequency synthesizer, 27... automatic gain control circuit,
28...Received electric field strength detection circuit, 29...Level discrimination circuit, 30...Reference level setting circuit, 31...Clock circuit, 33, 40...Transistor, 35...Comparison circuit.
Claims (1)
送を選択的に受信する電子同調式ラジオ受信回路
と、 時計回路と、 時計回路からの出力に応答し、夜間には、昼間
に比べて受信電界強度が高いラジオ放送を音響化
する制御回路とを含むことを特徴とする電子同調
式ラジオ受信機。 (2) 前記制御回路は、アンテナ出力を夜間には
昼間に比べて低く設定することを特徴とする実用
新案登録請求の範囲第１項記載の電子同調式ラジ
オ受信機。 (3) 前記制御回路は、ラジオ受信回路に含まれ
ている高周波増幅回路の利得を、夜間には昼間に
比べて低く設定することを特徴とする実用新案登
録請求の範囲第１項記載の電子同調式ラジオ受信
機。 (4) 前記制御回路は、前記予め定めた受信電界
強度を、夜間には昼間に比べて高く設定すること
を特徴とする実用新案登録請求の範囲第１項記載
の電子同調式ラジオ受信機。[Scope of Claim for Utility Model Registration] (1) An electronically tuned radio receiving circuit that selectively receives radio broadcasts exceeding a predetermined receiving field strength; a clock circuit; An electronically tuned radio receiver characterized by comprising a control circuit that converts radio broadcasts, whose received field strength is higher than that in the daytime, into audible sound. (2) The electronically tuned radio receiver according to claim 1, wherein the control circuit sets the antenna output lower at night than during the day. (3) The electronic device according to claim 1, wherein the control circuit sets the gain of the high frequency amplification circuit included in the radio receiving circuit to be lower at night than during the day. Tunable radio receiver. (4) The electronically tuned radio receiver according to claim 1, wherein the control circuit sets the predetermined received field strength higher at night than during the day.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15120985U JPS6261535U (en) | 1985-10-02 | 1985-10-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15120985U JPS6261535U (en) | 1985-10-02 | 1985-10-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6261535U true JPS6261535U (en) | 1987-04-16 |
Family
ID=31068069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15120985U Pending JPS6261535U (en) | 1985-10-02 | 1985-10-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6261535U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5870622A (en) * | 1981-10-22 | 1983-04-27 | Mitsubishi Electric Corp | Receiver |
| JPS5826234B2 (en) * | 1974-12-20 | 1983-06-01 | ソニー株式会社 | Method for recording and reproducing video signals and other information signals |
-
1985
- 1985-10-02 JP JP15120985U patent/JPS6261535U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5826234B2 (en) * | 1974-12-20 | 1983-06-01 | ソニー株式会社 | Method for recording and reproducing video signals and other information signals |
| JPS5870622A (en) * | 1981-10-22 | 1983-04-27 | Mitsubishi Electric Corp | Receiver |
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