JPS6314512Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention is based on a fuse locked loop (PLL).
This invention relates to a mute signal generator for a PLL tuner using a PLL tuner.

A tuner using a PLL is generally configured as shown in Fig. 1, where 1 is a receiving antenna, 2 is a receiving section including a detection/amplification circuit, etc., and 3 is a receiving section including a detection/amplification circuit, etc.
PLL section, 4 is a controller, 5 is a display section, 6a,
6b is a group of operation buttons, and 7 is a mute circuit.

One of the operation button groups 6a and 6b, 6a, does not change the received frequency of the tuner even if the operation button is operated, but the other 6b allows tuning of the tuner by operating the operation button. Operation button group 6b
It also generates a constant mute signal in response to the operation of the operation button, and applies this to the mute circuit 7 to cut off the audio signal sent from the receiver 2 to the speaker via the mute circuit 7. The controller 4 obtains signals from the operation button groups 6a and 6b, displays the receiving frequency, etc. on the display section 5, and
Settings such as the frequency division ratio of the PLL section 3 are performed.

With the above-described configuration, when the operation button of the operation button group 6b is operated, the controller 4 controls the PLL section 3.
The frequency dividing ratio N is outputted to tune the receiving section 2, and the receiving frequency at that time is displayed on the display section 5. When the receiving section 2 is tuned, it sends an audio signal to the speaker through the mute circuit 7. Further, when the operation button group 6b sends a signal to the controller 4 in response to the operation of the operation button, a mute signal to the mute circuit 7 is also outputted unconditionally.
Therefore, when the reception frequency changes, mute is applied for a certain period of time. As described above, each time the operation button related to the reception frequency setting is operated, a mute signal for eliminating noise is output until tuning is completed, thereby eliminating noise during tuning.

However, in the conventional device described above, a mute signal is generated unconditionally every time the operation button for setting the reception frequency is operated, so if the same operation button, which functions as a preset memory key, is repeatedly operated, for example, As a result, even though the receiving frequency did not change, muting was applied each time the button was pressed, causing a problem in which the audio signal became interrupted and audible.

This invention was made in view of the above points,
The purpose of this is to prevent the generation of mute signals when the receiving frequency does not change.
An object of the present invention is to provide a mute signal generator for a PLL tuner.

The present invention will be explained below with reference to FIG. 2 and subsequent figures.

FIG. 2 is a block diagram showing the configuration of a PLL tuner having a mute signal generator according to the present invention.
Components equivalent to those in FIG. 1 are given the same reference numerals.

In FIG. 2, the operation button groups 6a, 6 in FIG.
b are collectively shown as an operation section 6, and a comparison section 8 is added. The comparison section 8 is
Compares the frequency division ratio data input from the PLL section 3 and the controller 4, and if the two data do not match, outputs a mute signal for a certain period of time,
This is applied to the mute circuit 7.

FIG. 3 is a block diagram showing details of the main parts of the present invention. The PLL unit 3 includes a shift register 3a that receives frequency division ratio data from the controller 4 via a signal line _L1 , and a signal line _L2 from the controller 4.
In addition to a programmable frequency divider 3b that reads frequency division ratio data from the shift register 3a in response to a latch pulse applied via a phase comparator 3c,
Reference oscillator 3d, low pass filter (LPF) 3
e and a voltage controlled oscillator (VCO) 3f.

The comparison unit 8 compares the frequency division ratio data from the controller 4 and the frequency division ratio data from the shift register 3a, and includes a comparator 8a that outputs a signal if they do not match, and a comparator 8a that outputs a signal in response to a latch pulse from the controller 4. It includes a latch circuit 8b that latches the signal from 8a and outputs the signal, and a one-shot multivibrator 8c that generates a mute signal as a pulse lasting a certain period of time in response to the output of the latch circuit 8b. is applied to the mute circuit 7 to perform a mute operation.

As described above, when the preset memory key of the operation unit 6 is operated, the controller 4 outputs frequency division ratio data to the shift register 3a and one input of the comparator 8a. At this time, the frequency division ratio data corresponding to the reception frequency currently being received is input from the shift register 3a to the other input of the comparator 8a. Therefore, comparator 8a
compares the frequency division ratio data of both inputs for each corresponding bit, and outputs a signal when the two do not match. The output signal of the comparator 8a is applied to the input of a latch circuit 8b, and the latch circuit 8b latches the input signal in response to a latch pulse from the controller 4 and outputs a signal. The one-shot multivibrator 8c is triggered by the output signal of the latch circuit 8b and generates a mute signal at its output, which causes the mute circuit 7
performs a mute operation to cut off the audio signal from the receiving section 2.

However, when the frequency division ratio data output by the controller 4 in response to a key operation on the operation section 6 corresponds to the frequency currently being received and is the same as that in the shift register 8a, the comparator 8a of the comparison section 8 does not generate a signal at its output and no signal is latched by the latch circuit 8b, so the one-shot multivibrator 8c is not triggered and no mute signal is generated.

Therefore, for example, even if the same preset memory key is operated repeatedly, the inconvenience of muting as in the conventional case does not occur.

As mentioned above, the present invention compares the frequency division ratio data corresponding to the frequency currently being received with the newly added frequency division ratio data, and generates a mute signal only when the two do not match. Therefore, unnecessary muting is no longer applied, and reception performance that is favorable to the audibility can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing a tuner incorporating the device of the present invention, and FIG. 3 is a block diagram showing details of the main parts of the present invention. 3a...shift register (storage means), 8a...
... Comparator (comparison means), 8c... One-shot multivibrator (pulse generation means).

Claims (1)

[Scope of utility model registration request] A storage means for storing frequency division ratio data corresponding to the frequency currently being received; and a comparison between the frequency division ratio data stored in this storage means and the frequency division ratio data corresponding to the frequency to be newly received. A mute signal generating device for a PLL tuner, characterized in that it is provided with a comparing means that outputs a signal when both frequency division ratio data do not match, and a pulse generating means that generates a pulse in accordance with the output signal of the comparing means. .