JPS6130770B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a tracking correction device for obtaining optimal tuning between a high frequency tuning circuit and a local oscillation circuit in a synthesizer type superheterodyne receiver using a PLL (PHASE LOCK LOOP). For example, on September 5, 1978,
Patent application filed on date (1) ``Tracking correction device for broadcasting receiver'' is proposed. According to this document, it is proposed to perform optimal tuning by varying the tuning frequency of a high frequency signal tuning circuit (hereinafter referred to as a signal tuning circuit) near a tuning point. However, providing a variable cap (variable capacitance element) in parallel in the signal tuning circuit so that the tuning frequency can be varied near the tuning point lowers the Q of the signal tuning circuit and deteriorates the performance. The present invention aims to provide means for improving such problems. FIG. 1 shows the AM front section according to the above proposal. A DC voltage Vc is simultaneously applied to the variable cap C of the signal tuning circuit and the local oscillation circuit to vary the capacitance thereof. A variable cap _CTR is provided in the signal tuning circuit so that a high frequency tuning frequency (hereinafter referred to as tuning frequency) can be varied for automatic tracking, and its capacitance is controlled by a DC voltage _VTR . La is the high frequency signal tuning inductance,
Lo is the oscillation coil, Co is the DC blocking capacitor, R
is the DC voltage application resistor of the variable cap C _TR , C _T
and Cp are the trimmer capacitor and patching capacitor of the local oscillation circuit, and Ro is the varicap C.
This is a resistor for applying DC voltage. In the signal tuning circuit, the tuning frequency is basically determined by the high frequency signal tuning inductance La and the variable cap C, but the tuning frequency is determined by the high frequency signal tuning inductance La and the variable cap C.
C ₀ , a varicap C _TR and a resistor R for applying a DC voltage are added, and these enable tracking correction. For this reason, the Q of the tuning circuit of La and C is lowered by the Q of each of the DC blocking capacitor and the variable cap _CTR and the especially problematic resistance R, and even when R=1 MΩ, there is a non-negligible effect. Therefore, in order to improve this problem, the present invention makes it possible to vary the local oscillation frequency so that tracking correction can be performed using a local oscillation circuit.
As shown in the figure, there is an example in which a varicap _CTR , a DC blocking capacitor _C0 , and a DC voltage application resistor R are incorporated into a local oscillation circuit for tracking correction. In this example, there is no reduction in the Q of the high frequency tuning circuit, and the Q of the local oscillation circuit is slightly reduced, but as long as the Q necessary for oscillation can be maintained, there will be no major problem in terms of performance. According to the circuit shown in Figure 2, the tuning frequency of the local oscillation circuit is changed without correcting the deviation in the tuning frequency of the signal tuning circuit for tracking correction. If this changes, there will be an inconvenience that the broadcast signal cannot be received. For example, when trying to receive a broadcast of 800Hz=s, the oscillation frequency o of the local oscillation circuit is
o = s + i = 800 + 450 (KHz) However, i: intermediate frequency is 455KHz, and as shown in Figure 3, in the high frequency signal tuning circuit, there is a deviation of about 4KHz from the maximum response point, causing a tracking error. becomes. Therefore, local oscillation frequency o=1255KHz→
By changing to 1251KHz, the maximum response can be obtained in the high frequency signal tuning circuit, but the broadcast signal is only 800KHz, and 800-4
= It is inconvenient to receive at 796KHz. The present invention aims to provide a receiver that solves such problems, and is a wrinkle sizer type receiver using a PLL. An example to which the local oscillation oscillation circuit shown in the figure is applied will be described below. In addition, in FIG. 2, parts equivalent to those in FIG. 1 are represented by the same symbols. FIG. 4 shows a block diagram of a PLL synthesizer type AM tuner which is an embodiment of the present invention. 1 is an AM front end, which consists of a signal tuning circuit A, a local oscillation circuit B, a mixing and frequency conversion circuit C, and the like. The output from this AM front end 1 is passed through an intermediate frequency amplification circuit 2 to a detection circuit 3.
The signal detected there is amplified,
input to the speaker. 4 is a PLL synthesizer section, which includes a frequency divider D for the crystal oscillation circuit, a programmable frequency divider E for the local oscillation signal from the local oscillation circuit B, a latch circuit F that is a buffer for data given to the frequency divider E, and a phase It is composed of a comparator G and a low pass filter H. 6 is a 1-chip microcomputer (hereinafter referred to as
It is called CPU. ), including ROM, RAM and their address buses, data buses, accumulators,
It consists of I/O ports, etc. 7 is a display unit which displays the frequency at the time of reception of the signal from the CPU 6. 8 is the keyboard, 0-9
It has a number key and a set key, allowing you to input the desired reception frequency. Enter the desired receiving frequency from keyboard 8.
When an AM broadcast is received, the signal from the antenna is amplified by the signal tuning circuit A, mixed with the local oscillation signal of the local oscillation circuit B, and frequency-converted by the mixing and frequency conversion circuit to become a 455KHz intermediate frequency signal. This intermediate frequency signal is amplified by an intermediate frequency amplification circuit 2 and detected by a detection circuit 3. Here, the local oscillation signal of local oscillation circuit B is supplied to programmable frequency divider E, and the local oscillation signal is
The data from the CPU 6 is latched by the latch circuit F and fed from there to the program frequency divider E, so that the local oscillation signal is frequency-divided by 1/N. In addition, if the receiving frequency is 800KHz, N=
800+455=1255, generally receiving frequency K
In Hz, N=+455. This frequency-divided output is compared with a signal with a reference frequency of 1KHz obtained by dividing the oscillation output of the crystal oscillator by a frequency divider D in a phase comparator G, and after the comparison output passes through a low-pass filter H, the local oscillator Circuit B
The voltage is applied as a voltage to the variable capacitance element for controlling the local oscillation frequency of the signal tuning circuit A, and is also applied as a voltage to the variable capacitance element for controlling the tuning frequency of the signal tuning circuit A. Such a loop is a so-called PLL synthesizer loop, but since this itself is not the gist of the invention, a detailed explanation will be omitted. In this way, the local oscillation frequency is (+
455) KHz = 800 is controlled to be maintained at 1255KHz, and the signal tuning frequency is controlled by the output of the low-pass filter H, so if the tuner is well designed, the signal tuning frequency will be approximately 800KHz. get. However, as mentioned above, a tracking error occurs, which reaches about 4KHz as in the above example, and due to the variation in the variable capacitance element.
It gets even bigger. The present invention corrects such tracking errors to obtain optimal tuning, and an example will be described below. The comparator circuit 5 is a hysteresis comparator for comparing the magnitude of the output of the intermediate frequency amplification circuit 2 with the variable reference voltage V, and is a hysteresis comparator for comparing the magnitude of the output of the intermediate frequency amplification circuit 2 with the variable reference voltage V. A comparison is made with the extraction reference voltage V. That is, if it is larger than the reference voltage V, the output of the comparator circuit 5 is
HiGH (1), if smaller, LOW (0). The output of this comparator 5 is read by the CPU 6. Also, a 4-bit signal is obtained as the output of the CPU 6, and this signal is sent to the D/A converter 9.
Here, in response to a 4-bit signal, it is converted into an analog voltage and output, and this is applied to the variable shape C for tracking correction of the local oscillator circuit B.
Applied to _TR . FIG. 2 shows a configuration diagram of local oscillation circuit B. FIG. Here, a tuned circuit is formed by a variable cap C to which a voltage from a low-pass filter H is applied, an oscillation coil Lo, and a capacitor Cp, and a minute capacitor is connected in parallel with this tuned circuit. This minute capacitance is made by connecting a varicap _CTR in series with a capacitor of about 10PF. Here, the digital signal from CPU6 is
When the output from 0001 changes to 0010, 0011, ...1111, and the output of the D/A converter 9 is gradually increased from 1V, the varicap C _TR changes as shown in Fig. 5.
The capacity of will gradually decrease. As this capacitance decreases, the oscillation tuning capacitance of the entire oscillation circuit decreases and the oscillation frequency increases.If the voltage Vc from the low-pass filter H of the PLL synthesizer section remains constant, It becomes impossible to reach the oscillation frequency. However, due to the increase in the oscillation frequency, the voltage from the low-pass filter H of the PLL synthesizer section is lowered, and the local oscillation frequency is controlled to be the same value as before the capacitance was reduced, and the high-frequency signal tuning frequency is also changed as the capacitance decreases. It is controlled to be a certain value smaller than the previous one. That is, when the digital signal from the CPU 6 is initially at a certain value, when the digital signal is increased from that value, the analog voltage that is the output of the D/A converter 9 increases, in other words. V _TR
increases, the capacitance of the varicap _CTR decreases, and as a result, when the local oscillation frequency ₀ increases, the output voltage Vc of the low-pass filter H decreases, and the local oscillation frequency ₀ and high frequency signal tuning frequency s are controlled to decrease. , according to the characteristics of the PLL loop, the local oscillation frequency ₀ eventually settles to the value before the increase in the digital signal, and the high-frequency signal tuning frequency s becomes lower than the value before the increase in the digital signal due to the decrease in the output voltage Vc of the low-pass filter H. also settles down to a certain small value. For example, if the tracking error is 4KHz when receiving 800KHz, and the voltage applied to the variable cap _CTR is an analog voltage corresponding to a digital signal of 1000, the high frequency signal tuning circuit in this case will reach a maximum of 804KHz. Form a tuned circuit to obtain a response. Here, when the digital signal changes, the output 2 which is the output of the intermediate frequency amplification circuit 2 corresponding to 0001 to 1111 and the output 5 obtained as the output of the comparator circuit 5 are as follows.
It is shown as in FIG. Note that an example is described in which the tuning frequency of 2 KHz changes with each rise of "1" in the digital signal. The reference voltage V of the comparator 5 is set to an appropriate value, for example, a value greater than the noise level when there is no signal, and the comparator 5 has a hysteresis characteristic that allows the output to be reversed by slight fluctuations in the output of the intermediate frequency amplification circuit 2. Care has been taken to ensure that there is nothing to do. Therefore, when receiving 800KHz, if a predetermined voltage is applied to the varicap _CTR , for example, a voltage corresponding to a digital signal of 1000, the local oscillation frequency o will change according to the loop of the PLL synthesizer.
455 + 800KHz, and the high frequency signal tuning s becomes 804KHz according to the tracking error, which is the point at which the tuning point is obtained.After this, the voltage to the variable cap _CTR , in other words, the digital signal is varied, and the intermediate frequency is adjusted. To obtain the point at which the output of the amplification circuit 2 is maximum, for example, find the period of the digital signal during which the intermediate frequency amplification circuit 2 exceeds the reference voltage V, that is, the central value 0110 of 0011 to 1001, and High frequency signal tuning frequency 800KHz by applying corresponding analog voltage to Varicap C _TR
In other words, optimal tuning with tracking correction can be achieved. Focusing on this point, the CPU 6 is of a synthesizer type using a PLL, and supplies a signal for varying the voltage applied to the variable cap of the local oscillation circuit near the tuning point, and thus varying the high frequency signal tuning frequency s. and means for obtaining an output for providing a tuning point based on a signal responsive to whether the output from the intermediate frequency amplification circuit 2 is higher than the reference voltage V, and controlling input to the varicap of the local oscillation circuit. The device is configured to include means that can be introduced as a device, and has the following functional parts. Regarding the functional part of this CPU6, please refer to the 7th section below.
This will be understood from the explanation of the operation with reference to FIGS. 9 to 9. Note that FIGS. 7 to 9 show flowcharts for explaining the operation of the above embodiment. First, by turning on the power, it becomes START, and the initial value setting operation begins. At this time, registers to be used later, for example, X register, Y register,
The TR register etc. are cleared and the output of the detection circuit 3 is muted so that no sound is produced. In this initial value setting, a preset broadcasting station frequency, for example 530, is input into the display register X, and the contents of the X register, X=530, are displayed on the display section 7. next,

According to the routine of [Equation], "8" is input to the register TR as the voltage data to be applied to the variable cap C _TR , and the contents of the register TR are output. This results in CPU
A digital signal 1000 is input from 6 to a D/A transformer 9, from which an analog voltage corresponding to the digital signal 1000 is obtained and applied to the variable cap _CTR . next,

According to the routine of [formula], the data stored in register X, that is,
455 is added to =530, and the result is input to register Y and further output to be applied to PLL synthesizer section 4, ie, latch circuit F. The PLL synthesizer section 4 operates according to the output from the latch circuit F, receives the broadcast, and outputs an intermediate frequency signal to the intermediate frequency amplification circuit 2. The output _S1 that the comparison circuit 5 obtains by comparing this intermediate frequency signal with the reference voltage V is Low (0) level when there is no broadcast of the preset station, and High (1) level when there is broadcast. But this is

[Formula] Loaded into CPU6 by routine and is given to register A. Then the routine

According to [Formula], it is determined whether the contents of register A is ₁ or not.

[Formula] In the routine, wait for a key on keyboard 8 to be pressed, and if the pressed key is a numeric key, register the pressed number N (corresponding to the frequency of the station you wish to receive). X and displayed on the display section 8, indicating that the pressed key is

In the case of [formula]

[Formula] To return to the routine and receive the broadcast of frequency N displayed on display section 8.
Operate the PLL synthesizer section. Then, when it is determined that S ₁ =1 and A=1, the optimal tracking operation state is reached according to the optimal tracking routine as described later, and then the above-mentioned

[Formula] is introduced into Rouchi. Therefore, even when there is a preset broadcast, the frequency N of the desired broadcast can be given by key input on the keyboard 8, and the PLL synthesizer section 4 operates accordingly. In this way, if there is a broadcast, either a preset broadcast or a broadcast desired by the user by inputting with the keyboard 8,

When a YES determination is obtained in the routine of [Formula], the optimum tracking routine is introduced. FIG. 8 shows an example of an optimal tracking routine. This optimal tracking routine detects the optimal tracking point as follows, stores the data in the register TR, and outputs it, thereby setting the variable cap C _TR to the optimal capacity. As the voltage data applied to the variable cap C _TR , 0 is input to the register TR of the CPU 6, and the contents of the register TR are output, that is, a digital signal.
0000 is input to the D/A converter 9, and the analog signal obtained by D/A conversion is applied to the varicap _CTR . Then, input the output S ₁ obtained by comparing the outputs of the intermediate frequency amplifier 2 at this time into the register A, and judge whether it is 1 or not. If it is not Aki 1, that is, when S ₁ = 0 Add one to the contents of register TR, i.e.

[Formula] TR key after executing the routine When I was 16

[Formula] Return to Luci. In this way, registers TR
Add the contents one by one one by one, and eventually A = 1, that is, S ₁ = 1.

[Formula] According to the routine, the contents of the register TR are stored in the memory _M1 of the CPU 6. after that,

[Formula] After adding 1 to register TR according to the routine

[Formula] The routine outputs the contents of the register TR as a digital signal, sends the corresponding analog voltage to the variable cap C _TR , and then outputs the corresponding analog voltage to the comparator 5.
Input the output S ₁ of 1 to register A according to the output of 5 → A routine, and then

[Formula] When A = 1, that is YES in the routine, if TR key 16, then again

[Formula] Return to Luci. In this way, the value of register TR when S ₁ = 0, that is, A is 1, is

[Formula] Stored in the memory _M2 of the CPU 6 according to the routine. Then, the intermediate point M ₁ + M ₂ /2 between the value of memory M ₁ and that of memory M ₂ is set as the optimal tuning point and transferred to register TR.

[Formula] Enter according to the routine, and then The value of register TR in

[Formula] According to the routine, it is output as a digital signal to the D/A converter 9, and then applied to the variable cap _CTR as an optimum tuning voltage to determine the capacitance. In addition, N=800
If so, referring to Figure 8, the digital signal
0110 will be output to the D/A converter 9. Here too,

[Formula] If the judgment result of the routine is YES, that is, A=1, and

[Formula] The judgment result of the routine is YES. If it gets hot

[Formula] Store 15 in memory _M2 of CPU6 according to the routine,

[Formula] The routine is entered, and in the same way as above, a voltage is applied to the variable cap C _TR according to the value of the register TR at this time. Since the digital signal is 4 bits and the memory _M2 is also 4 bits, 15 is stored in the memory _M2 . As a result, although the voltage applied to the varicap C _TR may not necessarily give the optimum tracking point, it can reduce the tracking error to a sufficient degree for practical purposes. If we increase the number of these bits,
It will be understood that inputting 15 into memory _M2 as described above can be avoided. If we increase the number of bits like this, we get

[Formula] Although it is possible in principle to prevent A=1 from continuing until the end in a routine, it is unavoidable that the number of bits is limited in practice. Also, register RY is incremented from 0.
Even after turning 15

[Formula] If the routine continues to judge Aki1, that is, NO, and then

[Formula] In the routine, TR=16 or YES If it is determined that

[Formula] After 8 is input into register TR according to the routine

[Formula] The routine is reached and a digital signal 1000 is output from the CPU 6.
This is clear from the flowchart shown in Figure 6.

[Formula] Returns to the operation in which an analog voltage is applied to the variable cap _CTR in the same manner as in the routine. Therefore,

The [Formula] routine leads to an auxiliary routine when the contents of register A do not change when register TR is incremented, and is rarely introduced into such an auxiliary routine. Detection of the optimal tracking point can also be realized by selecting the center as described above in relation to the section in which the output of the intermediate frequency amplification circuit 2 is greater than the reference voltage; It is also possible to select such a value, and this example will be explained with reference to FIG. An A/D converter 5' is used in place of the comparison circuit 5 to convert the output of the intermediate frequency amplification circuit 2 into a digital signal according to its magnitude, and this digital signal is converted into a digital signal.
It is read by CPU6. As in the case of Figure 7,

[Formula] Luci hmm,

[Formula] According to the routine, the digital signal 0000 is converted into an analog voltage by the D/A converter 9 and then applied to the variable cap _CTR . The output of A/D converter 5' at this time is read into register A of CPU6, and then

[Formula] According to the routine, the value of register A is compared with the previously read value M in the comparison section of the CPU 6, and if the currently read value A is larger than the previously read value, that is, YES, register A The value of is stored in memory M, and the register TR is incremented by 1. Note that if the contents of the register TR are 0, the previously read value M is preset to an appropriate value, for example. That is, in Figure 9,

[Formula] Routine,

[Formula] Lou Chin each

[Formula] Routine,

[Formula] has been changed to routine, M=J It will be said that next

[Formula] According to the routine, NO That is

[Formula] Returning to the routine, the currently read value A and the previously read value M are compared in this way, and eventually

[Formula] For setting the optimal tracking point at the point where the routine becomes NO, which is considered to be the maximum point of the intermediate frequency signal.

[Formula] is introduced into the routine, and the value of the register TR at that time is output to the D/A converter 9 as the optimal tracking point. Here, despite the increment of register TR

[Formula] If the routine determines YES, 8 is input to the register TR, and the value is estimated to be the optimal tracking point and output to the D/A converter 9. This is because the digital signal 1000 has been returned to a state where it can be received according to the routine shown in FIG. 7, and it is considered that proper reception can be made. As described above, according to the present invention, tracking correction can be realized by varying the variable cap for tracking correction of the local oscillation circuit, so that a broadcast receiver can be made highly sensitive.

[Brief explanation of the drawing]

FIG. 1 shows an example of a signal tuning circuit and a local oscillation circuit before improvement according to the present invention, FIG. 2 shows an example of a signal tuning circuit and a local oscillation circuit according to the present invention, and FIG. 3 shows a high-frequency signal The response characteristics of the tuning circuit are shown, FIG. 4 is a block diagram of an embodiment of the tracking correction device for a broadcast receiver according to the present invention, and FIG. The characteristic diagram to be explained is shown, and the sixth
9 to 9 show flowcharts for explaining the above operation. 1: AM front end, 2: intermediate frequency amplification circuit, 4: PLL synthesizer section, 5: comparison circuit,
6: CPU, 8: Keyboard, 9: D/A converter,
A: Signal tuning circuit A, B: Local oscillation circuit, F: Latch circuit, G: Phase comparator, C and C _TR : Varicap.

Claims (1)

[Scope of Claims] 1. A synthesizer-type superheterodyne broadcast receiver using a PLL that controls the capacitance of a variable cap as a variable capacitance element of a high frequency tuning circuit and a local oscillation circuit, which The local oscillator circuit is provided with a variable cap as a variable capacitance element for tracking correction so that the high frequency tuning circuit can be optimally tuned, and a capacitance variable means is provided to vary the capacitance of the variable cap near the tuning point, and , a tuning determining means is provided for obtaining an output for giving a tuning point based on the intermediate frequency output obtained when varying the capacitance by the capacitance varying means, and introducing such output as a control input to the capacitance varying means; Based on the control input from
A tracking correction device for a broadcast receiver, characterized in that the capacitance variable means performs optimal tuning of the high frequency tuning circuit by controlling the capacitance of the variable cap for tracking correction.