JPH02112022A - Floating-point form multiplier - Google Patents

Abstract

PURPOSE:To realize a floating-point form multiplier which calculates an index with bias with one adder by using (1.2<n> + Yn-12<n-1> + Yn-22<n-2> +...+ Y12 + Y0) as one addition input and (Xn-12<n> + Xn-12<n-1> + Xn-22<n-2> +...+ X12 + X0) as another addition input and, at the same time, using one adder which inputs '1' as ab addition input as the operator for the exponent of multiplica tion. CONSTITUTION:A adder of an (n+1) digit is provided for making an arithmetic operation on two data to be operated of a floating-point form having exponent operands X and Y and either one of the exponent operands, for example, terms of after the 2<n-1> digit of the X are inputted as they are to one input of the adder. To the input of the 2<n-1> of X the term Xn-1 of the 2<n-1> digit of X is inputted after inversion and to the input of the 2<n> digit the term Xn-1 of the 2<n-1> of X is inputted. All terms after the 2<n-1> digit of the exponent operand Y are inputted to the other input of the adder and '1' is inputted to the input of the 2<n>-th digit. Moreover, '1' is inputted to the least significant digit carry input of the adder and (X+Y-B) is found. Therefore, the arithmetic operation on the exponent in the multiplication of a floating-point form can be performed with one adder only even when the exponent has a bias.

Description

[Detailed description of the invention] Industrial applications This invention relates to floating point type multipliers.

Conventional technology A binary number in floating point format is expressed as α=X 2 R-B β=i= y X 2 y-6. Here, x and y are mantissas, and X and Y are exponents expressed in binary numbers with bias B.

Multiplication of two numbers is αXβ= (X X y) X 21X6Y-111
-8, its mantissa is x+y, and its exponent is X+Y-B.

As shown in FIG. 5, this multiplication circuit uses a mantissa operator l to
An exponent calculator 2 calculates an exponent X+Y−B from Xy.

Conventional multipliers that perform this type of multiplication require two adders to implement this in hardware, for example,
10Y was calculated using one adder, and then (X+Y)-B was calculated using another adder.

Problems to be Solved by the Invention As mentioned above, conventional floating-point multipliers require two adders, requiring a large amount of hardware, and require the same amount of calculation time as two adders. There were drawbacks.

An object of the present invention is to provide a multiplier that enables floating-point multiplication that calculates biased exponents using a single adder, thereby reducing the amount of hardware and calculation time. .

Means for Solving the Problem The exponent part of a binary number in floating point format is often expressed as a biased binary number. In the case of a 0-digit index point, the bias B is taken as B=2r'-1-1, and the true index is x=X-
It can be expressed as B. Here, X is an exponent in biased binary representation and takes a value from 0 to 2''-1, thereby expressing the true exponent X from -(2n-'-1) to 2n-1.

When such binary numbers in floating point format are multiplied, it is necessary to obtain the exponent part of the multiplication result from the two exponent parts X and Y.

The true exponent part of floating point multiplication is the sum of the true exponent parts of the limb operations and can be expressed as (X - B) + (Y - B).

If this true exponent part is expressed in a modified form as X+Y-B)-B, it can be seen that X+Y-B is the exponent part expressed with bias B. Two adder circuits are normally required to obtain X+Y-B.

Now X :Xn-+2''-'+Xn-t2"-""
'+L2''X.

Y = Y, 1-, 2"-'+Yn-*2"-"+=-+
Y, 2+Y.

shall be.

B is B = 2n-'-1= 2''-'+2
n-3+-+2+2° note, -B = 2n+2"-
'+1 (Each digit of B was inverted and 1 was added to the LSB. Also extended by one digit.) Therefore, X+Y-B = O-2"+Y, 1-.2r'-'+Y
n-, 2″-′+-+Y, 2+Y.

+ 1-2"+(1+X,,)2n-'+X,,2''
-'+...+st2+Xo+〇"2+Yn-12''1-1+Yn-t2n-2t2
“Y.

+ (1+Xn,)2''+X,, 2n-'+X, 1-t
2”+---10x, 2+'(.+1= (1-2n+Y
,,2"+Y,t2n-'+・+Y,2+YO)"((
Xn-12"X-+2n-'Xo-z2°1+-+X,
24X, )+l+ -(1). Note that the underlined term Xn-1·2n1 can be expressed as (t+xn□)·2n″.

Therefore, it is possible to perform biased floating-point format multiplication using one adder that inputs the first term and the second term in the two parentheses of equation (1).

The multiplier of the present invention that performs such an operation has two operand data in floating point format each having exponent operands X and Y, and each exponent operand is B=2n-
It is expressed as a biased binary number of '-1, and X+Y
A floating point multiplier that multiplies the two operand data by executing -B is provided with an n+1 digit adder to perform the operation, and one input of the adder is connected to either of the exponent operands. On the other hand, for example, 2″-
”Enter the terms below FN as they are, and for the 2n-1 digit input, invert the 2°-1 digit term Xn-+ of X,
Input the 2° 1-digit term X n -1 of X into the 0-digit input, and input all the terms below 2° 1-digit of the other exponent operand Y into the other input of the adder. However, 1 is input to the input of the 2'' digit, and 1 is input to the carry input to the lowest digit of the adder to obtain X+Y-B.

Although the above-described configuration is based on positive logic, negative logic is also included within the technical scope of the present invention.

According to the present invention, the hardware is reduced by one adder compared to the conventional one, and the time required to add X+Y in the conventional method is reduced to 0.
I can do it.

Embodiment The adder 10 shown in FIG. 1 that calculates the exponent part receives the brightest term (2) in parentheses in equation (1) as one addition input.
n+yn-+2n-'+-yo)h<Terminal 1. Y, , ,Y,−1Y, and as the other input, the term in the second parentheses (Xn−+
2n+Xn-+2n-'+-...Xo) are supplied to the terminals Xn-1+Xn-1...Xo. Xn
-1, an inverter 5 is provided. 1 is applied to the carry input terminal.

The adder shown in FIG. 1 calculates equation (1), and as a result, calculates the exponent part X+Y-B of the calculation α×β.

The adder 10 in FIG. 1 is provided with full adders 20 for adding inputs a and b for the required bits as shown in FIG. The carry of the full adder is carried out manually. The a and b inputs of the k-th bit (k=1, 2.3...n) full adder contain the value Xk of the second bit.

Yk is applied.

Each full adder 20 may be configured by connecting an inverter (1), an AND gate A, and an OR gate 0 as shown in FIG. 3, or connect an exclusive OR EX, an AND gate A, and an OR gate 0 as shown in FIG. 4. I can give an example of what I did.

Further, the adder may use a carry lookahead generation circuit shown in FIG.

The exponent part is calculated using the above-mentioned adder, the mantissa part is calculated using various known multipliers, and the desired floating-point multiplication result is obtained by combining the mantissa part and the exponent part.

Effects of the Invention As detailed above, the present invention allows calculation of the exponent part in floating-point multiplication with a single adder even in the case of bias, reducing the number of hardware components, and Computation speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the invention, FIG. 2 is a block diagram showing a detailed example of the embodiment shown in FIG. 1, and FIGS. 3 to 5 are used for the example shown in FIG. FIG. 6 is a circuit diagram showing a specific example of a full adder, and FIG. 6 is a block diagram showing an example of a floating-point multiplier. 1... Mantissa part, 2... Exponent part, 10... Adder,
20...Full adder.

Claims (1)

[Claims] (1) (1・2^n+Y_n_-_12^n^-^1+
Y_n_-_22^n^-^2+...+Y_12+Y
_0) as one addition input, (X_n_-_12＾n+@
X_n_-_1@2^n^-^1+X_n_-_22^
n^-^2+...+X_12+X_0) as the other addition input, and one adder having 1 as the addition input is used as an arithmetic unit for the exponent part of floating-point multiplication. Multiplier of the form.