JPH0211185B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error detection circuit using a majority set cyclic code error decoding method. More specifically, the present invention relates to an error detection circuit for character code broadcasting in which digitally coded character information is multiplexed transmitted during the vertical blanking period of a television signal and then displayed on a home television receiver or the like. be.

The decoding method using general majority difference set cyclic codes is a well-known technique, and is described, for example, in "Coding Theory" (published by Shokodo, by Miyagawa, Iwadare, and Imai, p.287-p.290). .

Traditionally, in Japanese character code broadcasting, it has been considered best to use the (272, 190) code as an error correction method. This is clear from Japanese Patent Application No. 58-6579 (Japanese Unexamined Patent Publication No. 59-133751) entitled ``Error Correction Decoding System'' filed by the present applicant. In other words, this application relates to an error correction decoding system that attempts to recover as much as possible by correcting bit errors that occur in the transmission path, in which data bits 273, 273,
Using a signal with 191 information bits and 82 parity bits, one bit is reduced from this signal,
One packet consists of 272 bits, and data bits
272, a data signal of 190 information bits and 82 parity bits is formed and transmitted, and the transmitted data signal is multiplied by a matrix in which all predetermined columns are 1, thereby increasing the error correction probability and decoding the information. The purpose is to make it possible.

Using the basic error correction decoding method proposed in the above-mentioned Japanese Patent Application No. 1986-6579, it is possible to correct 8-bit errors in one packet (272 bits), but errors of 9 bits or more cannot be corrected. The problem was that it could hardly be corrected.

Another improved error correction decoding method proposed in the above-mentioned application (i.e., when errors cannot be corrected, errors of 9 bits or more can be corrected by shifting the first bit). The disadvantage of this method was that the processing time was too long.

Therefore, in Japanese Patent Application No. 58-54002 filed by the present applicant, in order to improve the error correction ability and at the same time reduce the processing time, the applicant proposed a majority decision circuit using a majority difference set cyclic code, a syndrome register, and a data register. In the error correction decoding system, a subtraction circuit is added to the majority decision circuit, and the decision threshold of the majority decision circuit is set to a specific value within the number of input elements of the majority decision circuit, and after cyclic correction, sequential correction is performed from the decision threshold via the subtraction circuit. The gist is to perform corrective decoding by subtracting a specific number from the threshold value until the determination threshold value reaches a predetermined value.

However, all of the above-mentioned methods have the disadvantage that undetectable errors occur.

In view of the above-mentioned points, an object of the present invention is to reduce the probability of error correction by treating it as error detection even when error correction detection in character code broadcasting is impossible and when the number of error correction bits is large. An object of the present invention is to provide an error detection circuit.

In order to achieve such an object, in the present invention, in an error correction circuit for character code broadcasting using a majority-set cyclic code error decoding system, the number of error correction bits generated from a syndrome register during cyclic correction is counted, and the number of error correction bits generated from a syndrome register is calculated. When the count value reaches a specific value or more, even if the syndrome registers are all zero, a means is provided to determine that an error has been detected, so as to reduce typographical errors.

The present invention will be explained in detail below with reference to the drawings.

First, a first embodiment of the present invention will be described with reference to FIGS. 1 to 3.

Here, FIG. 1 shows an embodiment of an error detection circuit to which the present invention is applied.

FIG. 2 is a simulation diagram showing the difference in correction ability depending on the initial threshold value when correction is performed by lowering the threshold value sequentially. Here, l is the initial threshold of the majority logic.

FIG. 3 is a flowchart showing the entire control procedure in the first embodiment of the present invention. here,*
The marks are steps that indicate CPU operations. In other steps, the circuit operates automatically. Note that each step shown in this figure will be described in conjunction with the explanation of FIG. 1 below.

In Figure 1, 100 is the central processing unit CPU
(not shown), 101 is a parallel (P/
S)/Series to parallel (S/P) conversion circuit, 102 is a selector, 103 is a data register (272 bits), 10
4 is a modulo-2 adder, 105 is an input port of the CPU, 106 is a gate, 107 is a modulo-2 adder, 108 is a timing generator, 10
9 is syndrome register (82 bits), 110
is a majority logic circuit, 111 is an error detection circuit, 11
2 is a clock signal, 113 is data before error correction, 114 is data after error correction, 115 is a reset signal, 116 is a load signal, 117 is a fetch signal, 118 is an error status signal, 119
is a ready signal, 120 is a data load control signal,
121 is a data load pulse signal, 122 is a data load clock signal, 123 is an error correction gate signal, 124 is an error correction signal, 125 is a syndrome shift clock signal, 126 is a fetch clock signal, 127 is serial load data, 1
28 represents cyclic data, 129 a syndrome register signal, 130 a threshold reduction signal, and 131 an uncorrectable error signal.

When the CPU receives a packet signal, it begins error correction processing for the packet signal. First, a reset signal 115 is issued and the syndrome register 109 is reset.
The timing generator 108 is set to the initial state, the threshold value of the majority logic circuit 110 is set to the initial state of "17", and the error correction counter of the error detection circuit 111 is set to "0". , and prepare for data loading.

Next, the CPU receives the received packet signal (i.e.
The data 113) before error correction is transferred to the parallel-to-serial conversion circuit 10.
Load to 1. When the conversion circuit 101 is for 8 bits, it is loaded 34 times, and when it is for 16 bits, it is loaded only 17 times. The load timing is performed in response to the load signal 116.

Timing generator 108 receives load signal 1
16, the data load pulse signal 12 is received.
1, the data 113 before error correction is set in the register of the conversion circuit 101, and in response to the data load clock signal 122, the data of the conversion circuit 101 is led to the data register 103 and the syndrome register 109. At this time, the gate 106 is controlled by the data load control signal 120 to allow the serial load data 127 to pass through, and the data selector 102 is set to a mode in which the serial load data 127 is selected. Of course, when the conversion circuit 101 is 8 bits, the number of pulses of the load clock signal is 8 bits, and the number of pulses of the load clock signal is 8 bits.
When 01 is 16 bits, the number of pulses of the load clock signal is 16 bits. At this time of loading, the error correction gate signal 123 inhibits the majority logic circuit 110, and the error correction signal 123 inhibits the majority logic circuit 110.
24 is not out.

Once all data is loaded into data register 103 and syndrome register 109, the circuit automatically enters error correction operation. The first time, in response to the control signal (error correction gate signal) 123, the majority circuit 11
0 operates and outputs an error correction signal 124. If there is no error at all from the beginning, the error detection circuit 11
1 detects no error from the syndrome register signal 129 by the logical sum thereof, and does not enter the error correction operation. CPU error status signal 118
When the packet is detected, it is determined that there is no error, and the received packet signal in the CPU is used as is for decoding.

The clock signal during error correction is provided by data load clock signal 122. 1st round 272
When a bit clock signal is output, only the syndrome register 109 is set to 1 by the 1-bit clock of the syndrome shift clock signal 125.
A bit shift is performed. At this time, the error correction gate signal 123 is turned off and error correction is not performed. The reason is that the frequency of the syndrome is 273,
This is because the data cycle is different from 272. If all errors have been corrected in this first round, the error status signal 118 indicates no error, and the ready signal 119 prompts the CPU to fetch data. Therefore,
The CPU only needs to constantly monitor the ready signal 119. Alternatively, this ready signal 119 may be supplied to the interrupt control line to notify the CPU.

The error-corrected data (circular data) 128 that has passed through the modulo-2 adder 104 is loaded again into the data register 103 via the data selector 102. Further, the error detection circuit 111 includes a counter that counts the error correction signal 124,
The configuration is such that an error correction impossible signal 131 is output when the counter indicates "12". When this error correction impossible signal 131 is being sent, the error status signal 118 is also configured to always indicate error detection.

The timing generator 108, which has received the error uncorrectable signal 131, outputs a ready signal 119 at the point where one round of bit shifting is completed. The CPU tries to import data, but
By looking at the error status signal 118, it is determined that there is an error, and the packet is not used.

When error correction by one round of data shift is not completed (that is, syndrome register 1
09 are not all "0" or the error correction signal is not output 12 times or more), the threshold of the majority logic circuit 110 is set by the threshold subtraction signal 130 from the timing generator 108. The same operation as last time is performed with the value set to "-1", that is, "16". By repeating such circuit operations, if error correction cannot be completely performed during the process, the threshold value is successively lowered until the calculation of the original threshold value "9" is completed. If the error status signal 118 does not indicate no error at this point, an error has been detected and this data is not used. At this time as well, the ready signal 119 and error status signal 118 inform the CPU of the error detection.

If the error correction ends midway (that is, when the syndrome register is all "0" and the error correction signal is output 12 times or less), the ready signal 119 is output at the same time as the 272-bit shift at that threshold value is completed. is output, and the error status signal 118 notifies the CPU that all corrections have been made.

The reason why the count number of the error correction signal is fixed at "12" and used for error detection is that with the method of correcting errors by sequentially lowering the threshold, it is possible to correct errors of 10 bits or less in almost all cases. This is because 90% of 11-bit errors can be corrected. Second
The figure shows the results of computer simulation.

When the error correction is completed (that is, when the syndrome register 109 is all "0" and the error correction count is "11" or less), the CPU issues a fetch signal and begins to take in the data after the error correction. Ready signal 119 by fetch signal
indicates a temporary busy state, but the serial-to-parallel conversion circuit 101
When the data is set, the ready signal 119 is shown again. Look at this ready signal 119,
The CPU takes in data from the conversion circuit 101. Since the required data has a length of 190 bits,
Fetch signals are generated 24 times when fetching every 8 bits, and 12 times when fetching every 16 bits. After the CPU captures 190 bits of data, it interprets and displays the data, and then begins the next packet reception process.

The above is an explanation of the operation of the first embodiment of the present invention.

Next, a second embodiment of the present invention will be described.

In the first embodiment described above, it is determined whether or not error correction has been performed correctly using the syndrome register 1.
09 are all "0" and the error correction count number is "11" or less, but by increasing the limit on the error count number or making it variable, the packet signal can be correctly corrected and restored. The probability can be increased. However, in this case, the probability of erroneous restoration increases, so CRC (Cyclic
It becomes necessary to have a function to detect errors in the data section using Redundancy Check).

FIG. 4 shows a second embodiment of the error detection circuit according to the present invention. Here, 400 is an encoder, 40
1 is a counter, 402 is a comparator, 403 is an OR circuit, 404 is a signal from a push button switch (not shown) indicating "11", 405, 40
6, 407 are signals from the push button switches indicating "12", "13", and "14", respectively; 408 is a signal from the push button switch indicating no limit; 409
is the same reset signal as signal 115 shown in FIG.
10 is the same error correction signal as the signal 124 shown in the first diagram, and 411 to 414 are the push button signals 4 described above.
Encode signals 04 to 407, 415 the output signal of the counter 401, 416 (signal 13 in FIG.
1) represents an error detection signal based on the number of error corrections, and 417 represents an error detection signal from the syndrome register detected by the signal 129 shown in the first diagram.

A designated one of the push button signals 404 to 408 becomes "1" by an external switch, thereby designating a threshold level for determining error detection. For example, push button signal 404
If is "1", encoded signals 411-414 passed through encoder 400 represent "11". That is, the signal 411 is "1", the signal 412 is "1", the signal 413 is "0", and the signal 414 is "1".
becomes. These encoded signals 411 to 414 are
This becomes one input signal of the comparator 402.

409 is a reset signal, which is output at the start of error correction. This reset signal 409 sets the counter 401 to the initial state of "0". When the packet signal error correction operation starts in this state,
To perform error correction, a counter input signal (i.e., an error correction signal) arrives and the counter 401
count up. Then, when the count number becomes larger than the value specified by the encode signals 411 to 414, the comparator output signal 16 becomes "1". Furthermore, even if the error detection signal 417 from the syndrome register is "0" (that is, when the syndrome register is "0"),
The comparator output signal 416 that has passed through the OR circuit 403 is directly converted to the error status signal 11.
8 as a "1", indicating error detection.

Push button signal 408 indicating no limit is “1”
In this case, the error detection function is stopped as a special case. That is, one value of the input to the comparator 402 is set to a value exceeding "272", or the output signal 41 of the comparator 402 is set to a value exceeding "272".
6 is directly controlled so that it does not become "1". This makes conventional error correction circuits (e.g.
The same operation as in the above-mentioned Japanese Patent Application No. 58-54002) is also possible. In this case, the probability of error correction increases, but naturally the probability of error correction also increases. Therefore, the error detection function using CRC described in the main text becomes even more important.

In the above explanation, the push button signals 404 to 40
We used the method of increasing the designated value of 7 from "11" to "+1", but in the same way, we configured it to be "+2", "+3", "+4", etc., and changed the designated number to 5 instead of 4. Of course, you can obtain the same functionality even if you specify more or less than three. Further, it is natural that the same effect can be obtained by using a configuration in which the CPU can issue an instruction to specify the push button signals 404 to 408.

Furthermore, a third embodiment of the present invention will be described.

In the second embodiment described above, the error detection signal 41
6 and 417 as separate flags,
A similar effect can be obtained by notifying the CPU of each. On the CPU side, it is up to the user's program to decide whether to use only the error detection signal 417 from the syndrome register for error detection, or whether to make error detection decisions including information on the error detection signal 416 based on the number of error corrections. It is possible to choose.

Finally, a fourth embodiment of the present invention will be described.

In the third embodiment described above, the error detection signal 41
6, the output data of the counter 401 is
By configuring the data so that it can be directly decoded on the CPU side, software can determine whether or not to use the error-corrected data. In cases such as the framing timing detection shown in Japanese Patent Application No. 160523/1983 filed by the present applicant, the threshold level should be changed from that used for normal packet signal error detection. In this case, the CPU can determine whether the framing timing is appropriate or not by simply reading the count number, together with the error detection signal 417, using a program. In this case, of course, no comparison is performed by the comparator, so error correction is performed until the end (that is, up to the threshold value "9"). Furthermore, by constantly counting and managing the error detection rate using software, it is possible to control the threshold level of error detection, thereby keeping the probability of error correction constant to some extent regardless of the reception environment. Furthermore, there is an advantage that the information on the error correction count number can be used as feedback information to the slice level adjustment and sample phase adjustment of the signal identification circuit in the character code broadcast receiving apparatus and the waveform equalizer.

Each of the above-mentioned embodiments is disclosed in the previously mentioned patent application No. 58-54002.
Since it is based on the error correction circuit shown in the issue,
Even if the initial value of the threshold level in the majority circuit is set to ``13'' which can obtain almost the same correction effect instead of ``17'', or the variable level of the threshold value is set to ``-1''. Without, “-2”,
Even if it is set to "-3", etc., error correction at a certain threshold level is repeated until there is no more error correction operation, and the threshold value is subtracted only after the error correction signal is no longer output. Almost the same error correction effect can be obtained by the above methods.

As described in detail above, by implementing the present invention, it is possible to obtain an overview of the count number of error correction bits, and therefore it is possible to achieve the effect of reducing the probability of error correction.

Next, the effects of each example will be listed.

In the first embodiment, the error detection from the syndrome register and the error detection by counting the error correction bits are logically summed and notified to the CPU as a flag, so the circuit and program can be easily configured. There is an advantage.

In the second embodiment, the threshold value for the count number of error correction bits in the first embodiment is made variable and specified externally by a push button, a volume containing an A/D converter, or the CPU, and reception is performed. At points where conditions are poor, the threshold for the number of error correction bits counted is increased. This makes it possible to increase the reception probability at points with poor reception conditions.

In the third embodiment, error detection from the syndrome register and error detection by counting error correction bits are notified to the CPU as separate flags, and the CPU makes the determination of error detection. Depending on the purpose of use, it is also possible to ignore error detection by counting error correction bits.

In the fourth embodiment, the CPU is configured to directly read the counter output indicating the count number of error correction bits, and the threshold value for error detection is determined by software. Further, information on the error correction count number can be input to a signal identification circuit and a waveform equalizer. In this case,
It is no longer necessary to directly specify a threshold value using a push button or to specify a threshold value from the CPU as one input to the comparator. When this comparison input is input as a status signal to the CPU, it is possible to create a configuration similar to the first to third embodiments by comparing it with a counter output by software.

As explained above, in the present invention, when the number of error correction bits is counted and the number of bits is large,
Even if the contents of the syndrome register are all “0”
Even if it is, it is treated as error detection, thereby reducing the probability of error correction. According to the present invention, not only all other error correction codes based on majority logic, but also other signals can be provided with a similar error detection function.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of an error detection circuit to which the present invention is applied, FIG. 2 is a diagram showing the packet correct reception rate after error correction by computer simulation, and FIG. FIG. 4 is a flowchart for explaining the operation shown in FIG. 4, and is a block diagram showing another embodiment of the error detection circuit. 100...Output port, 101...P/S,
S/P conversion circuit, 102...Selector, 103...
...data register, 104...adder modulo 2, 105...input port, 106...gate,
107...Adder modulo 2, 108...Timing generator, 109...Syndrome register, 110...Majority logic circuit, 111...
Error detection circuit, 112...Clock signal, 113
...Data before error correction, 114...Data after error correction, 115...Reset signal, 116...
Load signal, 117...Fetch signal, 118...
...Error status signal, 119...Ready signal, 120...Data load control signal, 121...
...Data load pulse signal, 122...Data load clock signal, 123...Error correction gate signal, 124...Error correction signal, 125...Syndrome shift clock signal, 126...Fetch clock signal, 127... Serial load data, 128... Circulating data, 129... Syndrome register signal, 130... Threshold reduction signal, 131... Error correctable signal, 400... Encoder, 401... Counter, 402... Comparator, 403 ...OR circuit, 404...
Push button signal indicating "11", 405..."12"
406...Push button signal indicating "13", 407...Push button signal indicating "14", 408...Push button signal indicating no limit, 409...Reset signal, 410... ...Error correction signal, 411-414...404-407
415... Output signal of the counter 401, 416... Error detection signal based on the number of error corrections, 417... Error detection signal from the syndrome register.

Claims (1)

[Claims] 1. In an error correction circuit for character code broadcasting using a majority-set cyclic code error decoding method, the number of error correction bits generated from a syndrome register during cyclic correction is counted, and the counted value is specified. An error detection circuit characterized in that the error detection circuit is provided with means for determining an error detection when the syndrome register reaches a value equal to or higher than a value, even if the syndrome registers are all zero, thereby reducing typographical errors. 2. The error detection circuit according to claim 1, wherein the specific value is changed according to external reception conditions.