JPH07202719A - Decoder for error correction code - Google Patents

Abstract

PURPOSE:To always keep a decoding characteristic of an error correction code obtained through multiple coding of digital information in a best state without being deteriorated by timewise fluctuation of an erroneous state. CONSTITUTION:In the decoder that decodes an error correction code subjected to multiple coding such as a product code comprising, e.g. two kinds of codes by using a 1st decoding means and a 2nd decoding means, the 1st decoding means is provided with an error number detection circuit 101 counting an error check result of each code word obtained by the 1st decoding means and circuits 102, 103 controlling the additional mode of suitable reliability information based on the count when the reliability of an error added by the 1st decoding means is expressed in at least three stages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to the transmission of digital information.
The present invention relates to a decoding device for a multi-coded error correction code that detects and corrects the error during recording / reproduction, and particularly to a decoding device for a product code.

[0002]

2. Description of the Related Art Generally, in a digital information recording / reproducing error correction system, a product code as shown in FIGS. 2 (a) and 2 (b) is used. This product code is configured by combining the codes in two stages, whereby it is possible to obtain a correction capability equivalent to that of a code having a long minimum Hamming distance and a high correction capability, and the calculation procedure of decoding in each stage is relatively easy. It has features. The Reed-Solomon code is often used as the code for each stage.

In the example shown in FIG. 2A, C ₁ (n ₁ ,
k ₁ ) code, and C ₂ (n ₂ , k ₂ ) code (n ₁ ,
n _2: code length, k _1, k _2: is a product code consisting of information code length). The code length and the information code length are in symbol units, and one symbol is 8 bits. In the case of FIG. 2 (a),
It has the feature that the lengths n ₁ and n ₂ of the code words of the C1 and C2 codes can be set independently and freely. FIG. 2B is a product code having a C1 code in the vertical direction and a C2 code in the diagonal direction. In the case of FIG. 2B, the length of L in the horizontal direction (the number of code words) can be freely set.

Generally, on the encoding side, C2 is encoded first and C1 is encoded second. In the following, recording / playback is 1
It is assumed that the symbols of one C1 code word are sequentially recorded and reproduced. Now, assuming that the minimum Hamming distances of C1 and C2 are d ₁ and d ₂ , respectively,
The minimum Hamming distance of this product code is d ₁ d ₂ , and errors can be detected up to (d ₁ d ₂ -1) symbols, and (d ₁ d ₂
It can correct up to -1) / 2 symbols.

FIG. 3 shows a simple block diagram of encoding / decoding of a general product code, and an encoding / decoding process taking FIG. 2 (a) as an example. 301 is a C2 encoder which is a first stage encoder, 302 is a C1 encoder which is a second stage encoder, 303 is a communication channel, and 304 is a C which is a first stage decoder.
1 decoder, 305 is a C2 decoder which is a second stage decoder.

The k ₂ × k ₁ blocked original information is
On the encoding side, the C2 encoder 30 which is the first stage encoder
C1 parity is added by 1 to form an n ₂ × k ₁ block. Next, the C1 encoder 30 which is the second stage encoder
By 2, C1 parity is added and the block becomes n ₂ × n ₁ and the encoding is completed. On the decoding side, the C1 decoder 304, which is the first stage decoder, detects and corrects the error. In the C1 decoder 304, since the distance is d ₁ , (d ₁
-1) Symbol error detection and error correction up to (d ₁ -1) / 2 symbols are possible.

At this time, a flag is added to each code word according to the result of the judgment and correction of the number of errors. Then, this flag is combined with the C1 decoding result and the C2 decoder 30 which is the second stage decoder
Send to 5.

The C2 decoder 305 determines the number of errors from the C2 code. The minimum Hamming distance is d only with the C2 code.
_Since it is ₂ , error detection up to (d ₂ −1) symbols,
It is possible to correct up to (d ₂ -1) / 2 symbols. Further, by treating the symbol to which the C1 flag is added as erasure (error whose position is known), error correction (erasure correction) up to (d ₂ −1) symbols becomes possible. C1 decoder 304 determines what kind of correction is performed by C2 decoder 305.
It is determined by referring to the C1 flag sent from. By performing the decoding in this way, an original information block of k ₂ × k ₁ can be obtained.

There are missed probabilities and uncorrectable probabilities for evaluating the characteristics of the decoding result. The missed probability is the probability that the error symbol is mistaken for a correct symbol. In a digital VTR or the like, this oversight causes an error to appear directly on the screen. The uncorrectability probability is the probability that the number of errors exceeds the correction capability and the errors cannot be corrected. When correction is impossible with a digital VTR or the like, information close to the original information can be obtained by performing interpolation or the like from the information of the peripheral pixels.
The lower the missed probability and the uncorrectable probability are,
Good decoding characteristics.

In a digital information recording / reproducing system, there are random errors, burst errors, and composite errors in which the two are mixed. The state of these errors is not constant but fluctuates in time. In the past, such a temporal variation of the error state was not considered so much. In other words, with C1 decoding,
These conditions have been fixed such as how to correct and add a flag, and how to correct from the C1 flag sent by the C2 decoder. Therefore, as shown in FIG. 4, the decoding mode 1 in which the miss probability and the uncorrectability probability are low (the decoding characteristic is good) in the error state A is the error state B.
Then, the miss-over probability and the uncorrectable probability become high (the decoding characteristics are bad), and conversely, in the error mode A, the overlook-probability and the uncorrectable probability become high in the decoding mode 2 in which the miss-over probability and the uncorrectable probability are low. That happens.
As described above, the conventional fixed decoding method has a drawback that the decoding characteristic may be deteriorated due to the change of the error state, and the image quality is deteriorated in the digital VTR or the like.

[0011]

As described above, since the decoding method is fixed in the prior art, it is not possible to adapt to the time-varying error state, and the decoding characteristic deteriorates depending on the changing error state. Therefore, the digital VTR or the like has a problem that the image quality is deteriorated. The present invention has been made to solve such a conventional problem, and an object of the present invention is to prevent deterioration of decoding characteristics due to temporal variation of error states and to always obtain the best decoding characteristics. Another object of the present invention is to provide a decoding device for correct error correction code.

[0012]

In order to achieve the above-mentioned object, the present invention provides a code obtained by multiple-coding digital information by at least two of a first decoding means and a second decoding means.
In the error correction code decoding device for decoding in steps, the first decoding means is configured to detect the reliability information for an error added by the first decoding means in at least three steps. A control means for controlling the addition mode of the reliability information of the first decoding means based on the error detection information obtained by the first decoding means.

Alternatively, the present invention converts digital information into C2.
(N ₂ , k ₂ ) code and C1 (n ₁ , k ₁ ) code (n ₁ ,
In the decoding device of the error correction code, the product code encoded in two stages of (n ₂ is the code length, k ₁ and k ₂ are the information code length) is decoded by the C1 decoding means and the C2 decoding means,
The C1 decoding means counts the error detection result of each codeword obtained from the C1 decoding means when the C1 flag added at the time of C1 decoding is at least 2 bits, and the counting means outputs the result. Control means for controlling the addition mode of the C1 flag on the basis of the counted value.

[0014]

That is, according to the present invention, when the code obtained by multiple-coding digital information is decoded in at least two stages of the first decoding means and the second decoding means, the first decoding means adds it. When the reliability information for the error is expressed in at least three stages, the addition mode of the reliability information of the first decoding means is controlled from the error detection information obtained by the first decoding means.

Alternatively, the present invention converts the digital information into C2.
(N ₂ , k ₂ ) code and C1 (n ₁ , k ₁ ) code (n ₁ ,
When a product code encoded in two stages of (n ₂ is a code length and k ₁ and k ₂ are information code lengths) is decoded by the C1 decoding means and the C2 decoding means, the C1 flag added at the time of C1 decoding is at least 2 If it is a bit, the error detection result of each code word obtained from the C1 decoding means is counted, and the addition mode of the C1 flag is controlled based on the obtained count value.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. In the figure, 101 is an error number determination circuit that determines the number of errors from the received word of the inner code, and 102 is a flag addition that determines how many errors should be added as a result of the error number determination. Mode determination circuit, 103
Is a flag addition control circuit that controls the flag addition circuit 104 in response to the result from the flag addition mode determination circuit 102, 104 is a flag addition circuit that adds a flag to the codeword whose error has been corrected, and 105 is an error flag. An error position / numerical calculation circuit 106 for calculating the position and size receives the result from the error position / numerical calculation, and an error correction execution circuit 107.
An error correction control circuit 108 for controlling a buffer memory 108 is a buffer memory 108 for delaying the time until the received word is corrected.

Here, the flag addition mode determination, which is a feature of the present embodiment, will be described by taking the case of FIG. 2A as an example. Now, assume that the code length of C1 is n ₁ , the number of information symbols is k ₁ , and the maximum error-correctable number is t ₁ . However, d ₁ = 2t ₁ +
Set to 1. The number of errors in the code sent through the transmission line is first determined by the first C1 decoder. At that time, C
A determination result of a 2-bit error number is obtained for each codeword. Here, the value of the determination result of the number of errors is that the minimum Hamming distance is d ₁ ,

0 ... C1 code word is determined to have no symbol error 1 ... C1 code word is determined to be a 1-symbol error 2 ... C1 code word is determined to be a 2-symbol error: t ₁ +1 ... C1 It is determined that the code word has an error of t ₁ +1 symbols or more. The determination result of the error number of C1 can be represented by a plurality of bits.

The value of the determination result of the number of errors is i (i = 0
.About.t ₁ +1), the number of C1 code words, N (i), is obtained for each block of the product code. In the present embodiment, the flag in the C1 decoder is determined (the maximum number of error corrections in the C2 decoder is determined) from the error number determination result obtained by the error number detection circuit in FIG. 1 according to steps S1 to S6 of the flowchart in FIG. Determine the method of adding. The flag added by the C1 decoder is 2 bits.

Here, ζ in FIG. 5 is a constant.
However, in the flowchart, the occurrence probability F of the number of errors (hereinafter, the number of error determinations) i in one codeword determined at the time of decoding F
It is represented by (i). That is, F (i) is i in the C1 decoder.
(I = 0 to t ₁ +1) is the probability of being judged as an error.
However, F (t ₁ +1) is the probability that more than t ₁ +1 errors are determined. For example, N (i) can be obtained by multiplying the number of C1 code words in the product code block by F (i). Therefore, F (i) and N (i) can be treated in the same way. Below, it demonstrates by probability.

Generally, in a C1 decoder, the occurrence probability F (i) of the number of errors (hereinafter referred to as the number of error determinations) i in one codeword determined at the time of decoding is F (i) = FM (i ) + relationship that FJ (i) (i = 0~t 1) ... (1-1). Here, FM (i) is the probability of erroneously determining the number of symbol errors at the time of decoding into different numbers i, and FJ (i) is the probability of correct determination of i errors.

In the C1 decoder, a flag is added according to the number of detected errors. However, since the flag has 2 bits, the reliability level is expressed in three levels as shown in Table 1.

[0023]

[Table 1]

Therefore, the number of errors to add a flag is two (hereinafter, flag addition boundary condition). Therefore, it is assumed that one of the flag addition boundary conditions is added with t ₁ or more errors. Below, the remaining flag addition boundary conditions (conditions for adding a small number of flags with few errors)
The determination of will be described. Here, a flag addition boundary condition for determining rp is set. When rp = 0, it is meaningless because the flag addition rate becomes 100%. Therefore r
The range of p may be considered as 1 ≦ rp ≦ t ₁ .

Now, in FM (i) of the equation (2-2), FM (0): error of d1 symbols or more → 0 symbol error (no error) FM (1): error of (d1-1) symbols or more → 1 symbol error FM (2) :( d1-2) or more symbols error → 2 symbol error: FM (t ₁₎ there is a :( d1-t ₁₎ or more symbols error → t symbol error.

In general, the largest in FM (i) is F
At M (t ₁ ), FM (i) has FM (t ₁ > FM (t ₁ −1)>...> FM (2)> FM (1)> FM
(0) There is a relationship.

[0027]

[Equation 1]

[0028]

[Equation 2]

[0029]

[Equation 3]

The probability FE (i) that an i-symbol error is determined and the symbol is erroneous after decoding is smaller as the erroneous determination probability FM (i) is smaller. Therefore, the smaller i is, the smaller FE (i) is. Poe, which is missed in the state probability of the symbol after decoding, is

[0031]

[Equation 4]

Is calculated by As a result, miss probability Poe
Becomes smaller as the flag addition boundary condition rp becomes smaller, regardless of the code length, the minimum Hamming distance, and the error state. That is, if only the missed point (POe) is considered, rp
The smaller is the better.

However, the flag addition rate P1 of Level1
Is represented by the following equation. P1 = F (rp) + F (rp + 1) + ... F (t 1 -1) In other words, the flag addition ratio P1 as rp is smaller becomes higher. The flag addition rate P2 of Level2 is

[0034]

[Equation 5]

It is represented by Here, if only the missed probability is lowered, the lowest value is obtained by setting rp = 1. Now, if you want to make P1 as low as possible,

[0036]

[Equation 6]

When the condition is satisfied, it can be considered that P1 is not so large even if a flag is added with one or more errors. On the other hand, if F (1) + F (O) >> F (O), P1 is considered to be large, so it is better not to add a flag with one or more errors. In the same way,

[0038]

[Equation 7]

At the time of, rp = x may be set. From the above,
A flowchart for determining the flag addition boundary condition rp is as shown in FIG. Where ζ is a constant,
0.1 to 0.2 is preferable, but other values may be used depending on the case.

According to the flowchart of FIG. 5, rp = 1
Is set as an initial value and rp is increased so that the flag addition rate P1 does not increase, so that the overlook probability Poe can be reduced.

Next, the case where the minimum Hamming distance is an even number will be described. Similarly to the case of an odd number, if the minimum Hamming distance d ₁ is set, the maximum error correctable number t is t = (d ₁ −2) / 2. Therefore, the conditional expression for determining the flag addition boundary condition rp is the same as when d ₁ is an odd number. Therefore, rp can be determined by the flowchart of FIG.

As an example, consider the case where the minimum Hamming distance is 13. Therefore, the maximum possible number of errors that can be corrected in the C1 decoder is 6. The code length is 110
And The procedure for determining the flag addition boundary condition rp in this case will be described with reference to steps S10 to S1 in the flowchart of FIG.
8 shows. Here, the value of ζ is 0.2.

[0043]

[Table 2]

Table 2 shows the decoding result when the average symbol error rate of 10 ^{-2 is} corrected up to 6 errors with the C1 code. From the results of Table 2, C selected in the case of this error
According to the flowchart of FIG. 6, the flag addition boundary condition rp in one decoder is determined as rp = 3 as follows.

[0045]

[Equation 8]

Table 3 shows the decoding characteristics (state probability of symbols after decoding) of the C1 code when the flag addition boundary condition rp is changed. In Table 3, symbol state probabilities P2c, P2e, P1c, P1e, POc, and Poe.
Is

P2c: Probability that the flag is set to level 2 and the symbol is correct P2e: Probability that the flag is set to level 2 and the symbol is incorrect P1c: Symbol that is set to the level 1 flag and symbol Is the correct probability P1e: The symbol is flagged at level 1 and the symbol is incorrect Poc: The symbol is not flagged and the symbol is correct Poe: The symbol is not flagged and the symbol is incorrect Represents the probability.

[0048]

[Table 3]

From Table 3, when rp is 3, POe, which is the miss probability, is about 1/10 ^{5 as} compared with when rp is 4. On the other hand, the flag addition rate P1 is only about 4 times higher. When rp is 1 or 2, the miss probability is low, but the flag addition rate is about 70 to 1 as compared with the lowest rp = 5.
56 times higher. Therefore, the flag addition boundary condition rp is 3
In case (shaded portion), the overlook probability POe is made as low as possible and the flag addition rate P1
Decoding characteristics (C1 that does not increase (= P1c + P1e))
It is understood that it is the state probability of the symbol after decoding).

The optimization of this flag addition boundary condition is performed by C1
This can be done using the error detection information of the decoder. Therefore, the decoding method of the C1 code can be automatically optimized. Further, a better C1 code decoding method can be determined by obtaining short-term optimization and long-term N (i), performing optimization, and comparing the results. It is possible not only to use the number of N (i) as it is, but also to determine rp by using the ratio thereof.

As described above, in the present embodiment, when decoding the code obtained by multi-coding the digital information, the decoding mode suitable for the error state is determined from the error detection information obtained by the first decoding means. In the first decoding means in which the decoding mode is changed by the control signal sent from the determiner, the best decoding characteristic can always be obtained by decoding in the decoding mode suitable for the error state.

[0052]

As described above, according to the error correction code decoding apparatus of the present invention, a decoding method suitable for the currently generated error state can be constructed based on the judgment result of the number of errors obtained at the time of decoding. As a result, it is possible to prevent the deterioration of the decoding characteristic due to the temporal variation of the error state and always obtain the best decoding characteristic.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a decoding device to which the present invention has been applied.

FIG. 2 is an explanatory diagram showing an example of a double-coded product code.

FIG. 3 is an explanatory diagram of double encoding and decoding of an error correction code.

FIG. 4 is a characteristic diagram showing a relationship between an error state and a decoding characteristic.

FIG. 5 is a flowchart showing an operation of selecting a flag addition mode in the decoding method of this embodiment.

FIG. 6 is a flowchart showing an operation of selecting a decoding method according to this embodiment.

[Explanation of symbols]

101 ... Error number detection circuit, 102 ... Flag addition mode determination circuit, 103 ... Flag addition control circuit, 104 ... Flag addition circuit, 105 ... Error position / error numerical value calculation circuit, 1
06 ... error correction control circuit, 107 ... error correction execution circuit,
108 ... Buffer memory.

Claims (2)

[Claims] 1. An error correction code decoding apparatus for decoding a code obtained by multiple-coding digital information in at least two stages of a first decoding means and a second decoding means, wherein the first decoding means comprises: When the reliability information for the error added by the first decoding means is expressed in at least three stages, the reliability information of the first decoding means is calculated from the error detection information obtained by the first decoding means. An error correction code decoding device, comprising: a control means for controlling the additional mode of the above. 2. Digital information is represented by a C2 (n ₂ , k ₂ ) code and a C1 (n ₁ , k ₁ ) code (n ₁ , n ₂ are code lengths, k
₍₁ and k ₂ are information code lengths) In a decoding device of an error correction code which decodes a product code encoded by two steps of C1 decoding means and C2 decoding means, the C1 decoding means adds C1 decoding means. When the flag has at least 2 bits, the counting means for counting the error detection result of each code word obtained from the C1 decoding means, and the addition mode of the C1 flag are set based on the count value output from this counting means. An error correction code decoding device comprising: a control unit that controls the error correction code.