JP6552776B1 - Error correction decoding apparatus and error correction decoding method - Google Patents

Abstract

An error correction decoding apparatus (100) performs a decoding process on received data that has been error correction encoded with a systematic code, and outputs a decoding result, a turbo decoding unit (2), first data included in the received data, And a first comparison unit (3) for determining whether or not the reliability of the decoding result is high by comparing with the decoding result.

Description

  The present invention relates to an error correction decoding apparatus and an error correction decoding method.

  In conventional wireless communication systems, data is error correction coded to detect errors that occur in the transmission path. As the error correction code, a convolutional code, a turbo code, or the like in which only an information bit portion of data is obtained by decoding may be applied to the data. In this case, the error correction decoding apparatus that decodes the error correction code performs error detection on the data subjected to the error correction decoding process using an error detection code such as cyclic redundancy check (CRC), and when an error is detected, By resending the data, the reliability of the decoding result is improved. Patent Document 1 discloses an error correction decoding apparatus that performs error correction decoding using transmission data to which a CRC code is added.

JP 2010-232992 A

  However, since the data received by the error correction decoding apparatus described in Patent Document 1 includes a CRC code, there is a problem that the amount of information that can be transmitted is reduced.

  The present invention has been made in view of the above, and an object of the present invention is to provide an error correction decoding apparatus that can suppress a decrease in the amount of information that can be transmitted while determining the reliability of a decoding result.

In order to solve the problems described above and to achieve the object, the error correction decoding apparatus performs a decoding process on reception data error-correction-coded with a systematic code, and includes a decoding unit that outputs a decoding result, By comparing the decoded first data with the decoding result to determine whether the reliability of the decoding result is high or not, and it is determined that the reliability of the decoding result is low, the reliability of the decoding result is low And a selection unit for outputting any one of the data of the information bit portion included in the received data as a result of decoding according to the presence or absence of the first signal. It is characterized by that.

  The error correction decoding apparatus according to the present invention eliminates the need for redundant bits for error detection by determining the reliability of the decoding result, and has the effect of increasing the amount of information that can be transmitted.

FIG. 1 shows a configuration of a wireless communication system according to a first embodiment. FIG. 2 shows functional blocks of the error correction decoding apparatus according to the first embodiment. 1 is a diagram illustrating a control circuit according to a first embodiment; Flow chart showing the operation of the error correction decoding apparatus according to the first embodiment FIG. 6 is a diagram showing functional blocks of an error correction decoding apparatus according to a second embodiment. Flow chart showing the operation of the error correction decoding apparatus according to the second embodiment The figure which shows the functional block of the error correction decoding apparatus concerning Embodiment 3. Flowchart showing the operation of the error correction decoding apparatus according to the third embodiment The figure which shows the functional block of the error correction decoding apparatus concerning Embodiment 4. A flowchart showing the operation of the error correction decoding apparatus according to the fourth embodiment

  Hereinafter, an error correction decoding apparatus and an error correction decoding method according to an embodiment of the present invention will be described in detail based on the drawings. The present invention is not limited by the embodiment.

Embodiment 1
FIG. 1 is a diagram of a configuration of the wireless communication system according to the first embodiment. The wireless communication system 20 includes a transmission device 30 and a reception device 40. The transmission device 30 and the reception device 40 communicate with each other by a wireless method or a wired method. The transmitter 30 performs turbo coding on data, modulates the turbo-coded data, and transmits the data to the receiver 40. The receiving device 40 receives data transmitted from the transmitting device 30.

  FIG. 2 is a diagram showing functional blocks of the error correction decoding apparatus according to the first embodiment. The error correction decoding apparatus 100 is provided in the reception apparatus 40. Alternatively, the error correction decoding device 100 has a function as the reception device 40. The error correction decoding apparatus 100 includes a first storage unit 1, a turbo decoding unit 2, a first comparison unit 3, and a selection unit 4. The received data received by the error correction decoding apparatus 100 is soft decision data demodulated by the demodulator. The soft decision data is composed of hard decision data which is determined to be either 0 or 1, and a degree of reliability of the hard decision data. The demodulation unit may be included in the error correction decoding apparatus 100, or may be included in an apparatus other than the error correction decoding apparatus 100 included in the reception apparatus 40. The hard decision data is also referred to as first data. The first storage unit 1 stores information data corresponding to the information bit portion of the hard decision data. The first storage unit 1 also transmits the stored information data to the first comparison unit 3. The first comparison unit 3 is also called a comparison unit. The comparison unit determines whether the reliability of the decoding result is high by comparing the first data with the decoding result. The turbo decoding unit 2 repeatedly performs turbo decoding decoding processing on the reception data a predetermined number of times. Further, the turbo decoding unit 2 transmits the decoding result, which is the result of the decoding process, to the first comparison unit 3. The first comparison unit 3 compares the information data with the decoding result, and counts the number of inverted bits. In addition, the first comparison unit 3 determines whether the counted value is larger than a predetermined threshold. The selection unit 4 uses the transmission of the first comparison unit 3 to select and transmit any one of the information data and the decoding result.

  The turbo decoding unit 2, the first comparison unit 3, and the selection unit 4 are realized by a processing circuit which is an electronic circuit that performs each process.

  The processing circuit may be dedicated hardware or a control circuit including a memory and a CPU (Central Processing Unit) that executes a program stored in the memory. Here, the memory corresponds to, for example, a nonvolatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), or a flash memory, a magnetic disk, or an optical disk. FIG. 3 is a diagram of a control circuit according to the first embodiment. When the processing circuit is a control circuit including a CPU, this control circuit is, for example, the control circuit 200 configured as shown in FIG.

  As shown in FIG. 3, the control circuit 200 includes a processor 200a, which is a CPU, and a memory 200b. In the case of being realized by the control circuit 200 shown in FIG. 3, the processor 200a is realized by reading and executing a program corresponding to each process stored in the memory 200b. The memory 200 b is also used as a temporary memory in each process performed by the processor 200 a. The first storage unit 1 is realized by the memory 200 b.

  Next, the operation of the error correction decoding apparatus 100 will be described. FIG. 4 is a flowchart showing an operation of the error correction decoding apparatus 100 according to the first embodiment. The error correction decoding apparatus 100 receives the received data from the demodulation unit provided in the front stage of the error correction decoding apparatus 100 (step S1). The first storage unit 1 stores information data included in the received data (step S2). The turbo decoding unit 2 receives the received data, and convolves the received data with one of the information bit sequence and two convolutional coding circuits constituting the turbo encoder that performs turbo coding included in the transmission device 30. A check bit sequence in the order encoded and transmitted by the encoding circuit, and a check bit sequence encoded and transmitted by the other one of the two convolutional encoding circuits after interleaving by the transmitting device 30; It is separated into three series (step S3). These three sequences are data turbo-coded by the transmission device 30 and data to be transmitted to the error correction decoding device 100. The information bit sequence is called a first bit sequence. The check bit sequence sent by the transmitter 30 is called a second bit sequence. The check bit sequence interleaved by the transmitter 30 is referred to as a third bit sequence.

  The turbo decoding unit 2 performs a soft input / soft output decoding process using the first bit sequence and the third bit sequence to generate first information. Further, the turbo decoding unit 2 performs soft input / soft output decoding processing using the first information, the first bit sequence, and the second bit sequence (step S4). The turbo decoding unit 2 performs the process of step S4 a predetermined number of times, generates a decoding result for the reception sequence of the information bit part obtained in the last decoding process, and outputs the decoding result to the first comparison unit 3 and the selection unit 4 (step S5). The information generated in step S4 is not a final decoding result by turbo decoding. The operations from step S3 to step S5 are general turbo decoding operations. Further, in the present embodiment, the error correction decoding apparatus 100 does not perform error detection using a CRC code. When the decoding result is transmitted from the turbo decoding unit 2, the first storage unit 1 transmits information data to the first comparison unit 3 and the selection unit 4 (step S6).

  The first comparison unit 3 compares the decoding result with the information data, and counts the number of bits subjected to bit inversion (step S7). In addition, the first comparison unit 3 determines whether the counted value is larger than a predetermined threshold (step S8). If the counted value is larger than the threshold (Yes in step S8), the first signal is transmitted to the selection unit 4 (step S9). When the counted value is not larger than the threshold value (step S8, No), the first comparison unit 3 does not transmit the first signal to the selection unit 4 (step S10). The selection unit 4 determines whether the first signal has been received (step S11). When the first signal is received (step S11, Yes), the selection unit 4 transmits information data to a subsequent function unit (not shown) (step S12). When the first signal is not received (step S11, No), the selection unit 4 transmits the decoding result to a subsequent function unit (not shown) (step S13). The first signal is a signal indicating that the reliability of the decoding result is low.

  In the present embodiment, when the number of bits subjected to bit inversion is larger than a predetermined threshold value, the selection unit 4 transmits information data to a subsequent function unit. In addition to this, the first comparison unit 3 Transmits the first signal and the result of turbo decoding to the subsequent functional unit and determines whether to select information data or the decoded result of turbo decoding in the processing by the subsequent functional unit. Good.

  When the number of bits that have been bit-inverted is larger than a predetermined threshold value, in general, there is a high possibility that the turbo decoding unit 2 is performing erroneous error correction decoding, and reliability as a decoding result is low. . For this reason, when the 1st comparison part 3 transmits the 1st signal which shows that the reliability of a decoding result is low, it can suppress using the decoding result which performed the error correction erroneously. Further, the reliability of the decoding result can be determined by comparing the first data with the decoding result. Further, since the decoding process is performed without using the CRC code, the amount of information included in the received data can be increased, and a decrease in the amount of information that can be transmitted by the error correction decoding apparatus 100 can be suppressed. In this embodiment, the case where the error correction code is a turbo code has been described. However, the error correction code is not limited to a turbo code, and may be a systematic code in which a portion of information bits is output to a transmission path. . If the error correction code is a systematic code, since the correspondence between the decoding result and the received sequence can be obtained, the same effect as in the present embodiment can be obtained.

Second Embodiment
FIG. 5 is a diagram showing functional blocks of the error correction decoding apparatus according to the second embodiment. The components having the same functions as those in the first embodiment are given the same reference numerals as those in the first embodiment, and redundant description will be omitted. The error correction decoding apparatus 100 a includes a first storage unit 1, a turbo decoding unit 2, a selection unit 4, a second storage unit 5, a second comparison unit 6, and a third comparison unit 7. Is provided. The second storage unit 5 stores the reliability information of the information bit portion included in the received data. The second comparison unit 6 compares the transmission of the first storage unit 1 with the transmission of the turbo decoding unit 2 and transmits a second signal indicating a portion performing bit inversion to the third comparison unit 7 To do. The third comparison unit 7 adds the reliability information of the position determined to be bit-reversed in the second comparison unit 6 to the reliability of the information bit portion stored in the second storage unit 5 and adds It is compared whether the obtained value is larger than a predetermined threshold value. The second comparison unit 6 and the third comparison unit 7 are collectively referred to as a comparison unit. The second comparison unit 6 and the third comparison unit 7 are realized by a processing circuit which is an electronic circuit that performs each process shown in FIG. The second storage unit 5 is realized by a memory.

  Next, the operation will be described. FIG. 6 is a flowchart showing an operation of the error correction decoding apparatus 100a according to the second embodiment. The first storage unit 1 stores information data (step S21). The second storage unit 5 generates reliability information from the soft decision information of each received data, and stores the generated reliability information (step S22). The turbo decoding unit 2 repeatedly performs a predetermined number of decoding processes, generates a decoding result for the reception sequence of the information bit part from the result obtained by the last decoding process, and sends the decoding result to the second comparison unit 6 Transmit (step S23). At this time, the first storage unit 1 transmits information data to the second comparison unit 6 in accordance with the timing at which the decoding result is transmitted (step S24). The second storage unit 5 transmits the reliability information of the information bit portion of the received data to the third comparison unit 7 (step S25).

  The second comparison unit 6 compares the decoding result transmitted from the turbo decoding unit 2 with the information data stored in the first storage unit 1 (step S26). Further, the second comparison unit 6 transmits the reliability information of the position where bit inversion is performed to the third comparison unit 7 (step S27). The third comparison unit 7 adds the reliability information of the bit-inverted position to the reliability of the information bit portion stored in the second storage unit 5 and adds the information based on the value added for the data for one code. It is determined whether the calculated value is larger than a predetermined threshold (step S28). When the added value is larger than a predetermined threshold (step S28, Yse), the third comparison unit 7 transmits the first signal to the selection unit 4 (step S29). When the added value is not larger than the predetermined threshold (No at Step S28), the third comparison unit 7 does not transmit the first signal (Step S30).

  The selection unit 4 determines whether the first signal has been received (step S31). When the first signal is received (step S31, Yes), the selection unit 4 transmits the information data read from the first storage unit 1 to the subsequent function unit (step S32). When the first signal is not received (step S31, No), the selection unit 4 transmits the decoding result transmitted from the turbo decoding unit 2 to the subsequent functional unit (step S33).

  In the second embodiment, when the value obtained by adding the reliability information of the bit-inverted position is larger than a predetermined threshold value, the selection unit 4 transmits the information data to the subsequent function unit. In addition, the third comparison unit 7 transmits the first signal and the decoding result obtained by turbo decoding to the subsequent functional unit, and selects which of the information data and the decoding result is selected by the processing by the subsequent functional unit. You may make it judge.

  If the value obtained by adding the reliability information of the bit-inverted position is larger than a predetermined threshold value, there is a possibility that error correction decoding is performed more erroneously than in the case of the number of bits described in the first embodiment. It becomes high and the reliability of the decoding result becomes low. For this reason, in addition to the effect of the first embodiment, the third comparison unit 7 transmits the first signal indicating that the reliability of the decoding result is low, and the decoding result obtained by performing erroneous error correction is used. It is possible to suppress the degradation of the reliability of the decoding result.

Third Embodiment
FIG. 7 is a diagram showing functional blocks of the error correction decoding apparatus according to the third embodiment. The components having the same functions as those in the first embodiment are given the same reference numerals as those in the first embodiment, and redundant description will be omitted. The error correction decoding apparatus 100b includes a turbo decoding unit 2, a first comparison unit 3, a selection unit 4, a third storage unit 8, an information bit selection unit 9, and a re-encoding unit 10. . The third storage unit 8 stores second data including information bits and check bits of the received data. The information bit selection unit 9 selects an information bit portion, that is, information data from the second data read from the third storage unit 8, and transmits the information data to the selection unit 4. The re-coding unit 10 performs turbo coding again on the result of turbo decoding. The third storage unit 8, the information bit selection unit 9, and the re-encoding unit 10 are realized by a processing circuit which is an electronic circuit that performs each process shown in FIG. The third storage unit 8 is realized by a memory.

  Next, the operation will be described. FIG. 8 is a flowchart showing the operation of the error correction decoding apparatus 100b according to the third embodiment. The third storage unit 8 stores the second data included in the received data (step S41). The turbo decoding unit 2 receives the received data, performs iterative decoding processing a predetermined number of times, and transmits the decoding result to the selection unit 4 and the re-encoding unit 10 (step S42). The re-encoding unit 10 performs re-encoding using the decoding result (step S43). Also, the re-encoding unit 10 transmits the re-encoding result to the first comparison unit 3 (step S44). The third storage unit 8 transmits the second data to the first comparison unit 3 in synchronization with the timing at which the re-encoding unit 10 transmits the result of re-encoding (step S45).

  The first comparison unit 3 compares the second data with the re-encoding result, and counts the number of bits subjected to bit inversion (step S46). The first comparing unit 3 determines whether the counted value is larger than a predetermined threshold (step S47). When the counted value is larger than a predetermined threshold (step S47, Yes), the first comparison unit 3 transmits the first signal to the selection unit 4 (step S48). When the counted value is not larger than the predetermined value (No at Step S47), the first comparison unit 3 does not transmit the first signal to the selection unit 4 (Step S49).

  The information bit selection unit 9 receives the second data from the third storage unit 8, and transmits the information bit part of the second data, that is, the information data to the selection unit 4 (step S50). The selection unit 4 determines whether the first signal has been received (step S51). When the first signal is received (Yes in step S51), the selection unit 4 transmits information data to an external functional unit (step S52). When the first signal is not received (step S51, No), the decoding result transmitted from the turbo decoding unit 2 is transmitted to the external function unit (step S53).

  In the present embodiment, when the number of bits that are bit-inverted in a state including check bits is larger than a predetermined threshold value, the selection unit 4 transmits information data to an external function unit. In addition, the first comparison unit 3 transmits the first signal and the result of turbo decoding to the external function unit, and either the information data or the turbo decoded decoding result is processed by the external function unit. It may be determined whether to select.

  In addition, when the re-encoding unit 10 performs re-encoding processing of the decoding result, only a part that generates check bits is turbo-encoded, and re-encoding processing that receives information bits in an interleaved order is not performed. When the first comparison unit 3 compares the information bits and the check bits obtained by receiving the information bits in the order of transmission and performing the re-encoding process, it is not necessary to perform the interleaving process in the re-encoding process, thereby delaying. In addition to the reduction in size, the same effect of improving the reliability after decoding can be obtained.

  If the number of bits that are bit-inverted with check bits included is greater than a predetermined threshold, it is generally more likely that erroneous error correction decoding is being performed and the reliability of the decoding result is low. Become. For this reason, in addition to the effects of the first embodiment, the first comparison unit 3 transmits the first signal indicating that the reliability of the decoding result is low, and the decoding result obtained by performing erroneous error correction is used. Can be suppressed, and the reduction in the reliability of the decoding result can be suppressed. In the present embodiment, since the decoding result is re-encoded, the same effect as when the turbo code is used can be obtained even if an error correction code other than the systematic code is used.

Fourth Embodiment
FIG. 9 is a diagram showing functional blocks of the error correction decoding apparatus according to the fourth embodiment. The components having the same functions as those in the first to third embodiments are given the same reference numerals as those in the first to third embodiments, and redundant description will be omitted. The error correction decoding apparatus 100 c includes a turbo decoding unit 2, a selection unit 4, a second comparison unit 6, a third comparison unit 7, a third storage unit 8, an information bit selection unit 9, and the like. An encoding unit 10 and a fourth storage unit 11 are provided. The fourth storage unit 11 stores reliability information of the soft decision data. The fourth storage unit 11 is realized by a memory.

  Next, the operation will be described. FIG. 10 is a flowchart showing an operation of the error correction decoding apparatus 100c according to the fourth embodiment. The fourth storage unit 11 generates and stores the reliability information of the soft decision data in the received data (step S61). The turbo decoding unit 2 performs iterative decoding processing a predetermined number of times, and transmits the decoding result to the selection unit 4 and the re-encoding unit 10 (step S62). The re-encoding unit 10 performs re-encoding processing using the decoding result (step S63). The third storage unit 8 transmits the second data to the second comparison unit 6 in accordance with the timing at which the re-encoding unit 10 transmits the re-encoding result (step S64). The fourth storage unit 11 transmits the reliability information of the soft decision data to the third comparison unit 7 (step S65).

  The second comparison unit 6 compares the re-encoding result transmitted from the re-encoding unit 10 with the second data, and transmits the reliability information of the bit-inverted position to the third comparison unit 7. (Step S66). The third comparison unit 7 adds the reliability information of the bit-inverted position to the reliability of the soft decision data stored in the fourth storage unit 11, and adds the information based on the value added for the data for one code. It is determined whether the calculated value is larger than a predetermined threshold (step S67). When the added value is larger than the predetermined threshold (step S67, Yse), the third comparison unit 7 transmits the first signal to the selection unit 4 (step S68). If the added value is not greater than the predetermined threshold (No at Step S67), the third comparison unit 7 does not transmit the first signal to the selection unit 4 (Step S69).

  The information bit selection unit 9 receives the second data from the third storage unit 8, and transmits the information bit part of the second data, that is, the information data to the selection unit 4 (step S70). The selection unit 4 determines whether the first signal has been received (step S71). When the selection unit 4 receives the first signal (Yes in step S71), the selection unit 4 transmits information data to an external functional unit (step S72). When the first signal is not received (step S71, No), the selection unit 4 transmits the decoding result transmitted from the turbo decoding unit 2 to an external function unit (step S73).

  Further, in the present embodiment, when the total reliability value of the bits inverted not only in the information bit part but also in the check bit part is larger than a predetermined threshold, the selection unit 4 sends the information data to the external In addition to this, the third comparison unit 7 transmits the first signal and the result of turbo decoding to the external function unit, and information data is processed by the external function unit. It may be determined which of the turbo decoding result is to be selected.

  In addition, when the re-encoding unit 10 performs re-encoding processing of the decoding result, only a part that generates check bits is turbo-encoded, and re-encoding processing that receives information bits in an interleaved order is not performed. When the second comparison unit 6 compares the information bits and the check bits obtained by receiving the information bits in the order of transmission and performing the re-encoding process, it is not necessary to perform the interleaving process in the re-encoding process, thereby delaying. In addition to the reduction in size, the same effect of improving the reliability after decoding can be obtained.

  If the total reliability value of the bits inverted not only in the information bit part but also in the check bit part is larger than a predetermined threshold, there is a possibility that error correction decoding is generally performed in error. It becomes higher than the first embodiment, and the reliability as the decoding result becomes low. For this reason, in addition to the effects of the first embodiment, the first signal is treated as a signal indicating that the reliability of the decoding result is low, so that the reliability of the decoding result is higher than that described in the first embodiment. Can be increased. In the present embodiment, since the decoding result is re-encoded, the same effect as when the turbo code is used can be obtained even if an error correction code other than the systematic code is used.

  The configuration shown in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and one of the configurations is possible within the scope of the present invention. Parts can be omitted or changed.

  DESCRIPTION OF SYMBOLS 1 1st memory | storage part, 2 Turbo decoding part, 1st comparison part, 4 selection part, 5 2nd memory | storage part, 6 2nd comparison part, 7 3rd comparison part, 8 3rd memory | storage part , 9 Information bit selection unit, 10 Re-encoding unit, 11 Fourth storage unit, 20 Wireless communication system, 30 Transmission device, 40 Reception device, 100, 100a, 100b, 100c Error correction decoding device, 200 Control circuit, 200a Processor, 200b memory.

Claims (12)

A decoding unit that decodes received data that has been subjected to error correction coding using a systematic code, and outputs a decoding result;
It is determined whether the reliability of the decoding result is high or not by comparing the first data included in the received data with the decoding result, and it is determined that the reliability of the decoding result is low. A comparator that outputs a first signal indicating that the reliability of the decoding result is low ;
Before Symbol the decoding result according to the presence or absence of the first signal, and a selector for outputting one of data of the information bit portion included in the received data,
Mis Ri correcting decoder you comprising: a. The first data is:
Including data of an information bit portion of the received data;
The comparison unit includes:
Comparing the first data with the decoding result to calculate a count value indicating the number of inverted bits, and determining that the reliability of the decoding result is low when the count value is larger than a threshold value; The error correction decoding apparatus according to claim 1 . The first data is:
Including data of an information bit portion of the received data;
The comparison unit includes:
The first data is compared with the decoding result, and the reliability of the position where the bit is inverted is added to the reliability of the first data, and when the added value is larger than a threshold, the decoding result 2. The error correction decoding apparatus according to claim 1 , wherein the error correction decoding apparatus is determined to have low reliability. The error correction decoding apparatus
The apparatus further comprises a re-coding unit that performs error correction coding on the decoding result again and outputs the result of re-coding
The first data is:
Including information bits of the received data and check bits of the received data;
The comparison unit includes:
The first data is compared with the re-encoding result to calculate a count value indicating the number of bit inversions, and when the count value is larger than a threshold, it is determined that the reliability of the decoding result is low. The error correction decoding apparatus according to claim 1 . The error correction decoding apparatus
And a re-encoding unit that performs error correction coding on the decoded result again and outputs the result of re-encoding,
The first data is:
Including information bits of the received data and check bits of the received data;
The comparison unit includes:
The first data is compared with the result of the re-encoding, and the reliability of the position where the bit is inverted is added to the reliability of the first data, and the added value is larger than a threshold, The error correction decoding apparatus according to claim 1 , wherein it is determined that the reliability of the decoding result is low. The re-encoding unit includes:
The error correction decoding apparatus according to claim 4 or 5 , wherein only a part generating check bits is error correction coded. A first step of decoding received data that has been subjected to error correction coding using a systematic code, and outputting a decoded result;
It is determined whether the reliability of the decoding result is high or not by comparing the first data included in the received data with the decoding result, and it is determined that the reliability of the decoding result is low. Outputting a first signal indicating that the reliability of the decoding result is low ;
Before Symbol third step the decoding result, to output one of the data information bits part included in the received data according to the presence or absence of the first signal,
Mis Ri correction decoding how to comprising a. The first data is
Including data of an information bit portion of the received data;
The second step is
Comparing the first data with the decoding result to calculate a count value indicating the number of inverted bits, and determining that the reliability of the decoding result is low when the count value is larger than a threshold value; The error correction decoding method according to claim 7 . The first data is:
Including data of an information bit portion of the received data;
The second step is
The first data is compared with the decoding result, and the reliability of the position where the bit is inverted is added to the reliability of the first data, and when the added value is larger than a threshold, the decoding result The error correction decoding method according to claim 7 , characterized in that it is determined that the reliability of is low. The error correction decoding method is
Including a fourth step of performing error correction coding again on the decoded result and outputting a result of re-coding,
The first data is:
Including information bits of the received data and check bits of the received data;
The second step is
The first data is compared with the re-encoding result to calculate a count value indicating the number of bit inversions, and when the count value is larger than a threshold, it is determined that the reliability of the decoding result is low. The error correction decoding method according to claim 7 , wherein: The error correction decoding method is
Including a fourth step of performing error correction coding again on the decoded result and outputting a result of re-coding,
The first data is:
Including information bits of the received data and check bits of the received data;
The second step is
The first data is compared with the result of the re-encoding, and the reliability of the position where the bit is inverted is added to the reliability of the first data, and the added value is larger than a threshold, 8. The error correction decoding method according to claim 7 , wherein it is determined that the reliability of the decoding result is low. The fourth step is
Error correction decoding method according to claim 1 0 or 1 1, characterized in that the error correction encoding only a portion that generates a check bit transmission order.

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