JPH0113249B2 - - Google Patents

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a cyclic majority code decoder.

(Prior art) The conventional cyclic majority code decoder is as follows (a) and (b)
It was constructed based on two methods.

In addition, in the following, the receiving sequence is r _o-1 ,
Among r _o-2 ,..., r ₀ , r _o-1 , r _o-2 ,..., r _ok are information points, r _ok-1 , r _ok-2 ,..., r ₀ are inspection points, and r _i The added noise bits are noise bits e _i , the composite parity check results are A _i1 , A _i2 ,..., A _ij (j is the value determined by the code length n and the check point k), and the arithmetic sum is S _i , S _o-1 , S _o-2 ,
..., S ₀ . The received series is sometimes referred to as received data.

(a) Obtain a composite parity check based on the parity check matrix of the code, input this check result to a majority decision element with a fixed threshold, and determine whether there is an error in the output of this element. How to perform error correction.

(b) Obtain a composite parity test from the syndrome,
A method of correcting errors in received data by inputting this test result into a majority decision element with a fixed threshold and determining whether there is an error in the output of this element.

FIG. 1 is a block diagram of a conventional cyclic majority code decoder, and shows a (21, 11) difference set cyclic majority code decoder constructed using the method (a).

In FIG. 1, the (21, 11) difference set cyclic majority code decoder includes a 21-stage shift register 1, a composite parity check generation circuit 2, a majority element 3 with a threshold of 3, and receives received data (to be described later) into the shift register 1. It consists of an input switch 4, a switch 5 used for cyclically shifting the shift register 1, and an exclusive OR circuit (EX-OR) 6. The composite parity check generation circuit 2 consists of five composite parity tests A _20,1 to A _20,5 .

Next, the decoding procedure (step 1) to (step 5) of this cyclic majority code decoder will be explained.

Note that in the following, the + sign indicates addition modulo 2 for each corresponding bit.

(Step 1) Turn on switch 4, turn off switch 5,
All 21 bits (r ₀ to r ₂₀ ) of received data are input to shift register 1. After this, switch 4 is turned off and switch 5 is turned on.

(Step 2) Find five composite parity checks orthogonal to noise bit _e20 .

The composite parity tests A _20,1 to _{A 20,5} are respectively A _20,1 = r ₉ + r ₁₂ + r ₁₃ + r ₁₈ + r ₂₀ A _20,2 = r ₁ + r ₁₁ + r ₁₄ + r ₁₅ + r ₂₀ A _20,3 = r ₄ + r ₆ + r ₁₆ + r ₁₉ + r ₂₀ A _20,4 = r ₀ + r ₅ + r ₇ + r ₁₇ + r ₂₀ A _20,5 = r ₂ + r ₃ + r ₈ + r ₁₀ + r ₂₀ , and these are the composite parity check generation circuit Composite parity check in 2 A _20,1 ~ A _20,5 output 2a ~ 2
It can be found as e.

(Step 3) Outputs 2a to 2e of composite parity check generation circuit 2
is input to the majority element 3. After this EX-OR6
, the output 3a of the majority element 3 and the first bit r ₂₀ of the received data at the right end of the shift register 1
The error in bit _r20 is corrected by performing exclusive OR with the output of bit r20.

(Step 4) By shifting the received data stored in shift register 1 one bit to the right, the error-corrected output of bit _r20 is output as output 6a of EX-OR6, and output 6a is output as output 6a of EX-OR6. It is output as data to the outside, and is cyclically shifted as input data to the left end of shift register 1 via switch 5, and the second bit _r19 is positioned at the right end of shift register 1.

Bit r ₁₉ is error corrected through the same decoding procedure (step 2) and (step 3) as bit r ₂₀ .

(Step 5) For each of the remaining bits _r18 to _r0 of the received data, (step 2) to (step 4) are repeated to perform error correction for each bit.

In this way, (Step 1) ~ (Step 5)
After completing the error correction operation of the received data using
a to 2e are all "0".

However, in the conventional system described above, since the threshold value of the majority decision element is fixed, when the number of error bits added to the received sequence exceeds the number of error bits that can theoretically be corrected, the composite parity check generation circuit The number of bits whose output exceeds the threshold of the majority element may exceed the number of error bits added to the received sequence, and even in this case, all bits of the received data are sequentially identified as errors based on the output result of the majority element. Since the error is corrected, even bits with no errors are corrected, which has the disadvantage of worsening the error correction rate.

Although not shown, in a cyclic majority code decoder configured using method (b), the threshold of the majority element is fixed, and each bit of the received data is sequentially processed based on the output result of the majority element. Since errors are corrected, bits with no errors are also corrected, which has the disadvantage of worsening the error correction rate.

(Object of the Invention) An object of the present invention is to provide a cyclic majority code decoder that improves the error correction rate when the number of error bits added to a received sequence exceeds the number of error bits that can be theoretically corrected. do.

(Structure of the Invention) Storage means for storing reception sequences r _o-1 , r _o-2 , ..., r ₀ and sequentially shifting the stored reception sequences, and an exclusive unit connected to an output terminal of this storage means. a first opening _/ closing means inserted between the output terminal of the exclusive OR circuit and the input terminal of the storage means _{; 2} ,…, r _ok is the information point, r _ok-1 , r _ok-2 ,
_{. _ _}
Among the composite parity check results A _i1 , A _i2 , ..., A _ij (j is a value determined by code length n and check point k) by this composite parity check means, the arithmetic sum S of bits whose check result is "1" is _i , (S _o-1 , S _o-2 ,…, S ₀ )
a counting means for counting the maximum value of the output of the counting means; a maximum value storage means for storing the maximum value of the output of the counting means; a comparison means for comparing the output value of the maximum value storage means with the output value of the counting means; a second opening/closing means for supplying the first output of the comparing means to the maximum value storage means; and a third opening/closing means for supplying the second output of the comparing means to the exclusive OR circuit at the time of correction. A cyclic majority code decoder.

(Embodiment) FIG. 2 is a block diagram of an embodiment of a cyclic majority code decoder according to the present invention, and is a (21, 11) difference set cyclic majority code constructed using the method (a) described above. A decoder is shown.

Components that are the same as those described above are given the same reference numerals, and their explanations will be omitted.

In FIG. 2, the (21, 11) difference set cyclic majority code decoder according to the present invention includes a 21-stage shift register 1 (storage means), a composite parity check generation circuit 2,
Arithmetic of the bit that is "1" from the composite parity check results of the outputs 2a to 2e of the switch 4, switch 5 (first opening/closing means), exclusive OR circuit (EX-OR) 6, and composite parity check generation circuit 2. Composite parity check result counting counter 7 for calculating the sum, maximum value register 8 for storing the maximum output value of the counter 7, comparing the output value of the counter 7 and the output value of the register 8, and outputting the two outputs. A comparison circuit 9 generates outputs 9a (second output) and 9b (first output), a switch 10 for outputting the output of EX-OR6, and transmits the maximum output value of counter 7 to register 8 at the time of check. Logical product circuit (AND) 1
1. AND12 (second opening/closing means) that transmits the output 9b of the comparison circuit 9 to the register 8 during check, AND13 (third opening/closing means) that transmits the output 9a of the comparison circuit 9 to the EX-OR6 during correction, and an inverter. It consists of 14 parts.

The composite parity check generation circuit 2 consists of five composite parity tests A _20,1 to A _20,5 . Switch 5 is inserted between shift register 1 and EX-OR6,
This is a switch that is turned on only when making corrections or checking.

Next, the decoding procedure (step 1) to (step 11) of the cyclic majority code decoder according to the present invention will be explained.

(Step 1) Switch 4 is turned on, switches 5 and 10 are turned off, and all 21 bits (r ₀ to r ₂₀ ) of received data are input to shift register 1. After this, switch 4 is turned off and switch 5 is turned on. Switch 10 is off.

(Step 2) Initialize the contents of the maximum value register 8 to "0" using the maximum value register clear signal. Then, the correction/check signal is used as a check.

The correction/check signal is supplied to the inverter 14 as a correction signal when it is at a high level ("1") and as a check signal when it is at a low level ("0").

(Step 3) Find 5 composite parity checks orthogonal to noise bit _e20 . The composite parity tests A _20,1 to _{A 20,5} are respectively A _20,1 = r ₉ + r ₁₂ + r ₁₃ + r ₁₈ + r ₂₀ A _20,2 = r ₁ + r ₁₁ + r ₁₄ + r ₁₅ + r ₂₀ A _20,3 = r ₄ + r ₆ + r ₁₆ + r ₁₉ + r ₂₀ A _20,4 = r ₀ + r ₅ + r ₇ + r ₁₇ + r ₂₀ A _20,5 = r ₂ + r ₃ + r ₈ + r ₁₀ + r ₂₀ , and these are the composite parity check generation circuit Composite parity check in 2 A _20,1 ~ A _20,5 output 2a ~ 2
It can be found as e.

Composite parity check A _20,1 ~ A _20,5 output 2a ~ 2
e is input to the composite parity check result counting counter 7. Then, the output 7a of the counter becomes the arithmetic sum of the bits of the outputs 2a to 2e of the composite parity check generation circuit 2, which are the composite parity check results "1".

(Step 4) Output 7 of composite parity test result counter 7
a and the output 8a of the maximum value register 8.
Here, the output value of the counter 7 and the output value of the maximum value register 8 are compared in magnitude.

Only when the output value of the counter 7>the output value of the register 8, the contents of the maximum value register 8 are rewritten with the output 7a of the counter 7 via AND11.

(Step 5) Shift the received data stored in shift register 1 to the right by 1 bit, and position the second bit _r19 at the right end of shift register 1. As a result, bit r ₁₉ is (step 3), (step 4)
The maximum value of the count value of the composite parity test result is stored through the same procedure as .

(Step 6) For each of the remaining bits _r18 to _r0 of the received data, repeat steps (step 3) to (step 5) 21 times.
The maximum value of the count value of the composite parity check result is stored.

As a result, the maximum value register 8 stores the maximum output value of the composite parity check result counter 7.

The procedures from (Step 1) to (Step 6) described above only check five composite parity checks and do not perform error correction on the received data. That is, after shifting the shift register 1 to the right 21 times, the state of the received data stored in the shift register 1 is the same as the state after executing (step 1).

(Step 7) The correction/check signal is used as a correction.

(Step 8) The same process as (step 3) is performed.

That is, the outputs 2a to 2e of five composite parity checks A _20,1 to _{A 20,5} orthogonal to the noise bit e ₂₀ are input to the counter 7.

(Step 9) Output 7 of composite parity test result counter 7
Output 8a of maximum value register 8 with a as one input
is used as the other input, both signals are supplied to a comparison circuit 9, where the output value of the counter 7 and the output value of the register 8 are compared in magnitude.

Output value of counter 7 ≧ output value of register 8 Only in this case, comparison circuit 9
The output 9a of the shift register 1 is supplied to the EX-OR 6, and the error in the first bit _r20 of the received data at the right end of the shift register 1 is corrected. That is,
The comparator circuit 9 functions as a majority element that uses the memory contents of the maximum value register 8 as a threshold value.

(Step 10) Shift the received data stored in shift register 1 to the right by 1 bit, and then shift the received data stored in shift register 1 to the right.
Position r ₁₉ at the right end of shift register 1. As a result, the output of bit _r19 is (step 8) ~
The error is corrected through the same procedure as (step 9).

(Step 11) For each remaining bit _r18 to _r0 of the received data,
A total of 21 steps (Step 8) to (Step 10)
Repeat until the bit is decoded.

As a result of performing (step 1) to (step 11), if all errors in the 21-bit (r ₀ to r ₂₀ ) received data have been corrected, the output 7a of the counter 7 will all be "0". , at this time, switch 5 is turned off, switch 10 is turned on, and shift register 1 is
Output the received data stored in.

If the output 7a of the counter 7 does not all become "0", the correction result stored in the shift register 1 is supplied to the shift register 1 via the switch 4 as new received data (step 2). Repeat steps ~ (step 11).

As mentioned above, when correcting errors added to a received sequence using the cyclic majority code decoder of the present invention, first, 21 bits (r ₀ ~
After determining the output 7a of each composite parity check result counting counter 7 for the entire received data of _r20 ) and determining its maximum value, this maximum value is adopted as the threshold of the majority element to correct errors in the received data. As a result, there is a greater possibility that the bits with errors are corrected first, and the probability that a bit without an error is determined to be an error bit becomes lower, and errors multiply, causing fatal received data errors. Since the probability of error is lowered, it is possible to improve the error correction rate when the number of error bits added to the received sequence exceeds the number of error bits that can theoretically be corrected.

The embodiment of the present invention described above is a cyclic majority code decoder configured using the method (a) described above, and although it will not be described in detail here, the present invention uses the method (b) described above. Needless to say, it can also be applied to those configured with

Further, although the above embodiment is a (21, 11) difference set cyclic majority code decoder, the present invention is not limited to this decoder.

FIG. 3 is a graph comparing the correction rates of the conventional cyclic majority code decoder and the cyclic majority code decoder of the present invention, both of which are constructed using the method (a) described above. It is a (73, 45) difference set cyclic majority code decoder. The theoretical number of error bits is 4. This graph shows the results of 1000 simulations.

The broken line is the correction rate of the conventional cyclic majority code decoder, and the solid line is the correction rate of the cyclic majority code decoder according to the present invention. It can be seen that the correction rate of the present invention is higher than the conventional correction rate when the theoretical number of error bits is exceeded.

(Effects of the Invention) The present invention can provide a cyclic majority code decoder that improves the error correction rate when the number of error bits added to the received sequence exceeds the theoretically correctable number of error bits. When correcting the added errors, first obtain the composite parity check results for the entire received sequence, and after finding the maximum value, use this maximum value as the threshold of the majority element. Since data errors are corrected, there is a greater possibility that errors will be corrected starting from bits with errors, and the probability that bits with no errors will be judged as erroneous bits will be lower, and errors will multiply and fatal received data Since the probability of an error occurring is lowered, the error correction rate can be improved when the number of error bits added to the received sequence exceeds the number of error bits that can theoretically be corrected.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional cyclic majority code decoder, Fig. 2 is a block diagram of an embodiment of the cyclic majority code decoder according to the present invention, and Fig. 3 is a block diagram of a conventional cyclic majority code decoder and the present invention. It is a graph comparing the respective correction rates with the cyclic majority code decoder. 1...Shift register, 2...Composite parity check generation circuit, 3...Majority element, 4, 5, 10...
...Switch, 6...Exclusive OR circuit (EX-
OR), 7... Composite parity check result counter, 8... Maximum value register, 9... Comparison circuit, 1
1, 12, 13... logical product circuit (AND), 14...
...Inverter.

Claims (1)

[Claims] 1. Storage means for storing received sequences r _o-1 , r _o-2 , ..., r ₀ and sequentially shifting the stored received sequences, and an exclusive OR circuit connected to the output terminal of this storage means. and a first opening _/ closing means inserted between the output terminal of the exclusive OR circuit and the input terminal of the storage means;
r _o-2 ,…, r _ok are information points, r _ok-1 , r _ok-2 ,…, r ₀
is the test point, the noise bit added to r _i is the noise bit e _i
A composite parity check means for performing a composite parity check orthogonal to the noise bit, and a composite parity check result by the composite parity check means.
Arithmetic sum _{S i , So -1 , So- 2} , ..., S ₀ , a maximum value storage means for storing the maximum value of the output of this counting means, and a comparison for comparing the output value of this maximum value storage means with the output value of the counting means. means, second opening/closing means for supplying the first output of the comparison means to the maximum value storage means at the time of checking, and a second opening/closing means for supplying the second output of the comparison means to the exclusive OR circuit at the time of correction. 3. A cyclic majority code decoder having 3 opening/closing means.