FI114515B - Method and apparatus for optimizing a decoder - Google Patents

Abstract

In a communications system, a message to be transmitted is used to generate an error detection checkword. Both the message and checkword are encoded into a communication traffic signal using an error correction code. An error correction decoder decodes a received traffic signal, generating a plurality of candidate decoded signals and quantitative measurements of the reliability of the candidates. An error detection calculator tests the most reliable candidate for compliance between its decoded message and checkword. If there is compliance, that candidate and its decoded message are selected. If there is no compliance, the next most reliable candidate is tested for compliance, the selection process continuing until compliance is found. If no compliance is found among all the candidates, an error corrector scrutinizes the most reliable candidate for the presence of a correctable error, and the corrected candidate is re-tested for compliance. If there is still no compliance, the next most reliable candidate is scrutinized for the presence of a correctable error, and the corrected candidate is retested for compliance, the process continuing until compliance is found, up to the limits of the error correction capability of the error corrector.

Description

114515

Method and apparatus for optimizing a decoder

Background

The present invention relates to a decoding system for use in signal communication, and in particular to a decoding stream to decode transmitted data messages using both error detection and error correction coding.

When transmitting data through error-prone communications channels, such as radio channels, error detection coding and / or error correction coding may be used to reduce errors in the transmitted data.

10 The transmitted data is often digital information, which is most readily understood in the form of messages consisting of binary bits of information, where each bit can be either ONE or ZERO. Any given message is then just a queue made up of UNITS with a set of ZEROS scattered between them. It will be appreciated that any string of L bits may represent one 2L of 15 unique messages.

Error-coding and error-correcting coding for digital information are different encoding formats, and both are important. A simple example of error-detecting coding is to add an identical copy of a message to this message, send both, bit by bit comparing the received message with the received message, ';' / mine. For each bit position, any difference between the message and its copy is proof of a transmission error. The total number of message differences is a quantitative measure of the reliability of the data transmission. It will be appreciated that the total number of differences is an inaccurate measure of concurrency, since no concurrent errors in the same bit positions of both the message and the copy are recognized: 'i'; vuuksiksi.

Normal error detection technology, cyclic excess checking technique. ankle (Cyclic Redundancy Check, CRC), produces and adds to the message "check bit-. · · ·. paths" determined by the bits of the data message. The check bits form • »30 a" check word ", which is characteristic of a particular message. Check -:.:: The word can be appended after the message so that both are processed by the same encoder, both are transmitted over the same communication channel together, and both are processed by the same decoder in the receiver. The CRC calculator in the receiver can then generate the check bits corresponding to the received decoded 35 message bits, and this 2 114515 check words calculated by the receiver can be compared to the decoded check word received with the message. Any anomaly indicates an error in transmission, and the degree of anomaly can be used as a quantitative measure of the reliability of the data transmission.

In contrast, a simple example of error correction coding is to send multiple identical copies of a given message and perform bit by bit comparison of all messages received in the receiver. Whether the bit of the message output from the receiver must be set to ONE or ZERO can be decided on the basis of "bit democracy", i.e. the majority of the bit values received for this 10 bit position determines the output. Transmission errors can be assumed to be uniformly distributed among the message copies and less likely to occur in the same bit position in the majority of copies.

A known error correction technique is convolutional coding, in which the transmitted bits, known as parity bits, are determined based on the message bits. The message bits are taken into account L bits at a time and r parity bits are transmitted for each L message bit. For example, the parity bits can be calculated as certain Boolean combinations of various bits of the message.

Sending convolutionally coded parity bits separates convolutional coding from generally alternative coding schemes, such as block coding, in which a small number of message bits are converted; and a plurality of such code words are transmitted: ·, *. to transfer the whole message.

The present invention will be described below primarily in the context of convolutional coding, although it may be applied with other coding forms as will be mentioned. A general description of the known convolutional coding technique will therefore be given below to assist in understanding the background of the present invention.

Figure 1 illustrates a transmitter 20 having a convolutional encoder ,,; j * 30 22 consisting of a shift register 24 through which bits of information to be encoded are transmitted. The shift register contains a limited number of bits L with the number L being. known as the code constraint length because the code is limited to be considered L bits at a time. At each time the bits in the shift register 24, which may be designated Bi, B2F B3, B4, BL, is fed to a logic network 26, 35 to develop two or more different Boolean combinations of bits. As illustrated in FIG. 1, bits in the shift register may be provided with a CRC error detector 114515 generator 28 which receives the message information to be transmitted and generates and adds to the check bits described above.

The combinations generated by the network 26 are the aforementioned parity bits, which may be called P2) .... Pr. The parity bits are transmitted over the communication channel 5 to a receiver 30 having a decoder 32 which converts them back into data bits B1t B2, B3, ..., BL, and finally to the transmitted message information.

An alternative embodiment of the communication system illustrated in Figure 1 is illustrated in Figure 2. Instead of the combination logic network 26 shown in Figure 1, the transmitter includes a look-up table 27 consisting of a 2L entry stored in conventional memory 10. The L-bit patterns B1, B2 ... B1 of the contents of the shift register 24 indicate the corresponding entries in the lookup table 27 which are formed by characteristic sets of parity bits P1, P2, ..., Pr. The Boolean combinations of the bits in the shift register 24 patterns is thus stored in lookup table 27 rather than 26 developed a logic array.

If two parity bits are generated for each bit transfer through shift register 24, the code is known as a rate 1/2 code, which transmits twice the number of parity bits as compared to the original transmitted da-tabs. If the transmission rate is fixed, the time required to transmit such parity bits is twice the time required to transmit the original data bits. More generally, if r parity bits are generated for each transmission, the code is known as a rate 1 / r code. Typically, the transmission rate of the pairs ·, teet bits is adapted to be r times the bit information ν 'of the message information. speed.

For example, a Boolean kombinaatioyhtälöt a rate 1/2 code, having; ' The constraint length 5 for generating parity bits could be: * * P-ι = Bi + B2 + B3 + Bs P2 = Bi + B4 + B5, * «» v: where "+" represents modulo-2 addition. It is seen that the modulo-2 addition is logically equivalent to the exclusive OR operation,;: * 30 since 0 + 0 = 0; 0 + 1 = 1+ 0 = 1; and 1 + 1 = 0.

As mentioned above, r times more parity bits than si-; \ weather input data bits are produced for the rate 1 / r code, and if all parity bits are transmitted, an r-fold excess is arranged to counteract errors. However, it will be appreciated that it is not necessary to transmit all the parity bits. If the transmitter and receiver have previously agreed on a standard ·: ·; the method for deciding which parity bits are not transmitted, the code is known as a 4114515 punctured convolutional code. Punctured codes typically result in encoding rates of m / r, such as 13/29, where matching to a transmission rate of r / m times the bit rate of the message information is required.

Tables of parity equations for various code rates and constraint limits leading to optimum codes have been published in the technical literature. See, e.g., G Clarke, Jr., and J. Cain, Error-Correcting Coding for Digital Communications. Appendix B, Plenum Press, New York (1981).

The main known convolutional code decoding methods are threshold decoding, Sequential Maximum Likelihood Sequence Estimation (SMLSE), and the stack algorithm. SMLSE technology is commonly known as the Viterbi Algorithm, which is described in the literature including D. Forney, "The Viterbi Algorithm",

Proc. IEEE, Vol. 61, pp. 268-278 (March, 1973). A description of the decoding methods can be found in the darke and Cain text exemplified above.

The operation of the SMLSE convolutional decoding algorithm is illustrated in Fig. 3 for a rate 1/2 code with a constraint length of five. In the SMLSE decoder, a plurality of electronic storage elements 33, 34, 35 are sequenced into groups called states, and the number of states is 2L'1, where L is the constraint length of the code to be decoded. The memory elements contain at least two types of information, i.e. bit histories in elements 33 and elements 34, with space-associated routers-Riikka. Additionally, the state numbers associated with the states can be stored in elements 34 in bi-: * '' binary L-1 bit patterns.

: v. Route metrics can be considered as a safety factor that represents the coefficient ···. the degree of resolution between the assumed bit sequence and the actual (i.e., received) bit sequence. When the putative and the actual bit sequence are identical, the path metric is smaller in quantity and the certainty associated with this putative bit sequence is greater. It is understood that a "putative bit sequence", or simply a "hypothesis", generally refers to any hypothetical bit sequence that has any probability of being the actual bit sequence of interest. You-30 can thus represent message information bits, parity bits, or other code words.

:! ·. An important part of most SMLSE decoders is copy I of the coding algorithm 38. For the example communication system illustrated in Figure 1, copy 38 could be an L-bit shift register and a combination logic network that implements the equations used in encoder 22 to generate parity bits P1, P2, .... Pr. . Alternative- ': * *! alternatively, copy 38 could be an L-bit shift register and a 2L labeled lookup table stored in electronic 5114515 memory, as in the system illustrated in Figure 2. In both cases, the 2L assumption is generated by copy 38 and compared directly to the received parity bit stream by comparator 39.

The (L-1) bit status numbers in the memory elements 34 represent all but one of the 5 contents of the coding shift register 24. The Lth bit represents the next bit to be decoded and may be either ZERO or ONE. Both possibilities are tested together with all other combinations of other bits represented by the state numbers. Thus, all 2L possible bit combinations are tested by a decoder and a running reliability factor, 10 path metrics 35, is stored to estimate the correlation between the assumed bit sequence and the received bit sequence.

The steps of the SMLSE algorithm are as follows for a speed 1/2 code with a restriction length of five.

Step 1. For the first state, 0000, it is assumed that the new bit 15 is also ZERO. The default 00000 is supplied to copy 38 to generate two default parity bits Pi (00000) and P2 (00000). In this way, the default information is encoded using the same parity equations used in the encoder shown in Figures 1 and 2.

Step 2. The actual received parity bits Pi (real) and 20 P2 (real) are compared to the assumed parity bits Pi (00000) and P2 (00000) by comparator 39. The comparison has one of the following results: both bits match; one of two bits matching and one not matching; or neither bit: v. match. If both Pi (00000) and P2 (00000) match the actual received- ···. For the parity bits Pi (real) and P2 (real), the value zero is added by adder 36 to the routing metric associated with state 0000, which can be represented by * Gpm (0000). Similarly, if there is only one match, the value one is added

Gpm (0000) of. If neither Pi (00000) nor P2 (00000) matches the actual received * · * * parity bits Pi (real) and P2 (real), the value two is added

Gpm (0000) of. In this way, the routimetric value for any given state 30 represents a cumulative mismatch between the assumed bit sequence and the actual bit sequence for a given state. The higher the cumulative total: '·. the inertia is for a given state, the higher the routing value, and the lower the running reliability coefficient for that state.

»*» I · 6 114515

Step 3. Steps 1 and 2 are repeated for position 1000. Assuming the new 5th bit is ZERO, pattern 10000 is input to copy 38 and its output bits Pi (10000) and P2 (10000) are compared to actual received bits Pi (real) and P2 (real). . The route metric for position 1000, denoted by 5 Gpm (1000), is updated as in step 2 based on comparing Pi (real) and P2 (real) with Pi (10000) and P2 (10000).

Step 4. Updated route metrics for states 0000 and 1000, i.e. Gpm (OOOO) and Gpm (1000), are compared by comparator 37. Any state with lower route metrics and, therefore, less mismatch, becomes 10 new states 0000 when the 38 the bit patterns are shifted to the left by one bit position, and the leftmost bit shifts over to the corresponding bit history in the memory elements 33, leaving 0000 in each case. Thus, either of the states 1000 or 0000 may be the precursor of the next state in the case of a new bit of 0, depending on which state survives because it has a Path 15 metric, the leftmost bit dropping out of encoder copy 38 pattern to become the rightmost bit of the next to 0000, it will be either 0 or 1. In addition, the other corresponding bits in the new bit history memory 33 are copied from the surviving selected state, overwriting the non-surviving selected non-surviving bits. For example, as shown in Figure 3, if 20 route metric Gpm (1000) is 1.8 and route metric Gpm (0000) is 9.5, state 1000 is selected to survive and bits 10110111 to the left are overwritten by bit; ; 33 new spaces for 0000.

Step 5. Steps 1-4 are repeated for the assumption that the new bit is FIRST * ···, NEN. Assumptions 00001 and 10001 for the actual received bits are respectively supplied to copy 38 to generate pairs of parity bits Pi (00001), • / Ρ2 (00001) and Pi (10001), P2 (10001) that could be expected. These parity bit ends-

• · I

paths are compared with the actual received parity bits h i n Pi (real) and '·' * P2 (real), resulting in updated route metrics Gpm (0000) and Gpm (1000), which are then compared. This results in a new state 0001 which also has potential.,; j '30 predecessors 0000 and 1000.

Step 6. Steps 1-5 are repeated for all other pairs of precursor states: 0001 and 1001 (leading to new states 0010 and 0011); 0010 and 1010 (leading to the new 'i ;.' states 0100 and 0101); 0011 and 1011 (leading to new states 0110 and 0111); 0100 and 1100 (leading to new spaces 1000 and 1001); 0101 and 1101 (leading to new facilities 351010 and 1011); 0110 and 1110 (leading to new spaces 1100 and 1101); 0111 and: ··: 1111 (leading to new spaces 1110 and 1111).

7 114515

After the above six steps, the two actual received parity bits have been processed and one new decoded bit has been transferred to all bit history memory elements 33. These stored patterns are candidates for the final SMLSE sequence. Due to the way in which bit histories overwrite other bit histories, when one of a pair of states is selected to survive, the older bits in the memory elements 33 are prone to contract. If all the oldest bits in all bit histories match, they can be removed as a final decision and the bit history memory elements 33 can be truncated by one bit.

The algorithm for codes having other rate, such as 10 1/4 rate, proceeds accordingly, even if four parity bits were generated for each assumption and compared with the four received bits, generating possible increments for zero, one, two, three, or four mismatch cumulative path metrics.

In another modification of the known algorithm, the received pair-to-fifte bit bits are characterized not only by their bit polarities but also by their size or quality measure, which represents "first order" or "zero". When a mismatch with a locally predicted default parity bit is detected, a higher amount of route metric is penalized if the received bit quality is high and therefore there is less doubt that its sign was actually 20 correct than if the quality was low and the received bit polarity was suspicious.

This "soft" decoding, as opposed to "hard" decoding, ideally uses a "soft" bit quality measure associated with -LOG (probability) where: v. "probability" is the probability that the bit polarity is correct. When this! · · ·. the logarithmic measure is used, the cumulative metric then represents all bits] *. 25 ^ the odds ratio product. The state and bit history sequence, whereby *, 'is the smallest cumulative metric, represents the sequence with the highest probability of being correct. Usually noise is assumed to be Gaussian noise, where in the case of * I · '·' 'the penalty term can be shown to be proportional to the square of the bit amplitude. Punishment for incompatibility with locally predicted ..! · * Between the 30 default bits and the received high quality bit can be influenced by adding a term proportional to 1 / (- LOG (probability)) such as ·. to the logarithmic multifunctional scale when a mismatch is detected. Such an insertion can have a substantial effect on the dimension only every time there is a high probability that the received bit polarity is correct and yet an incompatibility is detected.

* I * * »8 114515

Such convolutional encoders and decoders may be constructed to work with non-binary symbols such as temporal and quaternary symbols.

The three areas in which the performance of convolutional decoders can be improved include interrupting decoded bit sequences, terminating decoding when all received bits are processed, and determining the second best decoded bit sequence globally. For example, premature interruption of decoded bit sequences can lead to loss of information, and known interruption of decoding techniques can leave uncorrected message bit errors in one of the remaining decoded data message candidates. The present invention solves these annoying problems by avoiding the need to make early data bit decisions to interrupt the decoded bit sequences, and terminating the decoding while still retaining a number of potential decoded data message candidates.

Known methods for cleaving and terminating are described below for purposes of contrasting with the improvements of the present invention described below.

Known methods of interrupting the growth of history

The first known method for breaking the required bit history memory pi-20 is to make a decision on the oldest bit as soon as the memory is full. The oldest bit is taken from the history memory associated with the state with the lowest v, cumulative metric. The oldest bits of the other states are then discarded, reducing the memory by one bit and allowing the decoding to proceed for another step.

; '! After all received parity bits have been processed, the result of decoding is • / 25 one data sequence corresponding to the extracted bits followed by 2 (L'1) candidates' * '·' for the remainder of the message, corresponding to bits still in history memory, v: Another known the truncation method is to form a majority vote of the oldest bits of all states into a terminated bit, and then delete the van - ,, ;; · Hottest bits before proceeding.

Both known methods lose information by making 11 »premature decisions about the oldest bits.

> Vol

Known methods for terminating decoding

When the last bit of data is entered into the coding shift register, it must

I (I

passes the entire distance so that it affects the number of generated parity bits to be transmitted. This requires that additional bits, called end bits, have to be inserted after the last bit of data to pass through.

In the known terminating method, the ending bits are known bit patterns, such as all zeros. In this case, the prior art decoder method 5 must force the assumptions of each new bit corresponding to the end bit to a known value. Thus, after processing the parity bits corresponding to the zero-end bit, only the state numbers ending in zero would be produced, halving the number of states. Each successive known end bit halves the number of states so that only one state is left, which is a decoded 10 data message. Of course, it is possible that this one remaining candidate message contains uncorrectable bit errors.

Known Second Right Best Sequence Determination The 2 (L'1) surviving candidate sequences in a conventional Viterbi decoder may not contain the globally second best sequence, although they are guaranteed to contain the globally best sequence. Known modification of the convolutional decoder published by N. Seshrad and C. W. Sundberg

it is entitled "Generalized Viterbi Detection with Convolutional Codes", Proc. IEEE

Globecom. '89, pp. 1534-1538 (Nov. 1989), allows for the calculation of the second best globally as well as the globally best sequence. This requires doubling the number of farms. It is then stored for each replacement until this moment * ·. by far the best and second best route metric. In each iteration, the best * ·. of the four and the second best four are selected to survive in the new space.

«

Globally, the third best can also be calculated by the above method if a triple number of spaces is used. Generally, the correct second and third best sequences of this * * · '· / 25 globally by this method are achieved only at the cost of increased complexity. Generally, globally, the Nth best sequence can be calculated by the above method if N times the number of states is used. Then, it; i · for each position, the best path metric is stored to date N.

'30 In each iteration, N is selected from the best 2N to survive in the new states.

Summary

A communication system and method is provided to reduce errors in the transmission of the communication signal. The transmitted signal is used to generate an error detection check word. Both the data message and its corresponding error detection word 35 are encoded into the communication signal using an error correction code 114515. The error-correcting decoder decodes the received traffic signal, generating a plurality of candidate decoded signals. A quantitative measure of the reliability of each candidate is developed by a decoder. The error detector calculator tests the most reliable candidate for correspondence between its 5 decoded data message and its corresponding decoded error detection check word. If a match exists, this candidate and its decoded data message are selected. If there is no match, the next most reliable candidate will be tested for match as the selection process continues until a match is found. If no match is found among all candidates, the vir-10 repairman checks the most reliable candidate for the presence of the error to be corrected, and the corrected candidate is retested for compliance. If there is no match yet, the next most reliable candidate will be checked for the presence of the error to be corrected, and the matched candidate will be re-tested for compliance as the process continues until a match is found within the error correction capability limits of the corrector.

The preferred error correction coding method for data messages for use with the present invention is convolutional coding as described above. The present invention also uses error detection to check if the decoded data messages contain uncorrected errors.

The preferred error-detecting coding is achieved by adding a cyclic redundancy check (CRC) word to the data message before the error-correcting coding, so that the CRC word itself is also protected by error-correcting coding.

. ···. The present invention utilizes a Viterbi-SMLSE decoder 25, modified as described below, to decode the error-correcting coding, to generate a plurality of candidate bit sequences for the data message and to connect it. CRC word. The candidate bit sequence having the lowest cumulative path · * metric is then tested for the correspondence between its data message and the CRC bits. If the CRC succeeds, this candidate message will be selected for use. If CRC ..i: '30 fails, the candidate bit sequence having the next highest metric is checked, etc., until one of the bit sequences is found to be equivalent:. *. CRC, and this candidate message is selected for use.

· '·] If nothing is found to have a corresponding CRC then either the entire word is rejected, or other procedures can be defined to select one · ... · 35 candidate message based on whether the CRC has ability to also correct a limited number of errors. For example, a candidate bit sequence having 11114515 Low Metrics is checked again, and if its CRC syndrome matches a single bit error that can be detected and corrected, then this candidate message is selected for use. If its CRC syndrome does not match a single bit error that can be detected and corrected, then the candidate bit sequence having the next higher metric is checked again. If the candidate bit sequence having the next higher metric has a CRC syndrome corresponding to a single bit error that can be identified and corrected, then this candidate message message is selected for use, etc., until one of the candidate bit sequences is found to have a CRC syndrome corresponding to a single bit error. can be identified and corrected and this candidate message is selected for use.

The decoding system of the present invention can advantageously be used with a decoding system for separating different types of convolutionally encoded signals, which is described in co-pending application Serial No. 07 / 652,544, filed 8.

15 February 1991, which is hereby incorporated by reference.

Brief Description of the Drawings

The present invention will now be described in more detail with reference to preferred embodiments of the invention, which are given by way of example, and will be described in the accompanying drawings, in which: Figure 1 illustrates a communication system including convolutional: '; the encoder that can be used in the present invention; : * · ': Figure 2 illustrates a communication system including an alternative convolutional codec for the convolutional encoder shown in Figure 1. ·. which can also be used in the present invention; * · · Figure 3 illustrates an example of a convolutional decoding algorithm,

t i I

l !! which can be used in the present invention.

FIG. 4 illustrates a memory storage system for a cut-off technique that can be used in the present invention.

Figure 5 illustrates an example of a cutting technique that can be used

• · I

: 30 in the present invention.

Figures 6, 6a and 6b illustrate examples of bit sequences for decoding decision strategies that can be used in the present invention;

FIG. 7 shows a functional block diagram of an encoder for presenting: '': 35 for implementing an embodiment of the invention; 12 114515

Fig. 8 shows a functional block diagram of an encoder for implementing another embodiment of the present invention;

Fig. 9 shows a functional block diagram of a decoder according to an embodiment of the present invention; and FIG. 10 shows a functional block diagram of a decoder according to another embodiment of the present invention.

Detailed description

The present invention prefers to use the SMLSE method because this method theoretically provides optimum performance. Other methods tend to be a trade-off between performance and complexity, especially for long constraint length codes, and the complexity of SMLSE grows exponentially with increasing constraint length. Thus, although the present invention can be applied to any decoding method, such as the majority voting method, the preferred embodiment of the present invention will be described in conjunction with the SMLSE method. However, this embodiment is for illustrative purposes only.

The present invention employs a preferred bit-history interruption method in preferred embodiments, and one of the preferred decoding termination methods.

20 Bit History Truncation Method; v, The present invention avoids making premature data bit decisions for interrupting bit histories. The main reason to routinely use truncation is to avoid the inconvenience of copying ever-longer bit sequences from one state to another when one of the precursor states is selected to survive. It is more appropriate if the amount of bit history retained is co-metric v with a fixed word length of the digital signal processing device, such as 16 or 32 bits. A preferred method, which can be implemented by: · schematically using the memory storage system illustrated in Figure 4, arranges for the copying of the advantage of fixed history lengths between modes without having to make a hard decision on the oldest bit.

When the bit history has grown to be equal to the maximum fit '·; · word length M, all 2 (L'1) bit histories are entered into the first storage memory 46, as indicated by 40, which is accessed by (L-1) - ·; ·: With bit address 42. The (L1) bit 35 address 42 corresponding to the associated bit history 40 is then placed in each state in place of the original M bit, as indicated by 13114515. It will be appreciated that (L-1) is assumed to be smaller than M so that the M-L + 1 bit positions of each word are made available for additional decoding. The decoding algorithm can then be executed further M-L + 1 times until each bit history word is full again, and the contents are again input-5, this time to another storage memory 46, as indicated by 41, replacing the M bits in each history with their (Ll) - bit addresses 42 in the second storage memory 46. This process is repeated until all bits are processed. Thus, in the K th storage memory 46, 2 (L'1) M-bit history words are named with their respective (Ll)-length addresses 42. Each of the M-bit words contains 10 M-L + 1 decoded bits 41, and (L1) - bit address 42 in the (K1) storage memory 46 where the immediately preceding decoded bits 41 are located, the corresponding (L1) bit address 43 after all the bits have been processed, the decoder memory 48 contains 2 (L'1) max. An M-bit history word named by their respective (L1) bit addresses 42. Each bit history word contains the last 15 decoded bits 44, where Q is less than or equal to M-L + 1, and an (L1) bit address 43 which corresponds to the (L1) bit address 42 in the last storage memory 46, where the immediately decoded bits 41 are located. The decoder memory 48 also contains the cumulative path metrics associated with each corresponding message of 2 <L "1) candidates.

Each of the 2 (L'1) candidates at the end of the whole message processing can be constructed by concatenating the contents of the external storage memories 46 using address bits 43 as chain pointers. The steps for constructing a candidate from a data message from a final state 0 are as follows **. vat: 25 1) Extract Q decoded data bits from 44 M bits of state 0 history:; decoder 48 in memory as the last decoded data bits.

2) Extract the (L-1) address bit 43 from the 0-bit history of the final state 0 and retrieve the M-bit word from external storage memory 46, which #_ corresponds to that extracted (L-1) bit address 43.

3) Extract the M-L + 1 decoded data bit from the retrieved word and paste it into Q into the decoded data bit 48 extracted from the decoder memory.

14 114S15 4) Extract the L-1 address bit 43 from the retrieved word and use them to point to the previously used external storage memory 46 retrieving the previous M-bit word corresponding to the (L-1) bit address 43.

5) Extract the M-L + 1 decoded data bits from the 41 words retrieved and paste them into the extracted decoded data bits already extracted.

6) Repeat steps 4) - 5) until the end of the chain is reached.

The attached extracted data bits then form the decoded final state 0 candidate. Candidates from other end states can be constructed in the same manner, starting from the appropriate state and chaining backwards.

Figure 5 illustrates an example of a mapping operation assuming a constraint length L = 3. The final state in the decoder memory 48 having the smallest cumulative path metric 45 is the final state 10 (Gpm (10) = 2.0) with the last decoded data bits 44 being 01 (Q = 2). The extracted 2-bit address 43 is 00, and the 3 data bits 41 taken from the corresponding 00 address 42 in the 4th memory 46 are 110, which are mapped to 01, the last decoded data bits 44, resulting in 110-01. The next extracted 2-bit address 43 is 10, and the following 3 data bits 41 extracted from the corresponding 10-decoded 42 address 42 in the third memory 46 are 110, which when connected to a growing chain produces 110-110-01. The next extract 20 bit 2-bit address 43 is 01, and the next 3 data decoded data bits 41 extracted from the corresponding 01 address 42 42 in 2 memory 46 are 011, which when connected to a growing chain produces 011-110-110-01. The last extracted 2-bit address 43 is 11, and the remaining 5 data bits 40 extracted from the decoded corresponding 11 address 42 in the 1 memory 46 are 11101 which, when connected to the incremental chain, finally produces 11101-011-110-110- 01, to the decoded message candidate belonging to the decoded final state 10. Other final states include candidates: '. The shafts can be constructed in the same manner starting with a suitable space and chaining backwards with the results given in Figure 5.

Preferred methods for terminating the decoding • 30 Preferred methods for terminating the decoding retain a number of candidates, for example 2 (L'1).

. * · *. One preferred method utilizes end bits, but> a \ does not reduce the number of spaces at the end. Known end bits are used in the de- »* '·· ** encoder to predict for each state which parity bits should be received: 35 and the state metric is simply updated without any overwriting. Thus, «114515 15 2 (L'1) candidate data sequence is thus left at the end. Known end bits may be, as in the example bit sequence 50 shown in Fig. 6, an L-1 zero sequence 54 associated with an N1 + N2 bit sequence 52 (consisting of N1 message data bit and N2 error check bit).

Together with Fig. 3, an example of a preferred method for terminating decoding using predetermined end bits to decoder 32 in Figs. 1 and 2 is described, assuming a code constraint length L = 5, rate 1 / r = 1/2. Assuming that the last bit input to the 5-bit shift register in encoder copy 38 is the first of the known 4-bit end bit 10s 54, the steps to terminate decoding are as follows: 1) For the first state number 0000, it is "assumed" that the new bit is 0. The default 00000 as received information bits is thus supplied to copy 38 of encoder 22 to provide two parity bits P1 (00000) and P2 (00000) that could be expected.

2) The actual received parity bits P1 (real) and P2 (real) are compared with the default parity bits P1 (00000) and P2 (00000). The comparison results in either a complete matching of both bits, or a single mismatch of one of the two bits and a single mismatch of the other two bits, or a complete mismatch of both bits. If both P1 (00000) and P2 (00000) match f. ·. to the actual received parity bits P1 (real) and • «P2 (real), the number 0 is added to the routing metric, Gpm (0000) associated with state 0000. Similarly, if there is only one match, the number '1 is added to the 0000 routing metric Gpm (0000). If neither Pi (00000) nor P2 (00000) matches the actual received parity bits P-ι (real) and P2 (real), the value two is added to the 0000 path metric Gpm (0000). The new bit history 33 for 0000 is then ... T 30 ten 00100110, with the rightmost bit corresponding to the leftmost bit of 0000 in the 5-bit code copy.

:! ·. 3) Steps 1) and 2) are now repeated for 1000. "Assuming" the new I · 5th bit is 0, 10000 is input to encoder copy 38, and its output Pi (10000) and Ρ2 (10000) are compared to the received 35 to data P1 (real) and P2 (real). The routing metric for: "i 1000, Gpm (1000), is then updated as in step 2) based on comparing the actual received parity bits Pi (real) and P2 (real) with the default parity bits P100000) and P2 (10000). New bit history 33 instead of 1000 is then 10110111, whose rightmost bit corresponds to the 10,000 leftmost bits of the 38 bit pattern of the 5-bit encoder-5 copy.

4) Steps 1) to 3) are repeated for all other pairs of the preceding states 0001 and 1001, 0010 and 1010, 0011 and 1011, 0100 and 1100, 0101 and 1101, 0110 and 1110, and 0111 and 1111.

At the end of one of the foregoing iterations, two received 10 parity bits are processed and one new decoded bit is transferred to all bit history memories 33. Steps 1) to 4) are then repeated 3 more times for the 3 remaining bit 54s.

Another preferred method of deciding uses a method known as tail biting. In this method, the encoder uses a first-to-first encoded data bit to re-input through the last data bit. Similarly, the decoder uses the first decoded bits of each candidate cadet message together with assumptions of the last data bits to predict received parity bits and updates the metric accordingly without any overwriting, thus retaining all 2 (L'1) candidates at the end. Fig. 6a 20 shows an example of a bit sequence 52 that can be used for tail biting termination. The bit sequence 52 contains Ni + N2 bits, the first L-1 bits serving as "tail bits" which are previously unknown to the decoder 32 in Figures 1 and 2 and used to input the last bit of the bit to be encoded. ···. through the L-bit shift register 24 in encoder 22 of transmitter 20.

Together with Figure 3, an example of a preferred tail biting decoding termination method is described, assuming »· ♦ that the code constraint length is L = 5, rate 1 / r = 1/2. Assume that the last of the bits entered into the 5 * · · '' bit shift register in encoder copy 38 is the first of the unknown 4-bit "tail bits" 56, i.e. the first ... j '30 bits that should have been decoded. Suppose further that the first bit that needed to be decoded happened to be 1. The steps to complete the decoding are; The following: I · · 'II. · 1) For the first state number 0000, it is "assumed" that the new bit is 1. The default 00001 for received information bits 35 is thus supplied to copy 38 of encoder 22 to provide two •: · i parity bits Pi. (00001) and P2 (00001) that could be expected.

114515 17 2) The actual received parity bits Pi (real) and P2 (real) are compared with the default parity bits Pi (00001) and P2 (00001). The comparison results in either a complete match of both bits, or a single mismatch of one of the two bits and a single mismatch of the other two bits, or a complete mismatch of both bits. If both P- (00001) and P2 (00001) match the actual received parity bits Pi (real) and P2 (real), the number 0 is added to the routing metric, Gpm (OOOO) associated with state 0000. Similarly, if there is only one match, the number 1 is added to the 0000 routing metric Gpm (0000). If neither Pi (00001) nor P2 (00001) matches the actual received parity bits Pi (real) and P2 (real), the value two is added to the 0000 path metric Gpm (0000). The new bit history 33 in place of 0000 is sit-15 00100110, with the rightmost bit corresponding to the leftmost bit of 00001 in the 5-bit code copy 38.

3) Steps 1) and 2) are now repeated for 1000. "Assuming" the new 5th bit is 1, FIG. 10001 is input to encoder copy 38 and its outputs Pi (10001) and P2 (10001) are compared with received data Pi ( real) and P2 (real). The path metric for 1000, Gpm (1000), is then updated as in step 2) based on comparisons of the actual received parity bits Pi (real) and P2 (real) with the default parity bits Pi (10001) and. P2 (10001). The new bit history for 33 instead of 1000 is then, · 25 10110111, whose rightmost bit corresponds to a 5-bit encoder,

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* copy 38 of the leftmost bit of Figure 10001.

4) Steps 1) to 3) are repeated for all other pairs of the preceding states: 0001 and 1001, 0010 and 1010, 0011 and 1011, 0100 and 1100, 0101 and 1101, 0110 and 1110, and 0111 and 1111.

30 At the end of one of the above iterations, two responses * are processed the retrieved parity bit and one new decoded bit are transferred to all bit history memories 33. Steps 1) to 4) are then repeated 3 more times for the 3 remaining »» »bits" 56 "assuming that in each case a new 5: des bit is * · same as any received bit was. For example, if the 2, 3, and 35 4 decoded bits were assumed to be 0, 1, and 1, then in the second iteration of steps 1) - • * »·» 18 114515 4) the new bit is "assumed" to be 0 , In the 3rd iteration, the new bit is "assumed" to be 1 and in the 4th iteration the new bit is "assumed" to be 1.

An alternative decision for a tail biting decoder is to continue decoding in a circle until the number of last decoded bits 5 equals the same bits when first decoded, either in the state with the lowest metric, the number of Z states with the lowest metric in Z, or how many candidate sequences are required out of the decoder. Figure 6b shows an example where K bits 58 (in the Nh + NaJ bit sequence represents the number of matching bits when 10 are decoded twice during continuous decoding of bit sequence 52 to which decoding is terminated. In order to input the last bit through the L-bit shift register 24 20 in encoder 22 would be effective, either K should be at least equal to L-1, or if K is less than L-1, K-bit sequence 58 should suitably reside in bit 52. For example, if K is less than L -1, the rightmost K bits 58 must be at least LK-2 bits to the left of the rightmost bit in the bit sequence 52.

A known method for selecting a final data message is simply to select a state with a Low Cumulative Metric.

Embodiments of the Preferred Embodiments Block diagrams for implementing the preferred embodiments of the invention * · ·. shown in Figures 1, 2, 7, 8, 9, and 10.

Referring to Figures 7 and 8, a data message 60 consisting of a message bit to be transmitted from the Ni transmitter 20 is inserted with an error detector; but to code generator 28, which generates cyclic redundancy check 25 (CRC) by computing a division residual resulting from polynomial division of the data message 60 by the selected CRC polynomial (not shown). For example, the simplest polynomial is 1, and dividing the remainder by 1 of any data bit sequence results in exactly this data bit sequence re-generating a simple excess ····. More complex polynomials generally produce more complex divisions - · I ·. ···. 30 remains, as is well known. See, for example, Line and Costello, "Error, * 'Control Coding," Prentice-Hall (1983), Chapter 4.5 (ISBN 0-13-283796-X), which is incorporated herein by reference. The CRC splitter 64 consisting of the N2 error check bit is then appended to the Ni message bit 60, making a total of N1 + N2 bits 66, which are then supplied to the input of the convolutional error correction encoder

I I I

35 weather conditions. Depending on whether or not the tail biting process described above is used, an L-1 null can be added, where L is the constraint length of the convolutional code 191145, making a total of L-I + N1 + N2 bits. If the tail bite is used, the first L N1 + N2 bits 66 are loaded into the coding shift register 24, while if the tail biting is not used, the L-1 resets plus the first N1 data message bit 60 is loaded into the coding shift register 24.

The outputs of the shift register 24 are coupled to the inputs of the combination logic network 26 forming the parity bits 74 to be transmitted. An alternative shown in Fig. 8 is to use L bits in the shift register to point to a 2L element lookup table 27 in the electronic memory storing a suitable parity-bit combination for each possible shift register bit pattern. In the case of each of the 10 chips, the number of parity bits 74, which is relative to the inverse of the code rate 1 / r, is produced for each shift of the shift register 24. After the last N2 of the CRC bit 64 has been input, it is passed through repeating the first encoded bits which, in the case of a tail bite, means re-entering the first L-1's N1 + N2 bits 66, or without an initial 15 of the L-1. This can be accomplished by the fact that if the table of N1 + N2 bit 66 or L-I + N1 + N2 bit is considered to form a circle, then there is no difference in the operation of encoder 22 in either case.

The number of parity bits 74 transmitted from the transmitter 20 is either 20 (Ni + N 2) r or (L-1 + Ni + N 2) r, and these are successively supplied to modulator 76 for conversion to a suitable format for communication medium 78, e.g. for the passage of the di-channel.

• · * »· ·

Referring now also to Figs. 9 and 10, the detector 82 in the receiver 30 processes the received signal 80 through the communication medium 78 (e.g., a radio channel) to form estimates of the re-transmitted parity bits * / 74. These can be "hard" decisions 84 (binary 1's or 0's) or * · · "soft" decisions 85, as shown in Figure 10, which are ideally •; ; the probability that the parity bit is 1 or 0, respectively, is an estimate of the logarithm. Hard 84 (or soft 85) parity bit information is then provided to the Viterbi-30 SMLSE convolutional decoder 86, which operates in the preferred mode described above; '':

: * ·, If tail biting is used, then 2 (L'1) states correspond to * »· all the first unknown L-1 bits N1 + N2 of bit 66, and their> · T * path metrics are initialized to equal initial values , for example, zero. The decode: ,,,: 35 us then proceeds as described. If tail continuity is not used, only state 0 that corresponds to the initial zero entered into the shift register of the L-1 encoder 22 may exist and its path metric is initialized to zero. After one decoding iteration, two states are generated corresponding to the first unknown data message bit being 0 or 1. After the L-1 decoding iteration, all 2 (L * 1) states are active and then the decoding proceeds normally.

After performing Viterbi decoding, the number of 2 (L'1) of the candidate (Ni + N2) bit sequences is available in memory 94, each with an associated path metric value. The end state path metric 88 is passed to the path metric sorter 90, which arranges the end state path metrics 88 in descending order of value. The candidate (Ni + N2) bit sequences are then ordered using this sorted address sequence 92 and the candidate (N1 + N2) bit sequence is retrieved from memory 94 and exported to CRC calculator 98. CRC calculator 98 determines whether the attached N2 a bit CRC word N1 data message bits. The first candidate (N1 + N2) -bit sequence, which is found to have a valid CRC sequence, is then selected for its candidate N1 data message output 100. If no valid CRC is found and the CRC also has a limited error correction capability, the candidate (Ni + N2) bit sequences are scanned again in a sorted metric order to find individual errors to be corrected. The first candidate (Ni + N2) bit sequence that is found to contain a single error to be corrected is then selected, and the error is corrected. This procedure can be repeated up to the maximum allowable error correction capability of the CRC code.

; '; The present invention, which in one aspect is characterized by selecting the Nth best output of the error-correcting decoder according to the gene expression verification procedure, can also be applied to non-convolutional t · 25 coding formats such as, for example, block code, : with daus. For example, a small number of message bits at a time can be converted to a redundant block code, and a plurality of such block codes are transmitted to carry the entire message, including the CRC word. If some undetected errors are left after performing the CRC check after decoding, the quality of the block decoding can be examined and the least reliable block can be identified. The least reliable transmitted bit in the least reliable block can then be inverted and decoded by the block, re-checked by the CRC. If this fails, the second most unreliable bit or block can be modified and so on. Such embodiments of the present invention for block coding mode can be designed in detail by someone for whom coding and decoding theory; ·: Are familiar.

21 114515

While certain embodiments of the present invention have been shown and described, it should be understood that the invention is not limited thereto, as modifications may be made by those of ordinary skill in the art to which the subject matter pertains. The present application contemplates any and all other claims which fall within the spirit and scope of the present invention as disclosed and claimed herein.

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Claims (17)

22 11 4 51 5 A communication system for providing error reduction in the transmission of telecommunication signals, comprising: a transmitter comprising: an error detection signal generator for generating an error detection word corresponding to a data message to be transmitted; an error correction encoder for encoding said data message and said error detection check word; A receiver comprising: an error correction decoder for receiving and decoding an encoded data message and an encoded error detection check word, said decoder comprising: means for providing a plurality of candidate bit sequences corresponding to N ιοί 5 most despread candidate message data and first candidate information; means for computing a plurality of other error detection bits for each of the echocod bit sequences as a function of the decoded message data bits; means for comparing said second error detection bits of said candidate bit sequences with said first detection bit estimates of said candidate bit sequences to generate an error detection syndrome; : means for selecting the first candidate message candidate bit- »tl i * · '; the highest probability sequence and the error detection syndrome * ". does not indicate errors, and if there is no such candidate, to select the second candidate message from the highest probability candidate sequence whose syndrome indicates the number of errors to be corrected, and to correct said bit error A rigid system according to claim 1, wherein said data message and said error detection check word are encoded using convoy-30 lution codes. The system of claim 1, wherein said decoder utilizes sequential maximum likelihood sequence blocking techniques to decode said encoded data message and said encoded error detection word. The system of claim 1, wherein said decoder includes a memory for storing default bit states, a history of selected bits for each of the default bits mentioned, and a reliability factor for storing each of said default bit states. The rigid system of claim 1, further comprising: a transmitter having a convolutional encoder including: 5 L-bit shift register data message information information L bits and error detection check information information, wherein L is the convolutional code constraint length; a logical circuit for logically combining certain of said L bits to produce parity bits; and 10 means for transmitting said parity bits. The system of claim 1, wherein said encoded data message and said encoded error detection check word are parity bits. The system of claim 1, wherein said data-15 message includes a message bit to be transmitted and an error detection bit of N2 error detection check word. The system of claim 7, wherein said N2 error detection bits are a residue when dividing said N1 message bits by a polynomial cyclic redundancy check polynomial. The rigid system of claim 1, wherein said error-correcting encoder is initialized and terminated by encoding bits which are "" unknown to said decoder. * · »| The system of claim 1, wherein said error-correcting encoder is initialized and terminating with coding bits known to be available for said decoder. 11. A data transmission method adapted to reduce transmission:; occurring data bit errors, including the steps of: '' compiling a plurality of data bits in a message to be transmitted; calculating a plurality of first error detection bits as a function of said sa-30 nomadabits; :: appending said error detection bits to said message; :. ·. encoding said message and said associated error detection bits in a error correction encoder to produce a plurality of coding bits for transmission from said encoder; 11,11515 modulating said coding bits; transmitting said modulated coding bits via a communication medium; receiving estimates of the transmitted bits; Demodulating said received estimates; decoding said demodulated estimates in an error correction decoder; generating a plurality of candidate bit sequences corresponding to the N most probable transmitted candidate message data and the first candidate viral expression bit sequence; calculating for each of said candidate bit sequences a plurality of other error detection bits as a function of the decoded data bits; comparing said second error detection bits of said candidate bit sequences with said first error detection bit ester 15 bits of said candidate bit sequences to form an error detection syndrome; and selecting, from the candidate bit sequences, the first candidate message having the highest probability and the error detection syndrome not detecting errors, and if there is no such candidate, selecting the second candidate message having the highest likelihood and syndrome indicating the number of errors to be corrected; candidate message. The data transmission method of claim 11, wherein v. Said first and second error detection bits are a residue when dividing said message data bits by a polynomially cyclic redundancy check polynomial. The data transmission method of claim 11, wherein said error correction coding is convolutional coding. • · The data transmission method of claim 13, wherein said error correction coding is tail-biting convolutional coding, further comprising the steps of: initializing said encoder by inserting unknown data bits to said receiving decoder. before said shipment; and:, terminating said encoder by re-entering said data bits. • · The data transmission method of claim 13, wherein said error correction coding is convolutional coding, further comprising the steps of: initializing said encoder by input to said receiving decoder a known bit pattern prior to said transmission; and terminating said encoder by re-entering said bit pattern. The data transmission method of claim 11, wherein said error-correcting decoding uses a sequential maximum likelihood sequence estimation Viterbi algorithm. The data transmission method of claim 11, further comprising the steps of: sorting the candidate bit sequences after decoding the entire input signal in ascending order according to routing metrics corresponding to said final states of the decoder to determine the order of said error detection bit comparisons. * · • · * * · I «I I * t I · I I · 26 1 1 451 5