JPH02111121A - Driving method for circuit using clocked gate inverter - Google Patents

Abstract

PURPOSE:To make the operation of gate stable by inputting logic signals including a timing where logic is not inverted and being other signals than the inverted logic signals to gates comprising p-channel and n-channel transistors(TRs). CONSTITUTION:Logic signals phi1, phi2 are supplied even to a clocked gate inverter 1b of a 2nd stage in the case of applying the circuit to a shift register circuit and the logic signals phi1, phi2 of the opposite polarity to above are supplied to a clocked inverter 1c of a 3rd stage. Then the timing as to the logic signals phi1, phi2, that is, a time difference DELTAt is selected to nearly a time DELTAT where the pulse is unsharpened. For example, in the case of a clock signal in 1MHz, the time DELTAT is selected to be 60nsec. Thus, the overlap of the transition time of the ON/OFF of the two logic signals phi1, phi2 is almost eliminated. Then a shift register circuit operated more stably is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for driving a circuit using a clocked gate inverter applied to a shift register circuit or the like.

2. Description of the Related Art In general, when controlling the operation of an entire circuit using a clock signal, the circuit is often constructed using a clocked gate inverter whose output can be separated from the input according to the clock signal.

The circuit of such a locked gate inverter 1 is normally constructed as shown in FIG. That is, the power supply VDD
and ground, a p-channel transistor Q for input,
and an n-channel transistor Q2, a p-channel transistor Q for gate input to which an inverted clock signal φ is input, and an n-channel transistor Q4 to which a clock signal φ is input are connected in series. With such a configuration, the output and input can be separated in synchronization with the clock signal φ. That is, when the clock signal φ is at the H level, the inverted clock signal φ is at the L level, so the transistor Q and the source-drain of the transistor Q are in a low resistance state (that is, in the on state), and the output voltage changes according to the input terminal. is in a state of change. Conversely, if the clock signal φ is 1. Since the inverted clock signal φ is at the H level, the source and drain of transistors Q and Q4 are in a high resistance state (i.e., off state), and even if the input voltage changes, the output voltage will not leak current. It does not change and remains constant within a negligible range.

This is an example of a clocked inverter synchronized to the clock signal φ, but the l-transistors Q,,Q.

By inverting the signals as gate inputs to φ and φ, respectively, a clocked gate inverter synchronized with the inverted clock signal φ is obtained.

Here, in order to simplify the explanation, in the following explanation, symbols as shown in FIG. 10 will be used for the clocked gate inverter 1. This FIG. 1Q is shown isometrically in FIG. 9, in which the logic signal φ, indicated by the arrow pointing toward the clocked gate inverter 1, is applied to the n-channel transistor Q4 as shown in FIG. Indicates gate input. In addition, the logic signal φ shown by the arrow coming out from the clocked gate inverter in the figure is a gate signal for the p-channel transistor Q, as shown in FIG.
Indicates input. The operation of the clocked gate inverter 1 is shown in a timing chart as shown in FIG. 11.

According to this timing chart, the rising edge of the input signal to the input signal and the falling edge of the clock signal φ occur at the same time, but this is a common occurrence in clock-controlled circuits; This corresponds to a case where the signal changes in synchronization with the inverted clock signal φ.

Problems to be Solved by the InventionHowever, in the same timing chart No. 11, when the rising and falling states of the input signal and the clock signal φ are enlarged, the actual results are as shown in FIG. 12. , the pulse waveform has a so-called "drop" or "accent",
level or L level. Such a phenomenon inevitably occurs due to gate capacitance, parasitic capacitance, resistance, etc. in the circuit. In FIG. 12, changes in the input signal and the clock signal φ are shown superimposed to make the explanation easier to understand.

As mentioned above, the output is separated from the input at the falling edge of the clock signal φ, but in reality, as shown in Figure 12, there is an "abortion" in the pulse waveform, so it may not work as expected. There is. In other words, the gate input transistors Q, , Q, which are initially turned on, gradually increase their resistance as the clock signal φ falls, but the resistance of the gate input n-channel transistor Q in particular increases sufficiently. If the resistance of the input n-channel transistor Q2 decreases with the rise of the input signal before the input signal rises, the charge at the output terminal that should be maintained at H level escapes to the ground, resulting in a decrease in the output voltage. It will end up being put away. Such a phenomenon occurs, for example, when the threshold voltage Vru of the input and gate input n-channel transistors Q, , Q is at the level 2 shown in FIG. In other words, in such a case, τ, ~・
This is because these transistors Q, , Q are both turned on during τ2. Incidentally, even if the threshold voltage VTR of the human-powered n-channel transistor Q2 is at a level like ■1 shown in FIG.

If the threshold voltage VTH is low as shown in (2), there will still be a timing when the resistance between the output and the ground becomes low between τ and τ2, causing a drop in the output voltage. This can occur not only due to the threshold voltage of the transistor, but also when noise is introduced into the clock signal or input signal.

Means for Solving the Problems The gates of the p-channel non-channel transistor and the n-channel transistor that perform the gate operation of the clocked gate inverter are provided with logic signals that are inverted with respect to each other. Input a logic signal that includes timing that does not exist.

Since the operating logic signals have timings that are not inverted in logic, there is a timing when the fall of one logic signal is always earlier than the rise of the other logic signal, so it is synchronized with the rise of one logic signal. It operates stably even with human input signals. Therefore, the operation will not become unstable due to variations in the threshold voltages of the transistors.

Embodiment An embodiment of the present invention is illustrated in FIGS. 1 to 8.
jiJ. The same parts as those shown in FIGS. 9 to 12 are indicated using the same reference numerals.

First, the basic idea of this embodiment will be explained. clock signal φ
As shown in the enlarged timing chart of Fig. 2, the falling edge of the input signal is relatively early compared to the rising edge of the input signal.
Threshold hole l-1'' of transistors Q, , Q,
4i, Eν'Tl+ and without being affected by minute noise, the clocked gate inverter I
can operate stably. As mentioned above, this type of timing-based operation occurs when an input signal that changes in synchronization with the ffh of the inverted clock signal φ is gated at the falling edge of the clock signal φ, and is shown in FIG. The timing operation shown is to delay the rising edge of the inverted clock signal φ with respect to the falling edge of the clock signal φ. Instead of the inverted Glock signal φ, φ, as shown in FIG.

This means that two logical signals called φ2 are used. In the figure, the broken lines are the normal clock signal φ and the inverted clock signal φ. In other words, logic signals φ1 . φ2 is the first
As can be seen from the figure, the normal signals φ and φ have different pulse widths, and include timings whose logics are not inverted from each other; 7 With the configuration shown in FIG. If used instead of the signals φ and φ, stable gate operation can be performed even with a signal synchronized with the rise of the logic signal φ2.

Next, we will consider how an actual circuit operates using such a driving method. First, there is one problem with the driving method of this embodiment.

Logic signal φ1. The question is whether there is a risk of malfunction when φ is used in place of the normal clock signal φ or the inverted clock signal φ. One possibility is that the logic signal φ0. When φ and both are at L level and the input signal is also at L level, the output becomes H level. Malfunctions caused by this can occur, for example, when the circuit is configured as shown in FIG.

That is, in a configuration consisting of three stages of clocked gate inverters 1a to 1c, signal φ8 in the figure is φ, and φ2
If φ is a conventional dynamic shift register circuit, the input signal is transmitted to the next stage while being delayed by 172 cycles of the clock signal φ. However, according to the driving method using the logic signal as shown in the figure, as shown in the timing chart of FIG. It is synchronized with the U downlink of the signal φ. Further, in the clocked gate inverter 1c in the third stage, the signal is not cut in accordance with the logic signal φ1, and the logic signal φ1 rises at the same time as the rising edge of the clocked gate inverter 1b which is 2J smaller.

Therefore, when the driving method of this embodiment is applied to a shift register circuit, it is necessary to configure it as shown in FIG. That is, the second stage clocked gate inverter 1b
Also, logic signals φ1゜φ2 are applied to 3
Logic signal φ1 for the clocked inverter IC in the second stage
．． φ2 is the opposite of the case in FIG. In the case of such a configuration, operations are performed according to a timing chart as shown in FIG. According to this timing chart, the clocked gate inverters la, 1. The rises of the output pulses b and lc are not at equal intervals. However, in this respect, for example, the logic signal φ1. It would be better to take the AND of φ2 or use every other output 1, for example, the output of clocked gate inverters La and lc. If all the output pulses of the global toggle inverters 1a, lb, and Ic are used, the number of inverters per output can be reduced compared to the case of a normal dynamic shift register.

Next, logic signal φ1. Consider how much timing, ie, time difference Δt, should be added to φ2.

First, let us consider the case where the typical pulse waveforms of the normal clock signal φ and the inverted clock signal φ are rounded as shown in FIG. In the figure, ■.

is the threshold voltage VTH1 of the p-channel transistor Q1 for input; 5 is the threshold voltage of the p-channel transistor Q for gate input; T+
1, ■6 is the threshold voltage VTII of the n-channel transistor Q2 for human power, ■7 is the threshold voltage VTR of the n-channel transistor Q4 for gate input, and 8T is the time during which the pulse is dulled. First, focusing on the n-channel, during the period τ6 to τ7, both transistors Q2. Both Q4 are turned on, preventing gate operation. Also, focusing on the p-channel, both transistors Q l during the period τ, ~τ
+Q3 are both turned on, similarly preventing gate operation. Therefore, the time difference Δt is (8 at τ7−) and (τ
, -τ6), it is better to choose the larger one. In fact, it is sufficient to add a time of about T to the time during which the pulse is dulled.

More practically, an example of a normally used clock signal φ and an inverted clock signal φ is shown in FIG. 8(b). this is,
This is an example of a l MHz clock signal.

In this case, the magnitude of the time T during which the pulse waveform is distorted is determined by the function knob of the clock generation circuit, the capacity of the shift register section, and other factors, but in the example shown here, both the rising and falling edges are It used to take about 60 nsec as T.

Therefore, as mentioned above, the time difference Δt2 is ΔT=60
nsec, and the logic signal φ1. By advancing the fall of φ2 by 60 nsec, the two logic signals φ1. The overlap of the on/off transition times of φ2 can be almost eliminated.

Logic signal φ1. having timing as shown in FIG. 8(a). If φ2 is operated using the circuit configuration shown in FIG. 5, a shift register circuit that operates more stably can be obtained. Further, according to such a configuration and driving method, it is possible to reduce the number of inverters in the shift register section.

Note that in the timing chart shown in FIG. 1, the logic signals φ1. The falling timing of φ2 is the same as the other logic signal φ2. This is earlier than the rise of φ1. This is because the above-mentioned situation can also occur in the opposite case, that is, when an input signal synchronized with the rising edge of the clock signal φ is gated at the falling edge of the inverted clock signal φ. Therefore, depending on the circuit configuration, it is not always necessary to do this, and it may be sufficient to make only the fall of one signal φ1 or φ2 earlier than the rise of the other signal φ2 or φ.

Effects of the Invention As described above, the present invention provides signals that are a combination of logic signals that are inverted to each other and that are inverted to each other for the gates of the p-channel transistor and the n-channel transistor that perform the gate operation of the clocked gate inverter. By inputting a logic signal that includes timing that does not exist, there will always be a timing where the fall of one logic signal is earlier than the rise of the other logic signal, even if the signal is synchronized with the rise of one logic signal. The gate operation is stable, and the operation is not unstable due to variations in the threshold voltage of the transistor, and stable operation can be performed.

[Brief explanation of drawings]

FIG. 1 is a timing chart showing an embodiment of the present invention;
Figure 2 is a timing chart showing the basic concept, Figure 3 is a circuit diagram of the shift register circuit configuration, Figure 4 is a timing chart showing its operation, and Figure 5 is a circuit diagram of the shift register circuit configuration according to this embodiment method. , FIG. 6 is a timing chart showing the operation, FIG. 7 is an explanatory diagram of the timing to shift, FIG. 8(a) is a timing chart according to the method of this embodiment, FIG. Fig. 9 is a basic circuit diagram of a clocked gate inverter showing a conventional example, Fig. 10 is its symbolic circuit diagram, and Fig. 11 is a basic circuit diagram of a clocked gate inverter showing a conventional example.
The figure is a timing chart showing the operation. FIG. 12 is a timing chart showing an enlarged portion of the timing chart. 1...Clocked gate inverter, Q3...p channel transistor, Q4...n channel transistor, φ1. φ2...logic signal, mi

Claims (1)

[Claims] Inputting logic signals other than mutually inverted logic signals, including timings whose logics are not mutually inverted, to the gates of p-channel transistors and n-channel transistors that perform gate operations of a clocked gate inverter. A method for driving a circuit using a clocked gate inverter.