JPH02111031A - Manufacture of mos integrated circuit - Google Patents

Abstract

PURPOSE:To keep a direct-contact resistance value between a polysilicon layer and an N-type source-drain diffusion layer low by a method wherein a sidewall is removed selectively inside a direct contact hole. CONSTITUTION:A silicon oxide film 2 in a prescribed region on a silicon substrate 1 is removed selectively; a direct contact hole 3 is made. Then, a polysilicon layer 4 is grown; it is doped with phosphorus; an N-type diffusion layer 5 is formed. Then, the polysilicon layer 4 is removed selectively; a gate electrode is formed; a phosphorus ion 6 is implanted by making use of the gate electrode as a mask; an N-type diffusion layer 7 is formed. Then, sidewalls 8, 9 of the silicon oxide film 2 are formed; the sidewall 9 at the inside of the hole 3 is removed selectively; after that, an arsenic ion 10 is implanted by making use of a polysilicon electrode and the sidewalls 8, 9 of a silicon oxide film as a mask; an N-type source-drain diffusion layer 11 is formed. The N-type diffusion layer directly under polysilicon is connected directly to the source-drain diffusion layer; accordingly, a direct contact resistance is not increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a MOS semiconductor integrated circuit having direct contact between a polysilicon layer and a diffusion layer on a substrate semiconductor.

(Prior Art) As a technique for improving the integration density of MOS integrated circuits, a buried contact technique between a polysilicon wiring layer and a diffusion layer on a silicon substrate has been commonly used. First, an example of a conventional direct contact forming process will be described with reference to FIG. In the figure, a predetermined region of the gate oxide film 21 on the substrate 22 is selectively removed to form a direct contact hole 2.
A polysilicon layer 24 is then formed on this hole, and an N-type impurity (for example, phosphorus) is diffused into this polysilicon layer 24. N-type impurities are diffused into the silicon substrate through the formed opening, and an N-type diffusion layer 25 is formed under the opening (see FIG. 2).
b)]. Next, the polysilicon layer 24 is selectively removed to form a gate electrode and wiring [FIG. 2(C)].

At this time, a considerable amount of the surface of the exposed bottom of the contact hole is removed when the polysilicon layer 24 is selectively removed.

Next, using the previously formed polysilicon gate electrode as a mask, N-type impurity ions 26 are implanted to form a source/drain diffusion layer 27 (FIG. 2(d)).

The polysilicon layer is thus electrically connected to the N-type source/drain diffusion layer on the silicon substrate via the N-type diffusion layer directly below the direct contact hole.

(Problem to be solved by the invention) In recent years, as the gate length of MOS transistors has become shorter, deterioration of transistors due to hot electrons generated by a high electric field near the drain has become a major problem. Low concentration n- by ion implantation using the gate electrode as a mask
LD manufactured by a layer formation process and a highly concentrated 04 layer formation process by ion implantation using the gate electrode and sidewalls formed of an insulator at both ends of the gate electrode as a mask.
D (Lightly-Doped-Drain)
(Reference 2, "Micro Devices," published by Nikkei McGraw-Hill, August 22, 1983). When the direct contact technique described in the previous section is used for an integrated circuit having an N-type MOS transistor of this LDD structure, the following problems occur. That is, in FIG. 3, under the side wall 28 formed on the end surface of the polysilicon layer 24 overlapping with the direct contact hole 23 is a thin N-type diffusion layer 29, and a dense N-type diffusion layer immediately below the polysilicon layer. 25 and the source/drain diffusion layer 27 are not directly connected.

Therefore, the resistance value of polysilicon, silicon substrate, and direct contact increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an MO'S integrated circuit that solves the problem of direct contact resistance deterioration that occurs when the LDD structure is adopted.

(Means for Solving the Problems) A method for manufacturing an MO3 integrated circuit according to the present invention includes a first step of forming a gate insulating film in a predetermined region on a P-type semiconductor substrate or a P-type well region; a second step of selectively removing and opening a predetermined region of the gate insulating film; a third step of forming a polysilicon layer on the gate insulating film; and doping the polysilicon layer with an N-type impurity. a fourth step of selectively removing the polysilicon layer to form a gate electrode; and a sixth step of ion-implanting N-type impurities using the gate electrode as a mask.
a seventh step of forming sidewalls made of an insulating material at both ends of the gate electrode; and an eighth step of selectively removing the sidewalls formed in the seventh step within the opening region formed in the second step. and a ninth step of ion-implanting N-type impurities at a high concentration using the gate ff electrode and the sidewall as a mask.

(Function) In the present invention, after the insulating side walls for forming the LDD structure are formed at both ends of the polysilicon gate electrode.

Selectively removing the sidewall within the direct contact hole. Therefore, inside the direct contact hole, a lightly doped N-type diffusion layer is not formed at the end of the polysilicon layer, and the heavily doped N-type diffused layer immediately below the polysilicon is directly connected to the source/drain diffusion layer. Therefore, no increase in direct contact resistance occurs.

(Example) An example of the present invention will be described with reference to FIG. normal MO
After forming an element isolation region and a silicon oxide film 2 on a silicon substrate 1 by the manufacturing method of an S integrated circuit [FIG. 1(a)], the silicon oxide film 2 in a predetermined area is selectively etched by a photomask etching method. to form a direct contact hole 3 [FIG. 1(b)]. Next, a polysilicon layer 4 is grown using a low pressure CVD method (in this example, the film thickness is 400 nm), and the polysilicon layer 4 is doped with phosphorus using a vapor phase diffusion method. Doping was carried out at 1000° C. for 30 minutes.

As a result, the silicon substrate in the direct contact hole is doped with phosphorus through the polysilicon layer 4, and an N-type diffusion layer 5 is formed [FIG. 1(C)]. Next, the polysilicon layer 4 is etched using a photomask dry etching method.
is selectively removed to form a gate electrode and wiring.

Next, using this gate electrode as a mask, N-type impurity ions 6 (phosphorous ions in this example) are implanted to form a thin N-type impurity ion.
A type diffusion layer 7 is formed [FIG. 1(d)]. Next, the reduced pressure C
After growing the silicon oxide film 2 over the entire surface by the VD method, the silicon oxide film 2 is etched back by the dry etching method to form sidewalls 8 and 9 of the silicon oxide film 2 on the side surfaces of the polysilicon (see FIG. 1). e)]. In this example, the thickness of the silicon oxide film sidewall is 250 nm. Next, after selectively removing the silicon oxide film side wall 9 inside the direct contact hole using a photomask wet etching method, using the polysilicon electrode and the silicon oxide film side wall as a mask, N-type impurity ions 10 (in this example, Arsenic ions) are implanted to form an N-type source/drain diffusion layer 11 [FIG. 1(f)]. The subsequent steps are the same as those for manufacturing a normal MOS type semiconductor integrated circuit.

(Effects of the Invention) According to the present invention, in an integrated circuit having an N-type MOS transistor with an LDD structure, the direct contact resistance value between the polysilicon layer and the N-type source/drain diffusion layer can be kept low. Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a process sequence diagram explaining the present invention in detail, and FIGS. 2 and 3 are diagrams showing an example of a conventional direct contact forming process. 1... Silicon substrate, 2... Silicon oxide film,
3...Direct contact hole, 4...Polysilicon layer, 5...N-type diffusion layer generated by diffusion of N-type impurities through the polysilicon layer. 6.10... N-type impurity ion, 7... N-type diffusion layer with low concentration, 8, 9... Side wall, 11... N-type source/drain diffusion layer. Patent Applicant: Matsushita Electronics Co., Ltd. Figure 1, 11 pieces of carpet 2 Figure 1 3 die 'shirih]) evening') VJL number engraving

Claims (1)

[Claims] A first step of forming a gate insulating film in a predetermined region on a P-type semiconductor substrate or a P-type well region, and a second step of selectively removing and opening a predetermined region of the gate insulating film. a third step of forming a polysilicon layer on the gate insulating film; a fourth step of doping the polysilicon layer with an N-type impurity; and selectively removing the polysilicon layer to form a gate electrode. a sixth step of ion-implanting N-type impurities using the gate electrode as a mask; a seventh step of forming sidewalls made of an insulating material at both ends of the gate electrode; an eighth step of selectively removing the sidewalls formed in the seventh step in the opening region formed in the step of step 2; and ion implantation of N-type impurities at a high concentration using the gate electrode and the sidewalls as masks. A method for manufacturing a MOS integrated circuit, comprising a ninth step of: