JPH02109184A - Outline vector storing system - Google Patents

Abstract

PURPOSE:To express an outline vector in the number of bits without generating waste by storing each outline vector in a variable length format with expression of double bit length in unit of four bits. CONSTITUTION:The outline vectors V1-V7... are stored in the variable length format with the expression of the double bit length N, 2N, 3N... setting the four bits as unit. In the case of expressing the outline vector in two components concretely, the first and second components of the outline vector are expressed in the double bit length in unit of four bits. And corresponding four digits of the first and second components of each outline vector are coupled so that the first component is ranked at a high-order and the second component at a low-order, and are stored sequentially as information of eight bits. At the time of reading out and processing a stored outline vector, it is read out in unit of eight bits, then, the first and second components can be processed in unit of four bits in parallel enabling a processing to be performed efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field 1] The present invention relates to an outline vector storage method applied to desktop publishing systems, etc. -Relates to a storage method for outline vectors in which line vectors are stored as binary information.

[Prior Art] A so-called desktop publishing system has recently been proposed in which characters, figures, etc. can be freely printed on a CRl file and then printed out using a laser printer or the like. 1. In such a system, the fonts of usable characters or figures (hereinafter simply referred to as characters and figures) are set in advance.
43 <It is necessary to store the fin 1~ in the so-called dot method, which stores the character figure as a dot] ~ information (dot fin 1~), and the so-called dot method, which stores the outline of the character figure in multiple ways. Vector information (Ara)・Line fin 1
There is a so-called beta 1 to 1 method, in which the data is stored as (to).

When the above-mentioned vector method is adopted, for example, a plurality of vectors (1 - 1 - line vector) representing the contours of the J: una character figure indicated by the arrows in Fig. 9 are stored in memory in advance, and the character figure is When displaying on a CRT display, multiple outline vectors expressing character figures are dot-expanded (vector) into bitmap memory.
(raster conversion). If the outline of a character figure is stored in multiple outline vectors in this way, various operations such as enlarging/reducing, rotating, tilting, etc. can be easily performed on the character figure, and the resulting image can be obtained through the processing. This has the advantage that there is little deterioration of character figures.

Conventionally, when storing a plurality of 1-line vectors i representing the outline of a character figure in a memory, the X and Y components of the outline vector are stored in the memory as binary information. The number of bits of binary information representing the X and Y components is fixed to the number of bits capable of representing the most likely appearance of each component, for example, 16 bits.

[Problem to be Solved by the Invention 1] By the way, as mentioned above, in the conventional storage method of storing a plurality of outline vectors representing the outline of a character figure as binary information with a fixed bit length, it is difficult to use memory efficiently. is insufficient.

As shown in Figure 9, the outline of a character figure is generally made up of a mixture of outline vectors of different lengths, and furthermore, the outline vector components of a character figure used in this type of image processing device are compared. This is because there are many things that can be expressed with only 4 bits if the binary number table is flat. That is, the number of bits that can express the expected maximum length of the vector results in a situation where a large number of relatively small petals are expressed.

Therefore, an object of the present invention is to express the lines vectors 1 to 1 in binary information using a more efficient number of bits.

"Technical means for solving the problem" The present invention provides a plurality of outlines expressing the contours of characters and figures.
．． V6V7,...) are assumed to be stored as binary information, and the technical means for solving the above problem in this storage method are as shown in Fig. 1(a).
Each line vector (Vl, V2V5.V4.V
5. V6. V7. -), with 4-bit t(N) as the medium bit length {N, 2N, 3N.

...} There are four ways to store the expression in variable length format.

When a line vector is specifically expressed as a two-component, the first and second components of the outline vector are expressed in bit lengths that are equal multiples of 4 units, and for each outline vector, the first The corresponding four digits of the component and the second component are combined so that the first component is at the top and the second component is at the F position, and are sequentially stored as 8-digit information. In this specific configuration, when processing the five stored outline vectors, the first one is read out in units of eight.
It becomes possible to process the component and the second component in parallel into about 4 bits each, making the processing more efficient.

When storing line vectors in this type of variable length format, a length identification code is required that indicates how many bits the binary information representing the vector is expressed. The identification code represents a vector and is encoded into a portion of the J binary information. That is, the binary information and the length identification code are integrated without representing the vector information. Therefore, the length identification code part of the series of binary information is a wasted bit for expressing the solid 1 to 1. Furthermore, when looking at the contours of character shapes (for example, see Figure 9), outline vectors of different sizes do not exist randomly, but appear in a certain cluster, and in particular, small outline vectors are unique. It is something that appears continuously rather than appearing. That is, since the bit length of the data is constant for these continuous vectors, it would be wasteful to have a length identification code for each.

From this point of view, when storing line betas in a variable length format of binary information, in order to use an efficient number of bits, as shown in FIG. 1(b), The length of the binary information (V) regarding the outline vector to be stored is indicated by an identification code (D) that is separate from the binary information, and this identification code ([)
i) (Ara of bit length specified by the identification code (Di") after arranging i = 1.2, 3,...}) Binary information regarding the line vector (V il,
V i2,...} are arranged in sequence.

Ta.

[Function] When expressing the outline of a character figure using multiple outline vectors, most outline vectors are expressed using the minimum unit of 4 bits N, and outline vectors that exceed this and cause jagged edges are expressed with the corresponding size. 8 bits (2N), 12 bits (3N) depending on the multiple bit length
, 16 bits (4N>, . . . ).

At this point, generally a certain range of large jagged line vectors from 1 to 1 appear continuously, but -G identification code (1)
When i) is separated from the binary information about the vector, for the outline vector that appears continuously, after arranging the identification code (Di), progress information (Vil.

Vl2,...} are stored in sequence.

Binary information regarding the outline vector (V N.
V i2,...}, the identification -J-do (Di
) is recognized, the binary information (Vt1, Vl2,...} regarding line vectors from Ara 1 to
) shall be treated as belonging to a bit maker specified by .

shall be handled as such.

[Example] Hereinafter, practical examples of the present invention will be explained based on the drawings.

FIG. 2 is a block diagram showing an example of the basic configuration of an image processing apparatus having a vector node A-1 to which the outline vector storage method according to the present invention is applied.

In the same figure, 10 is a CP that controls the overall control.
U, 12 is a ROM that stores programs, j-pull, etc.
, 14 is an R A lvl which has areas such as image information for driver 1 to development, a map memory, etc., 16 is a vector storage area in which character and graphic fonts are stored as a set of a plurality of vectors, and 18 is a back 1 - Ruf A 1 - Full 91 - raster conversion of fonts in memory 16 URAM 14 p] - Beta 1 - raster conversion zorohi tree for font dot expansion on map memory (1-8l>) , these, CPU10, ROM1
2, RAM 14, vector fin 1 to memory 16, and back 1 to raster conversion processor 18 are connected to the bus. Further, 20 is an interface circuit, and the CRT display 13 is connected via this interface circuit 20.
, a printer 15, and an input device 17 such as a keyboard device or a scanner.

In the vector font memory 16, characters and graphics (A) and Y are stored in accordance with the storage method according to the present invention.

For example, as shown in FIG. 3, the font stored in the vector fin menu 16 is
+-11 is specified, and the character figure therein, for example, 1
1 V T1 contour A→13-→C-D-1[-su[-
A is specified as a vector (out-of-in vector). Specifically, vectors 1 to 0Δ, AB, BC.

CD, DE, EF, and FA are specified, and each fish 1 to 1 is the displacement from the origin 0 for OA, the displacement from point A for △13, and the displacement from [3 fish for B C]. It is expressed by the amount of displacement in the X and Y directions of each point (pulled to the displacement it u /ll bits of each point) as a unit, and the variable length format is expressed in multiples of the distance as shown in 1-, it is stored in vectors 1 to 16. That is, as shown in FIGS. 4(a) to 4(d), vectors]
・Depending on the size of C1, each component of the vector (X, Y
) to 4 bits (1 nibble: 1IH), 8 bits (2 nibbles: l1il, +11.), 12 bits (321 le: 1111,111..1.11), 16 bits
~(4 nibbles: HH, Ill, ill, LL)
It is expressed in.

In addition, the identification codes necessary for storing the components 1 to 7 in such a variable length format are set as shown in FIG. 5, for example. This identification code is 8
Bit-]-The F-order 4 bits of the code are fixedly determined as '1111', and the F-order 4 bits express individual identification information.Specifically, "oooi" is
This means that the direction changes. For example, as shown in Figure 3, it is necessary information about
010'' means that the Y direction changes, for example,
T5 in FIG. 3 is necessary information regarding vectors AB, BC, etc.

Indicates the length of binary data representing a vector? lIndicates 4-bit length (1 nibble) as an identification code' +
ooo''', not indicating 8 bit length (2 nibbles)'''100
1” (12 bits long, 3 nibbles) “1010”
"1oi1" indicating a 16-bit length (4 nibbles) is determined for each. Furthermore, "1iio" does not indicate the end of the outline of the character figure, but indicates the end of the character figure. ＃”1111
” are determined respectively, and these codes become necessary information regarding the vector FA shown in FIG. 3, for example.

'' The X and Y components of the vector are each expressed in units of 4 bits and in multiples of l bits long (X.

The vector is stored in the font memory 16 in 8 bits (1 by 1), similar to the identification code, as shown in FIG. This sixth
In the example shown in the figure, the vector data is arranged next to the 8-bit identification code without indicating the data bit arrangement, and the upper 4 bits of the vector data to 8 bits 1 are the X component and the lower 4 bits. is the Y component. The 4 bits of the X component and the 4 bits of the Y component correspond to each other, that is, the 1st to 4th digits, the 5th to 8th digits, the 9th to 12th digits, and the ff113th to 12th digits. The 16 digits are connected. For example, 1-8 (11
111000) is a code that means the data pimil length is 4 bits (1 nibble), and the X component XHH of the following nibble unit
and Y component YHH.
ll), and F 9 (11111001)
l- means data bit length 8 bits (2 nibbles)
Do e, the upper nibble of the following X component X1ll+, the upper nibble of the Y component Y Ill (7) set (XHII, YIE)
The lower nibble of the X component is /l/XIn, and the lower nibble Y111- of the Y component is expressed in navy blue (XIIL, Yllll,). Also, 1:△(1i11
1010> is a hood that means the data bit length is 12 bits (32 sols), and the highest nibble of the following X component is XH1l,
The top two sol Yll11 of the Y component (X old 1゜YH1
+) Upper nibble of X component XHI-1 Upper nibble of Y component (XHl,, \HL) ) group (X
LH.

Yl, 11) expresses one -C solid 1-.

Furthermore, Fi B (+1111011) means a data bit length of 16 bits 1- (4 nibbles); X1. One vector is expressed by adding the set (X + 4., Y 1.L) of the lowest nibble YLL of the L and Y components.

The vector information stored as described above is read out at the 91st position of 8 bits. When the first nibble is '1111'
”, it is recognized that the identification = 1-code, and pin 1 of the vector data that follows the information in the lower nibble of history.
~ I am specifically aware of V & length etc.

When the f-ta bit length is recognized by the identification code,
Next, data that follows is processed as vector data of the identified pin 1 length until another code is read out. <r 43 indicates the length of the data. For identification ≧1 codes other than the TIE-specific code, the attributes of the subsequent - vector information are specified. for example,
F 1 (11110001) in FIG. 6 is the X component placed after it (X IIIL X +11.
i+.

X Lm) 16 bits] and Y component (Yllll, Y
LII-, YLII.

Yl, L) 16 bits] indicates the attribute of the vector (that changes in the x direction) specified by .

The above-mentioned vectors representing the contours of the characters/figures read out from the vector fint memory 16 are subjected to processing such as enlargement, reduction, rotation, and tilt in the vector raster conversion processor 18, and then converted into dots to form the characters. Graphic information is R
It is developed in the bitmap memory area of AM14. The basic configuration of the main parts of this vector raster conversion processor 18 is shown in FIG. 7, for example.

In the figure, 100 is an X-component calculator that performs calculations on the X-component of a vector, 200 is a Y-component calculator that performs calculations on the Y-component of vectors 1 to 3, and 300 is the X-component calculator 100 and Y This is a control circuit that performs 1I11 control of the component arithmetic unit 200. The X-component arithmetic unit 100 loosely sets the input interval of vectors. 1i'? L buffer 10
2, and a basic arithmetic unit 10 that performs basic operations such as addition and subtraction.
4,108,112°116 and each! Latches 106, 110, 11 that temporarily store calculation results between J calculation units
4,118, and the Y component arithmetic unit 200 similarly includes a buffer 202, a basic arithmetic unit 204 . ．． 208,212゜2
16, latches 206, 210, 214, and 218. The X-component arithmetic unit 100 and the Y-component arithmetic unit 200, in which these basic arithmetic units are arranged in series, are vibe-line arithmetic units in which the processing in each basic arithmetic unit is a basic arithmetic step. The control circuit 300 also includes the X and Y component calculator 10.
0,200 buffer, basic arithmetic unit, Bano 7302 that supports latches, arithmetic sacred treasures 304, 308, 312
316 and latches 306, 310, and 314, and similarly constitutes a vibe line arithmetic unit whose basic arithmetic step is processing by an arithmetic controller.

Here, the pipeline operation is a process of performing arithmetic processing on a vector of - at each basic arithmetic step, and is an arithmetic lj formula in which the next vector information is sequentially performed for the basic arithmetic step that has been processed, and is This realizes simultaneous processing of multiple vectors by time division.

Note that the X and Y component calculation units 100 and 200 have a path from the latch 110 (114,) on the X component calculation unit 100 side to the Y component calculation unit 200111 (11 calculations Ia 212 (216), and a corresponding latch on the Y side. 210 (214) to the herbaceous arithmetic unit 112 (116) on the X side, there is also a path for supplying the performance frame results in each component arithmetic unit to the other arithmetic unit.

J: Sea urchin vector anl-memory 16 to 8 as mentioned above
The vector information read out in bits is processed in the vector raster conversion processor 18 by adding attribute information (tags are added to the vector, indicating the attributes of the vector, such as the positive/negative of the solid color, the starting point of the character/figure, etc.). 1 to 1
Top 4 hits of 8-bit data (XHII, XIIL
, 1-11.8. l-111) is the X component extractor 10
0, the same lower 4 bits (Y old 1. Y) IL, YLI
I.

YLl,) is also added to the Y component calculator 200]
~Repeat information is supplied to the control circuit 300 in parallel as input data.

A more specific configuration of the X and Y component calculators 100 and 200 is partially shown in FIG. 8, for example. This example specifically shows one enlargement/reduction processing block, and in reality, the
0 and 200, for example, in the first stage. In addition,
For convenience, the explanation will be made assuming that the X component arithmetic unit 100 is used.

This enlargement/reduction processing block includes a latch 31, a shifter 3
2. The front part of the adder 33, the latch 34, and the adder 35
, shifter 36, and latch 37. A magnification (for example, 16 bits) is set in the latch 31 at the front stage, and according to the setting magnification, the lower 2 bits and 1-digit 2 bits of the 4-bit input data (X111+, Xl) L, etc.) from the buffer 102 are set. Two corresponding outputs a and b are produced. Output a of each system,
b is in relation to the input bits, and follows, for example. Jitter 32 is a two-way shifter,
The a output of the latch 31 and the b output via the shifter 32 are added by an adder 33. The latch 31, shifter 32, and adder 33 constitute a multiplier that can multiply input data by a set magnification. For example, if the setting magnification is "2x" (,-ooio) T"
') When the
``6'' (...0110) (lower 2 bits are 1)
1). Then, the data obtained by shifting the b output by 2 bits from 1 to (
-, 011000) and the above a output (・0010) are added, and the result is (...011010 = 26),
That is, the multiplication result "26" of the input data "13" and the magnification II 211 is stored in the latch 34.

When the bit length of vector data is 4 bits or more, processing is performed sequentially starting from the more significant 4 bits XIIH. Therefore, in the latter part of the enlargement/reduction processing block, if the data of the vector component is 4 bits or more, for example, 8 bits, the above multiplication result for the upper 4 bits XHH is shifted by 4 bits ( Shifter 36) Adds the multiplication result for the next 4 bits x 11F to give the overall multiplication result, and in the case of 12 bits or 16 bits, adds the addition result and the next 4 bits x 1. H,X
The multiplication results for L1 and Ll are sequentially added to obtain the overall multiplication result. As a result, multiplication of vector components of 4 bits or more (cases shown in FIGS. 4(b), 4(c), and d) is realized.

Note that when the reduction processing is performed in this enlargement/reduction processing block, the register 31 is set to a magnification m that is a condition of O<magnification m<1.

In the above-mentioned enlargement/reduction processing block, the first stage part including the adder 33 and the second stage part including the adder 35 constitute basic calculation steps, and when the 4-bit data processing in the first part is completed, the 4-bit data is transferred to the second part. Shifting to the processing of the part, processing of the next 4-bit data is started in the former part, and processing in the curved part and the latter part proceeds simultaneously (pipeline calculation).

The vector rask conversion process 1-18 processes the vector representing the font by enlarging/reducing each component (X, Y) in 4-bit units, as well as processing rotation, tilting, etc., and interpolation processing. The fin 1- is developed on the bitmap memory by converting the dots 1 to 1 and calculating the address of .apprxeq. on the bitmap memory for each dot (vector rask transformation). These enlargement, reduction, rotation, tilt, interpolation processes, etc. are efficiently processed by the pipe-in performance frame using the above-mentioned basic arithmetic unit as a unit. Each calculation controller in the control circuit 300 controls the calculation mode of the corresponding basic calculation unit, such as addition and subtraction, based on the information (tag data).

According to this embodiment, as described in 1), the font can be expressed as -
Express the X and Y components of [vector] to the same multiple bit length in units of 1 bit, and for each vector, the corresponding 4 digits of the X and Y components are expressed as the upper X component and the lower Y component. Since the 8-bit data is combined and stored sequentially in the solid 1 to font memory 16, it is possible to read and process it in 8-bit units, and the software that can be used in J3 such as cPtJ etc. This allows for better consistency of data and more efficient processing. In particular, since the corresponding 4 digits of the X and Y components are combined to create 8 bits of data, the data read from the camera (8 bits ~) can simply be converted to the top 4 bits.
Parallel processing of the X component and the Y component can be easily put to practical use by only dividing iJ into the lower 4 bits. Furthermore, since each vector component is processed using a 4-bit single Q, simple calculation steps such as addition, subtraction, shift, etc. Conversion processing becomes possible.

Furthermore, since the identification code is made separate from the vector component data, no bits of binary data are wasted because they do not represent the vector component data. Furthermore, since the upper 4 bits of the identification code are set to '1111', the maximum value of the vector component data that is expressed in distinction from the identification code becomes larger.

Note that the present invention can of course be applied to the aspect of the outline vector representing the font (character/figure) other than the one expressed by the displacement amount of points as described above. For example, the present invention can be similarly applied to specifying a vector using coordinate data itself, or specifying a vector based on magnitude and direction.

In addition, the identification code indicating the bit length of information regarding the outline vector is
The invention of separating 4-bit information from 4-bit information is not limited to storing multiples of 4-bit information in variable-length formats with good representation; This method can also be applied to cases in which vectors are expected to be continuous to some extent, and the vectors are stored in an arbitrary variable-length film 1-. Furthermore, the specific identification code is not limited to that in the first embodiment.

In the above embodiment, the vector fin data stored in advance in the memory 16 was stored according to the storage method according to the present invention, but the present invention is not limited to such an embodiment. For example, Mr. M may develop characters and figures read by an image scanner into dots on the RAM 14, convert the dot information into vector information, and store it in a specific area of the RAM 14 according to the storage method according to the present invention. .

``Advantageous Effects of the Invention 1 and Beyond'' As explained above, according to the present invention, an outline vector representing the contour of a character figure in which relatively small vectors appear continuously can be generated in units of 4 bits. Since it is stored in a variable length format with a bit length that is a multiple of the bit length, when expressing the line vectors in binary information, it becomes possible to express them with a more efficient number of bits. Also, when storing in variable length format, the bit length of the outline vector]
Since the identification code is separate from the binary information related to the outline vector, no bits are wasted and the dynamic range is wider. .

In this way, according to the present invention, it becomes possible to express the line vectors 1 to 1 with a more efficient number of bits, so that the data can be compressed when stored, and memory can be used more efficiently. It becomes possible.

[Brief explanation of drawings]

FIG. 1 (a>(b) shows the configuration of the present invention; FIG. 2 shows an example of an image processing device having a vector font memory to which the storage method according to the present invention is applied) Figure 3 is a diagram showing an example of a character/figure character figure represented by a vector, Figure 4 is a diagram showing an example of the type of data length of a vector, and Figure 5 is an example of an identification code. , Figure 6 is a diagram showing the storage state of the vector f - , Figure 7 is a block diagram showing an example of the basic configuration of the main parts of the vector (/raster transformation processor), and Figure 8 is the X component calculation. FIG. 9 is a block diagram partially showing an example of the detailed configuration of the device, and FIG. 9 is a diagram showing an example of the state of the outline vector.D1 to D3...Identification code Patent applicant Agent of Lus Isis Dems Co., Ltd.
Patent attorney Tomohiro Nakatoshi (3 others) [Code explanation 1 10...C1) U 12...ROM 14...RAM 16...Betta 1 Helf Ant memory 18...Vector rask Conversion processor 100...
X component calculator 200...Y component calculator 300...III control circuits v1 to v7...Outline vector 7 (b) DI-D3 Identification code V: Binary information Roff correct] []1= =ko■32

Claims (5)

[Claims] (1) Multiple outline vectors expressing the outline of character figures {V1, V2, V3, V4, V5, V6, V7,
...} as binary information, and each outline vector {V1, V2, V3, V4, V
5. V6, V7, ...} is stored in a variable length format expressed in multiple bit lengths {N, 2N, 3N, ...} in units of 4 bits (N). . (2) In the outline vector storage method according to claim 1, the first and second components of the outline vector, which is a two-component representation, are expressed in the same multiple bit length in units of 4 bits, and for each outline vector, , an outline vector storage method characterized in that four corresponding digits of a first component and a second component are combined so that the first component is in the upper order and the second component is in the lower order, and sequentially stored as 8-bit information. (3) An outline vector storage method that stores a plurality of outline vectors representing the outline of a character figure in a variable length format of binary information, in which binary information (V
) is the identification code (D) indicating the bit length of the binary information (
V), and after arranging this identification code (Di) (i = 1, 2, 3, ...), the binary information ( Vi1, V
i2,...) is sequentially arranged. (4) The outline vector storage method according to claim 3, wherein binary information regarding each outline vector is stored in a variable length format expressed in multiple bit lengths in units of 4 bits. method. (5) In the outline vector storage method according to claim 4, the first and second components of the outline vector, which is a two-component representation, are expressed in the same multiple bit length in units of 4 bits, and for each outline vector, , an outline vector storage method characterized in that four corresponding digits of a first component and a second component are combined so that the first component is in the upper order and the second component is in the lower order, and sequentially stored as 8-bit information.