JPH0210757A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH0210757A JPH0210757A JP63161811A JP16181188A JPH0210757A JP H0210757 A JPH0210757 A JP H0210757A JP 63161811 A JP63161811 A JP 63161811A JP 16181188 A JP16181188 A JP 16181188A JP H0210757 A JPH0210757 A JP H0210757A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- semiconductor chip
- metal
- thermal stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000000853 adhesive Substances 0.000 abstract description 12
- 230000001070 adhesive effect Effects 0.000 abstract description 12
- 230000008646 thermal stress Effects 0.000 abstract description 10
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 238000000926 separation method Methods 0.000 abstract 2
- 229910001374 Invar Inorganic materials 0.000 abstract 1
- 238000005336 cracking Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000007767 bonding agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は印刷配線板に半導体部品を実装する構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a structure for mounting semiconductor components on a printed wiring board.
第３図は、従来の印刷配線板の実装構造を示す断面図で
、図において、（１）は半導体チップ、（２）は印刷配
線板、（３）は半導体チップ（１）と印刷配線板（２）
との間を電気接続するワイヤボンド部分、（４）は半導
体チップ（１）を印刷配線板（２）にダイボンドする接
着剤である。FIG. 3 is a cross-sectional view showing the mounting structure of a conventional printed wiring board. In the figure, (1) is a semiconductor chip, (2) is a printed wiring board, and (3) is a semiconductor chip (1) and a printed wiring board. (2)
The wire bonding portion (4) for electrically connecting the semiconductor chip (1) to the printed wiring board (2) is an adhesive.
次に動作について説明する。Next, the operation will be explained.
半導体チップ（１）は高密度実装を実現するためパッケ
ージに入れず直接半導体チップ（１）全印刷配線板（２
月こ実装する。In order to realize high-density packaging, the semiconductor chip (1) is directly mounted on the entire printed wiring board (2) without being placed in a package.
Implemented this month.
半導体チップ（１）の電極から印刷配線板（２）の導体
部に、例えば２５μｍ径の金線などでワイヤーボンドす
る。半導体チップ（１）を印刷配線板（２）に接着剤（
４）によりダイボンドする。半導体チップ（１）は通常
Ｓｉであり４ Ｘ １０−’℃−１の線膨張係数を有し
ており、印刷配線板（２］は２０ Ｘ １０−’（３’
の線膨張係数を有する。この線膨張係数差により生じる
熱応力を吸収できる接着剤（４）を用いる。Wire bonding is performed from the electrodes of the semiconductor chip (1) to the conductor portion of the printed wiring board (2) using, for example, a gold wire with a diameter of 25 μm. Place the semiconductor chip (1) on the printed wiring board (2) with adhesive (
4) Die-bond. The semiconductor chip (1) is usually Si and has a coefficient of linear expansion of 4 x 10-'°C-1, and the printed wiring board (2) has a coefficient of linear expansion of 20 x 10-'(3'
It has a linear expansion coefficient of An adhesive (4) that can absorb the thermal stress caused by this difference in coefficient of linear expansion is used.
従来の印刷配線板の実装構造では半導体チップの大きさ
が１辺５間より大きくなると、熱応力による半導体チッ
プの割れや剥離、ダイボンド剤でのクラック、剥離など
が生じるなどの問題点がめった。In the conventional printed wiring board mounting structure, when the size of the semiconductor chip becomes larger than 5 squares on a side, problems such as cracking or peeling of the semiconductor chip due to thermal stress, cracking or peeling due to die bonding agent, etc. occur.
この発明は上記のような問題点を解消するためになされ
たもので、１辺５１１１以上の半導体チップを実装し熱
応力による割れ等の生じない昼信頼度の印刷配線板の実
装構造を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to obtain a mounting structure for a printed wiring board that mounts semiconductor chips of 5111 or more on a side and has daytime reliability without cracking due to thermal stress. With the goal.
この発明に係る印刷配線板の実装構造は半導体チップを
実装する印刷配線板の部分に所要の線膨張係数を有す金
属を設け、その上に半導体チップをダイボンドしたもの
である。The printed wiring board mounting structure according to the present invention is such that a metal having a required linear expansion coefficient is provided on the portion of the printed wiring board on which the semiconductor chip is mounted, and the semiconductor chip is die-bonded thereon.
この発明における印刷配線板の金属は半導体チップと印
刷配線板との間に介在することにより半導体チップに生
じる熱応力を抑えることができる。The metal of the printed wiring board in this invention is interposed between the semiconductor chip and the printed wiring board, so that thermal stress generated in the semiconductor chip can be suppressed.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図において、（１）は半導体チップ、（２）は半導
体チップ（１）を実装する印刷配線板、（３）は半導体
チｆノ＋１１と印刷配線板（２）との間を電気接続する
ワイヤボンド部分、（５０よ所要の線膨張係数を有する
金属である。（６）は半導体チップ（１）を金属（５）
にダイボンドするための接着剤、（４）は金属（５）を
印刷配線板（２）に取付は固定するための接着剤である
。In Figure 1, (1) is a semiconductor chip, (2) is a printed wiring board on which the semiconductor chip (1) is mounted, and (3) is an electrical connection between the semiconductor chip (11) and the printed wiring board (2). The wire bond part (50) is a metal having the required coefficient of linear expansion. (6) is a metal (5) that connects the semiconductor chip (1).
(4) is an adhesive for attaching and fixing the metal (5) to the printed wiring board (2).
半導体チップ（１）は通常２龍Ｘ２Ｓ１１から１ｏｕＸ
ＩＯ龍の寸法であり、これをパッケージに入れ実装して
いた。ところが、高密度実装の要求からパッケージを小
さくするか、図のように半導体チップのままで印刷配線
板（２）に実装するようになってきている。印刷配線板
（２）に、２〜ｌ０ＸＩＯ−’℃−１程度の線膨張係数
を有する、インパールアロイ４２、コバールなどの金属
（５）を接着剤（４）などで取付ける。Semiconductor chip (1) is usually 2RYX2S11 to 1OUX
These are the dimensions of the IO dragon, and they were packaged and implemented. However, due to the demand for high-density packaging, packages are being made smaller, or semiconductor chips are being mounted on printed wiring boards (2) as shown in the figure. A metal (5) such as Imphal Alloy 42 or Kovar having a coefficient of linear expansion of about 2 to 10XIO-'°C-1 is attached to the printed wiring board (2) using an adhesive (4) or the like.
つき゛に、半導体チップ（１）を金属（５）に接着剤な
ど（６）でダイボンドする。このように半導体チップ（
１）の線膨張係数が４ｘ１０ ”（３ｓであり、この値
に金属（５）の線膨張係数を近づけることにより、半導
体チップ（１）にがかる熱応力を抑えることができる。At the same time, the semiconductor chip (1) is die-bonded to the metal (5) using an adhesive or the like (6). In this way, semiconductor chips (
The linear expansion coefficient of 1) is 4×10 ″ (3s), and by bringing the linear expansion coefficient of the metal (5) close to this value, the thermal stress applied to the semiconductor chip (1) can be suppressed.
金属（５）と印刷配線板（２）との間に熱応力は生じる
が金属（５）は機械的に安定しており、接着剤（４）に
よりゐ、６程度応力が吸収されるので各部位において剥
；碓やクラックなどの障害は生じない。Although thermal stress occurs between the metal (5) and the printed wiring board (2), the metal (5) is mechanically stable and the adhesive (4) absorbs about 60% of the stress, so each No defects such as peeling or cracks occur at the site.
なお、１肥実施例では印刷配線板（２）を特殊な加工を
しない、構造とした場合を示したが、第２図に示すよう
な堀り込み；Ｊ造にすることもできる。In addition, although the printed wiring board (2) has a structure without any special processing in the 1-fer embodiment, it can also be made into a J-shaped construction as shown in FIG.
このように印刷配線板（２）に堀り込み部（７）を設け
た場合には、全体高さを第１図の実施例よりも低くする
ことができ、接着剤（４）の選定において、堀り込み部
（７）に接着剤が入れ易く、粘度の低い材料を使うこと
も可能となる。When the printed wiring board (2) is provided with the recessed portion (7) in this way, the overall height can be made lower than in the embodiment shown in FIG. It is easy to put the adhesive into the digging part (7), and it is also possible to use a material with low viscosity.
以上のようにこの発明によれば、半導体チップにかかる
熱応力を抑えるように構成したので、ＬＳＩなどの半導
体チップを高信頼性で高密度実装ができる効果がある。As described above, according to the present invention, since the structure is configured to suppress thermal stress applied to the semiconductor chip, there is an effect that semiconductor chips such as LSI can be mounted with high reliability and high density.
第１図はこの発明の一実施例による印刷配線板の構造断
面図、第２図はこの発明の他の実施例を示す印刷配線板
の構造断面図、第３図は従来の印刷配線板の構造断面図
である。
図において、（１）は半導体チップ、（２）は印刷配線
板、（３）はワイヤボンド部、（４）は接着剤、（５）
は金属、（６）は接着剤、（７）は堀り込み部を示す。
なお、図中、同一符号は同一、または相当部分を示す。
第１図
乙、撞着別
第２図
第３図FIG. 1 is a structural sectional view of a printed wiring board according to an embodiment of the present invention, FIG. 2 is a structural sectional view of a printed wiring board showing another embodiment of the invention, and FIG. 3 is a structural sectional view of a conventional printed wiring board. FIG. In the figure, (1) is a semiconductor chip, (2) is a printed wiring board, (3) is a wire bond part, (4) is an adhesive, and (5) is a printed wiring board.
(6) is the adhesive, (7) is the digging part. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1: B, discrepancies: Figure 2: Figure 3
Claims (1)
機械的特性を有する金属を設けたことを特徴とする印刷
配線板。A printed wiring board characterized in that a metal having required mechanical properties is provided in a semiconductor mounting portion of the printed wiring board on which a semiconductor is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63161811A JPH0210757A (en) | 1988-06-28 | 1988-06-28 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63161811A JPH0210757A (en) | 1988-06-28 | 1988-06-28 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0210757A true JPH0210757A (en) | 1990-01-16 |
Family
ID=15742362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63161811A Pending JPH0210757A (en) | 1988-06-28 | 1988-06-28 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0210757A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0546069U (en) * | 1991-11-21 | 1993-06-18 | 日本無線株式会社 | High-density mounting circuit board |
| US6320267B1 (en) * | 1998-08-10 | 2001-11-20 | Sony Corporation | Bonding layer in a semiconductor device |
-
1988
- 1988-06-28 JP JP63161811A patent/JPH0210757A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0546069U (en) * | 1991-11-21 | 1993-06-18 | 日本無線株式会社 | High-density mounting circuit board |
| US6320267B1 (en) * | 1998-08-10 | 2001-11-20 | Sony Corporation | Bonding layer in a semiconductor device |
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