JPH02103935A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an inorganic insulating film which is stable and high in reliability by treating it with plasma in gas atmosphere which reacts on the relatively heavy constituent element of an inorganic insulating film being formed on a semiconductor substrate and contains a relatively light constituent element. CONSTITUTION:After accumulating an Al-Si-Cu film on a semiconductor substrate 71 whereon a heat silicon oxide film is formed, wiring 72 at the first layer having a specific pattern is formed. By a plasma CVD method, a P-SiO film 73 is accumulated, and after applying positive photoresist 74, the P-SiO film 73 on the wiring 72 is etched back. After surface cleaning, a P-SiO film 75 is accumulated by plasma CVD conditions, and it is drawn up to ultimate vacuum of a plasma device, and plasma treatments by N2O are done continuously. This way, silicon surplus layer 76 existing at the surface layer of a P-SiO film 75 can be modified into a P-SiO film 76'. Next, wiring 78 at the second layer is formed and two-layer wiring structure is completed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a technology for forming an inorganic insulating film layer used as an interlayer insulating film of multilayer wiring. It is.

(Prior Art) A conventional example of a method for forming an interlayer insulating film layer of a plasma silicon oxide film in a two-layer wiring will be briefly described with reference to FIG.

As shown in FIG. 5(a), the arrangement of the first layer made of Al-3i-Cu having a predetermined pattern and having a thickness of 1.0 μm is provided on a semiconductor substrate 11 on which a thermal silicon oxide film is formed. 9!A plasma silicon oxide film (hereinafter referred to as P-SiO film) 13 is formed on 12 by plasma CVD method.
After depositing 1.5 μm of p-5to film 13 and coating a positive photoresist 14 with a thickness of 2.0 μm, an RI is applied so that the etching rate of the p-5to film 13 and the positive photoresist 14 are the same.
Under E condition, the P-SiO film 13 on the first layer wiring 12
Etch back to 0.2um.

After surface cleaning, as shown in FIG. 5(b), a 1.0 μm thick P-S i O film 15 is redeposited to form a flat interlayer insulating film layer, and then normal photolithography and RIE are performed. A through hole 17 is formed at a predetermined position. After this, a 1.0 μm thick /I film having a predetermined pattern is formed by ordinary sputtering, photolithography and RIE.
I? A second layer wiring 18 made of -8i-Cu is formed.

Next, as shown in FIG. 5(e), a top passivation film 19 is formed using the plasma CVD method described above.
After depositing a P-SiO film with a thickness of 0 μm, predetermined bonding and
A pad opening is formed to complete the two-layer wiring structure.

(Problem to be Solved by the Invention) Generally, in order to improve the reliability of semiconductor devices, P-Si is used as an interlayer insulating film or a top passivation film for multilayer wiring.
An inorganic insulating film such as O@ is used. However, the conventional inorganic insulating layer forming technology has the following problems.

Plasma CVD method (film formation conditions: Si
H4/N 20-200/24008 CCM
In the P-SiO film formed by the P-SiO film formed by the P-SiO film using the P-SiO film using the P-SiO film formed by the P-SiO film using the P-SiO film produced by the P-SiO film using the P-SiO film using the P-SiO film formed using the P-SiO film using the P-SiO film produced by the P-SiO film using the P-SiO film produced using the P-SiO film using the P-SiO film using the P-SiO film, there exists a silicon excess layer 16 up to a depth of about 0.2 μm from the film surface. This can be seen from the child analysis.

An example is shown in FIG. 7, and the film formation conditions and formation method (
Blaz 7CVD, reduced pressure CVD, normal pressure CVD.

Although the thickness of the silicon-excess layer 16 varies depending on the sputtering method, ECR plasma CVD method) and equipment, it has been found that in most cases, the thickness is in the range of 5 to 35% of the formed film thickness. Furthermore, in the case of silicon nitride films and silicon carbide films other than silicon oxide films, the thickness is within the same range.
It was also confirmed that the silicon-excess layer was formed.

The silicon excess layer 16 is thought to be formed when atoms with light mass (e.g., oxygen atoms in the case of P-5iO) escape from the film surface when the formation reaction is abruptly stopped to control the film thickness. There are many incomplete or weak bonds between atoms in the silicon-excess layer 16. For this reason, the electrical characteristics in particular become extremely unstable, and the conventional example has the following problems.

■The level of leakage between wirings on the insulating film is extremely high. For example, as shown in Figure 3, the leakage between the second layer interconnects on the P-SiO interlayer insulating film is approximately 203 pA/ca at an interconnect spacing of 1.5 umS and an electric field of 0.5 MV/am. Wiring leakage when formed on a film (0,52p
This is approximately 390 times that of A/am).

■Interfacial charge density N due to MIS structure as shown in Figure 4
The level of variation ΔNss in interfacial charge density due to ss and BT processing is high. For example, in the case of a conventional P-SiO film,
As high as N s s -2, OX 10"am-2, BT
The fluctuation amount ΔNss after the treatment (I M V / am -300°C - 20 minutes) is ΔNss when the gate electrode is anode (+BT).
Although it shows normal behavior as a positive ion movable type with N s s ”i +1.2
T) at time ΔN s s '= + 7.581011
010a and the positive ion mobile type exhibit different behavior, and N
Stability and reliability of ss fluctuation and vth deteriorate. In FIG. 4, a gate oxide film 6 is formed on an n-type silicon substrate 61.
2. P-8iO film 63, gate electrode (1.0 μm AN)
64 are sequentially stacked.

The present invention was made in view of the above circumstances, and after forming an inorganic insulating film by a conventional method such as plasma CVD method,
The surface layer where light constituent atoms diffuse outward and heavy constituent atoms become excessive, such as an excess silicon layer formed from the surface of the inorganic insulating film to a thickness of about 5 to 35% of the formed film thickness, is treated with plasma. To provide a method for manufacturing a semiconductor device that can improve the film quality of the surface layer by replenishing light constituent atoms diffused to the outside by oxidation, etc., and form an electrically stable and highly reliable inorganic insulating film. purpose.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a method for forming an inorganic insulating film as an interlayer insulating film or a passivation film on a semiconductor substrate having a predetermined structure and pattern. After forming an inorganic insulating film by a CVD method or the like, at least a part of the light constituent atoms diffuse to the outside at the end of the inorganic insulating film forming reaction, and the film quality of the surface layer of the inorganic insulating film is improved, where heavy constituent atoms become excessive. For this purpose, plasma treatment is performed in an atmosphere containing at least one kind of lighter atoms, such as oxygen, nitrogen, and carbon, which reacts with the heavy constituent atoms and is necessary to form a stable insulating film. This is an inorganic insulating film formation technology that replenishes the light constituent atoms lost in the plasma treatment and modifies the excess layer of heavy constituent atoms to create a more reliable inorganic insulating film with stable electrical properties. can be easily realized.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIGS. 1(a), (b), (c), and (d) show an embodiment of the present invention. That is, as shown in FIG. 1(a), 1. ．． 0μm thick AN-Si-C
After depositing the u film, conventional photolithography method and RI
First layer wiring 72 having a predetermined pattern by E method
was formed. Plasma CVD method (SI Ha/N
x O-200/ 2400 S CCM-0,4T
1.5. c.
After depositing a P-3iO film 73 with a thickness of zm and coating a positive photoresist 74 with a thickness of 2.0 μm, RIE method (CH
F 3 / C2F 6/ 0□/He=10/35/
The P-SiO film 73 and the positive photoresist 74 are etched at the same etching speed using a 20/35 SCCM-3,0 Torr-550W).
-5iO film 73 is etched until the film thickness becomes 0.2 μm.
Backed up.

After surface cleaning by plasma ashing method and rinsing with running water, as shown in Figure 1(b), P-8 with a thickness of 0 μm was
An iO film 75 is deposited under the same plasma CVD conditions as described above,
Pull down to the ultimate vacuum level of the plasma CVD equipment and continuously apply N.
Plasma treatment with 20 (N 20 = 2800 S
CCM-Q, 4Torr-1,2KW-300
°C) was performed.

As a result of the plasma treatment, a silicon excess layer 76 exists on the surface layer of the P-3iO film 75 after deposition with a thickness of 0.20 μm, which corresponds to 20% of the deposited film thickness (confirmed by Auger electron analysis as shown in FIG. 2). was modified into a P-3iO film. 76' is a portion with improved film quality.

Next, as shown in FIG. 1(C), a through hole 77 is formed at a predetermined position by normal photolithography and RIE.
After forming, a 1.0 μm film with a predetermined pattern is formed using the usual sputtering method, photolithography method, and RIE method.
A second layer wiring 78 made of thick Al1-3L-Cu was formed.

Next, as shown in FIG. 1(d), a top passivation film 79 is formed under the plasma CVD conditions described above.
, Oμrn thick P-8iO@ was deposited, and after the plasma treatment, predetermined bonding pad openings were formed by normal photolithography and RIE to complete the two-layer wiring structure according to the present invention. .

In the above embodiments, an interlayer insulating film of multilayer wiring is used as an example, but any inorganic insulating film formed on a semiconductor substrate, such as a passivation film, may be applied at any stage.

In addition, in the above embodiment, plasma CVD is used as the inorganic insulating film.
The P-3iO film was formed using a plasma C method.
Any physical growth method such as low pressure CVD method other than VD method, chemical vapor deposition method such as atmospheric pressure CVD method or ECR plasma CVD method, or sputtering method is sufficient, and the types of films formed include silicon oxide film, silicon nitride film, It goes without saying that any inorganic insulating film made of a silicon compound, such as a silicon charcoal film, or an inorganic insulating film made of a material other than silicon compounds that can be applied to semiconductor devices may be used.

Furthermore, in the case of a silicon compound such as the P-3iO film used in the above example, an excess silicon layer is formed on the surface layer of the film, but in other materials as well, a heavy structure is formed due to the external diffusion of light constituent atoms as described above. Needless to say, an excess layer of atoms is formed.

In addition, in this example, in order to modify the silicon-excess layer formed on the surface of the P-SiO film, N20 plasma treatment is performed to make the silicon-excess layer almost a normal P-SiO film, but the light constituent atoms Plasma treatment aims to improve the excess layer of heavy constituent atoms due to external diffusion into a stable insulating film. Any gas atmosphere containing at least one type of lighter atom of the same or different type as the element is sufficient, and if the excess layer of heavy constituent atoms is a modified insulating film with stable film quality, the excess layer of heavy atoms may be removed. The quality of the film formed below may be the same or different. In other words, taking a P-3iO film as an example, due to the film quality reform of the silicon-excess layer on the surface layer, 02, N2, No.
NO2, Co.

Reacts with Si atoms such as CO□, CH4, C2H8,
0. Perform plasma treatment using at least one type of gas that supplies NSC atoms, and the modified film quality will be P-8.
Any material other than iO, such as P SiN 5P-3iC or a stable intermediate insulating material thereof, may be used.

Furthermore, the plasma treatment conditions for improving the film quality of the excess layer of heavy atoms may be such that an insulating film can be stably formed, and it is not necessarily necessary to perform the plasma treatment continuously with the formation of an inorganic insulating film.

Note that the terms "heavy" and "light" refer to relative differences in atomic weight.

[Effects of the Invention] As described above, the present invention has the advantage that light constituent atoms existing in the surface layer of an inorganic insulating film formed by chemical vapor deposition methods such as plasma CVD methods or physical growth methods such as sputtering methods are diffused to the outside. The unstable layer in which heavy constituent atoms become excessive is subjected to plasma treatment in a gas atmosphere containing at least one type of relatively light atom necessary for reacting with the heavy constituent atoms and forming a stable insulating film. This method is characterized by replenishing at least one of the same kind or different kind of relatively light atoms as the light atoms lost to excessive heavy atoms to form a stable insulating film layer, and has the following effects.

■Leak level on the surface of the inorganic insulating film is extremely low. The leakage between the second layer interconnects on the P-SiO interlayer insulating film in the example was measured under the same measurement conditions as before (interconnect spacing 1.5 μm,
At an applied electric field of 0, 5 MV/ell), 0.
8-1. OpA/cm and about 1/203 to 1.
/254, which is at an extremely low level (see Figure 3).

■Interfacial charge density N5s- due to the MIS structure shown in Figure 4
1, lXl0 mouth (to) -2, which is about 1/2 of the conventional example,
The fluctuation amount ΔNss after BT treatment (I M V / cs -300℃-20 minutes) is ΔNs s' when the gate electrode is anode (+BT); +6.5X10"co+-" when the gate electrode is cathode (-BT) ΔNs sm+0.52X10”
am-” (almost no increase), showing normal positive ion mobile type behavior, and Nss.

The 8Nss levels were both low, indicating improved stability and reliability.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the formation process of an embodiment of the present invention, FIG. 2 is a characteristic diagram showing an example of the results of Auger electron analysis showing the effect of improving the film quality of an excess silicon layer according to the present invention, and FIG. Leakage between wiring on inorganic insulating film according to invention and conventional technology a11
A characteristic diagram showing an example of the constant results, Figure 4 is M! A cross-sectional view showing an example of an S-structure semiconductor device, FIG. 5 is a cross-sectional view showing a conventional inorganic insulating film formation process, and FIG. 6 is an Auger electron analysis showing the presence of an excess silicon layer on the surface of a conventional P-SiO film. FIG. 7 is a characteristic diagram showing an example of the dependence of a conventional silicon-excess layer on plasma CVD conditions. 71... Semiconductor substrate, 72... First layer wiring, 7
3...P-SiOM, 74...Positive photoresist, 75...P-3iO film, 76...Silicon excess layer. 77... Through hole, 78... Second layer wiring,
79...Top passivation film. Applicant's agent Patent attorney Takehiko Suzue 79:)-/AtV Shibeshi 1 Blade's bulges 11 BishiS 艮zaωm1 Figure 2 Figure 4

Claims (4)

[Claims] (1) In a method for manufacturing a semiconductor device in which an inorganic insulating film is formed on a semiconductor substrate, there is a step of forming an inorganic insulating film on a semiconductor substrate, and a relatively heavy constituent element of the inorganic insulating film formed by this step. 1. A method of manufacturing a semiconductor device, comprising the step of performing plasma treatment in a gas atmosphere containing at least one relatively light constituent element necessary for forming a reactive and stable insulating film. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming an inorganic insulating film and the step of performing plasma treatment are performed continuously without exposing the semiconductor substrate to the atmosphere. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the heavy constituent element includes at least Si. (4) The method for manufacturing a semiconductor device according to claim 1, wherein the relatively light constituent element includes at least one of O, N, and C.