JPH0691082B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JPH0691082B2
JPH0691082B2 JP63257682A JP25768288A JPH0691082B2 JP H0691082 B2 JPH0691082 B2 JP H0691082B2 JP 63257682 A JP63257682 A JP 63257682A JP 25768288 A JP25768288 A JP 25768288A JP H0691082 B2 JPH0691082 B2 JP H0691082B2
Authority
JP
Japan
Prior art keywords
film
insulating film
layer
inorganic insulating
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63257682A
Other languages
Japanese (ja)
Other versions
JPH02103935A (en
Inventor
康一 間瀬
正泰 安部
敏彦 桂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63257682A priority Critical patent/JPH0691082B2/en
Publication of JPH02103935A publication Critical patent/JPH02103935A/en
Publication of JPH0691082B2 publication Critical patent/JPH0691082B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置の製造方法に係り、特に多層配線
の層間絶縁膜に使用される無機絶縁膜層形成技術に関す
るものである。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for forming an inorganic insulating film layer used for an interlayer insulating film of a multilayer wiring. Is.

(従来の技術) 第5図を用いて、二層配線におけるプラズマ・シリコン
酸化膜の層間絶縁膜層の形成法の従来例を簡単に示す。
第5図(a)に示すように、熱シリコン酸化膜が形成さ
れた半導体基板11に設けられた、所定のパターンを有す
る1.0μm厚のAl-Si-Cuから成る第1層目の配線12上
に、プラズマCVD法によりプラズマ・シリコン酸化膜
(以下、P-SiO膜と称する)13を1.5μm堆積し、2.0μ
m厚のポジ型フォトレジスト14を塗布した後、該P-SiO
膜13と該ポジ型フォトレジスト14のエッチング速度が同
一となるRIE条件で、該第1層目の配線12上のP-SiO膜13
を0.2μmまでエッチ・バックする。
(Prior Art) A conventional example of a method for forming an interlayer insulating film layer of a plasma silicon oxide film in a two-layer wiring will be briefly described with reference to FIG.
As shown in FIG. 5A, the first-layer wiring 12 made of Al-Si-Cu having a predetermined pattern and having a predetermined pattern, which is provided on the semiconductor substrate 11 on which the thermal silicon oxide film is formed. A plasma silicon oxide film (hereinafter referred to as a P-SiO film) 13 is deposited to a thickness of 1.5 μm by a plasma CVD method, and a thickness of 2.0 μm
After applying m-thick positive photoresist 14, the P-SiO
Under the RIE condition that the film 13 and the positive photoresist 14 have the same etching rate, the P-SiO film 13 on the wiring 12 of the first layer
Etch back to 0.2 μm.

表面清浄化後、第5図(b)に示すように1.0μm厚のP
-SiO膜15を再堆積し、平坦な層間絶縁膜層を形成後、通
常のフォトリソグラフィ法とRIE法により所定の位置に
スルーホール17を形成する。この後、通常のスパッタ
法、フォトリソグラフィ法とRIE法により、所定のパタ
ーンを有する、1.0μm厚のAl-Si-Cuから成る第2層目
の配線18を形成する。
After cleaning the surface, as shown in Fig. 5 (b), 1.0 μm thick P
-The SiO film 15 is redeposited to form a flat interlayer insulating film layer, and then the through hole 17 is formed at a predetermined position by the usual photolithography method and RIE method. After that, the second-layer wiring 18 made of Al—Si—Cu having a predetermined pattern and having a thickness of 1.0 μm is formed by the usual sputtering method, photolithography method, and RIE method.

次に、第5図(c)に示すように、トップ・パシベーシ
ョン膜19として、前述のプラズマCVD法により1.0μm厚
のP-SiO膜を堆積した後、通常のフォトリソグラフィ法
とRIE法により、所定のボンディング・パッド開孔部を
形成し、二層配線構造を完成する。
Next, as shown in FIG. 5C, as the top passivation film 19, a P-SiO film having a thickness of 1.0 μm is deposited by the above-mentioned plasma CVD method, and then by a normal photolithography method and an RIE method. A predetermined bonding pad opening is formed to complete the two-layer wiring structure.

(発明が解決しようとする課題) 一般に、半導体装置の信頼性向上のため、多層配線の層
間絶縁膜やトップ・パシベーション膜として、P-SiO膜
などの無機絶縁膜が使用されている。しかし、従来の無
機絶縁膜層形成技術には以下に示す問題点がある。
(Problems to be Solved by the Invention) Generally, in order to improve the reliability of a semiconductor device, an inorganic insulating film such as a P-SiO film is used as an interlayer insulating film or a top passivation film of a multilayer wiring. However, the conventional inorganic insulating film layer forming technique has the following problems.

従来例に示したプラズマCVD法(膜形成条件:SiH4/N2O
=200/2400SCCM-1.5KW-0.4Torr-300℃)により形成した
P-SiO膜には、膜表面から0.2μm程度の深さまでシリコ
ン過剰層16が存在することが第6図に示すオージェ電子
分析から分かる。また、第7図に一例を示すが、膜形成
条件、形成方法(プラズマCVD、減圧CVD、常圧CVD、ス
パッタ法やECRプラズマCVD法)や装置により該シリコン
過剰層16の厚さは異なるが、ほとんどの場合、形成した
膜厚の5〜35%の範囲にあることが判明している。さら
に、シリコン酸化膜以外のシリコン窒化膜やシリコン炭
化膜などの場合も、同様な範囲の厚さで、該シリコン過
剰層の形成されることも確認した。
Plasma CVD method shown in the conventional example (film forming conditions: SiH 4 / N 2 O
= 200 / 2400SCCM-1.5KW-0.4Torr-300 ℃)
It can be seen from Auger electron analysis shown in FIG. 6 that the silicon excess layer 16 exists in the P-SiO film up to a depth of about 0.2 μm from the film surface. Although an example is shown in FIG. 7, the thickness of the silicon excess layer 16 varies depending on the film forming conditions, the forming method (plasma CVD, low pressure CVD, atmospheric pressure CVD, sputtering method or ECR plasma CVD method) and equipment. It has been found that, in most cases, it is in the range of 5 to 35% of the formed film thickness. Furthermore, it was also confirmed that in the case of a silicon nitride film or a silicon carbide film other than the silicon oxide film, the silicon excess layer is formed in the same range of thickness.

該シリコン過剰層16は、膜厚制御のため形成反応を急停
止した際に質量の軽い原子(例:P-SiOの場合は酸素原
子)が膜表面から抜けることで形成されると考えられ、
該シリコン過剰層16における原子間の結合には不完全あ
るいは弱い部分が多く存在する。このため、特に電気特
性が極めて不安定となり、従来例において以下の問題点
がある。
It is considered that the silicon excess layer 16 is formed by atoms with a light mass (eg, oxygen atoms in the case of P-SiO) escaping from the film surface when the formation reaction is suddenly stopped for film thickness control,
There are many incomplete or weak bonds in the bonds between atoms in the silicon excess layer 16. For this reason, the electrical characteristics become extremely unstable, and the conventional example has the following problems.

絶縁膜上の配線間リーク・レベルが極めて高い。例え
ば、第3図に示すように、P-SiO層間絶縁膜上の第2層
目の配線間のリークは、配線間隔1.5μm、電界0.5MV/c
mで約203pA/cmと熱シリコン酸化膜上に形成した場合の
配線リーク(0.52pA/cm)の約390倍となる。
The leakage level between wirings on the insulating film is extremely high. For example, as shown in FIG. 3, the leakage between the wirings of the second layer on the P-SiO interlayer insulating film is 1.5 μm between the wirings and the electric field is 0.5 MV / c.
It is about 203 pA / cm in m, which is about 390 times the wiring leak (0.52 pA / cm) when formed on the thermal silicon oxide film.

第4図に示すようなMIS構造による界面電荷密度Nssと
BT処理による界面電荷密度の変動量ΔNssのレベルが高
い。例えば、従来例のP-SiO膜の場合、Nss=2.0×1011c
m-2と高く、BT処理(1MV/cm-300℃‐20分)後の変動量
ΔNssは、ゲート電極陽極(+BT)時でΔNss≒+1.2×1
011cm-2の正イオン可動型と正常な挙動を示すが、ゲー
ト電極(−BT)時でΔNss≒+7.5×1010cm-2と正イオン
可動形とは異なった挙動を示し、Nss変動やVthの安定
性、信頼性が低下する。尚、第4図では、n形シリコン
基板61上に、ゲート酸化膜62、P-SiO膜63、ゲート電極
(1.0μmAl)64が順次積層されている。
The interface charge density Nss due to the MIS structure as shown in FIG.
The level of variation ΔNss in the interface charge density due to BT treatment is high. For example, in the case of the conventional P-SiO film, Nss = 2.0 × 10 11 c
High as m -2 , the fluctuation amount ΔNss after BT treatment (1MV / cm-300 ° C-20 minutes) is ΔNss ≒ + 1.2 × 1 when the gate electrode is anode (+ BT)
It shows normal behavior with positive ion movable type of 0 11 cm -2 , but ΔNss ≒ +7.5 × 10 10 cm -2 at gate electrode (-BT), which is different from the positive ion movable type. Nss fluctuations and Vth stability and reliability are reduced. In FIG. 4, a gate oxide film 62, a P-SiO film 63, and a gate electrode (1.0 μm Al) 64 are sequentially laminated on an n-type silicon substrate 61.

本発明は、上記の事情に鑑みてなされたものでプラズマ
CVD法などの従来法により無機絶縁膜を形成した後、該
無機絶縁膜表面から形成膜厚の5〜35%程度の厚さに形
成されるシリコン過剰層のように、軽い構成原子が外部
拡散し、重い構成原子が過剰となった表層部を、プラズ
マ酸化などで外部拡散した軽い構成原子を補充すること
で、該表層部の膜質を改善し、電気的に安定で信頼性の
高い無機絶縁膜を形成し得る半導体装置の製造方法を提
供することを目的とする。
The present invention has been made in view of the above circumstances.
After forming an inorganic insulating film by a conventional method such as the CVD method, light constituent atoms such as a silicon excess layer formed from the surface of the inorganic insulating film to a thickness of about 5 to 35% of the formed film diffuses outwardly. However, by supplementing the surface layer portion where the heavy constituent atoms are excessive with the light constituent atoms that have been diffused outward by plasma oxidation, etc., the film quality of the surface layer portion is improved, and electrically stable and highly reliable inorganic insulation An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a film.

[発明の構成] (課題を解決するための手段と作用) 本発明は、所定の構造とパターンを有する半導体基板上
に、層間絶縁膜あるいはパシベーション膜として、無機
絶縁膜を形成する場合において、プラズマCVD法などで
無機絶縁膜を形成後、該無機絶縁膜形成反応終了時に軽
い構成原子の少なくとも一部が外部拡散し、重い構成原
子が過剰となった該無機絶縁膜の表層部の膜質改善を目
的に、該重い構成原子と反応し、該無機絶縁膜と同等の
膜質の安定な絶縁膜形成に必要な、少なくとも1種類以
上のより軽い原子例えば、酸素、窒素、炭素などを含む
雰囲気によるプラズマ処理を行なうことを特徴とした無
機絶縁膜形成技術であり、該プラズマ処理で損失した軽
い構成原子を補充し、該重い構成原子の過剰層を改質し
て、電気的特性などの安定した、より信頼性の高い無機
絶縁膜の形成を容易に実現できる。
[Structure of the Invention] (Means and Actions for Solving the Problems) The present invention is directed to plasma formation when an inorganic insulating film is formed as an interlayer insulating film or a passivation film on a semiconductor substrate having a predetermined structure and pattern. After forming the inorganic insulating film by the CVD method or the like, at the end of the inorganic insulating film forming reaction, at least a part of the light constituent atoms are out-diffused, and the heavy constituent atoms are excessive. For the purpose, plasma in an atmosphere containing at least one kind of lighter atom, such as oxygen, nitrogen, or carbon, which reacts with the heavy constituent atoms and is necessary for forming a stable insulating film having a film quality equivalent to that of the inorganic insulating film. This is an inorganic insulating film forming technique characterized by performing a treatment, by supplementing light constituent atoms lost by the plasma treatment and modifying an excess layer of the heavy constituent atoms to obtain electrical characteristics, etc. Stable, can be easily realized in the formation of more reliable inorganic insulating film.

(実施例) 以下図面を参照して本発明の実施例を詳細に説明する。Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図(a),(b),(c),(d)は本発明の一実
施例を示す。即ち、第1図(a)に示すように、熱シリ
コン酸化膜の形成された半導体基板71上に、通常のスパ
ッタ法で1.0μm厚のAl-Si-Cu膜を堆積した後、通常の
フォトリソグラフィ法とRIE法により所定のパターンを
有する第1層目の配線72を形成した。プラズマCVD法(S
iH4/N2O=200/2400SCCM-0.4Torr-1.5KW-300℃)により
1.5μm厚のP-SiO膜73を堆積し、ポジ系フォトレジスト
74を2.0μm厚に塗布した後、RIE法(CHF3/C2F6/O2/He
=10/35/20/35SCCM-3.0Torr-550W)によりP-SiO膜73と
該ポジ系フォトレジスト74を同一のエッチング速度で、
該第1層目の配線72上の該P-SiO膜73の膜厚が0.2μmに
なるまでエッチ・バックした。
1 (a), (b), (c) and (d) show one embodiment of the present invention. That is, as shown in FIG. 1A, a 1.0 μm thick Al—Si—Cu film is deposited on a semiconductor substrate 71 on which a thermal silicon oxide film is formed by a normal sputtering method, and then a normal photo film is formed. The wiring 72 of the first layer having a predetermined pattern was formed by the lithography method and the RIE method. Plasma CVD method (S
iH 4 / N 2 O = 200 / 2400SCCM-0.4Torr-1.5KW-300 ℃)
P-SiO film 73 with a thickness of 1.5 μm is deposited, and a positive photoresist is used.
After applying 74 to 2.0 μm thick, RIE method (CHF 3 / C 2 F 6 / O 2 / He
= 10/35/20 / 35SCCM-3.0Torr-550W) with the same etching rate for the P-SiO film 73 and the positive photoresist 74,
Etching back was performed until the film thickness of the P-SiO film 73 on the wiring 72 of the first layer became 0.2 μm.

O2プラズマ・アッシング法と流水水洗による表面清浄
後、第1図(b)に示すように、1.0μm厚のP-SiO膜75
を前述と同じプラズマCVD条件で堆積し、プラズマCVD装
置の到達真空度まで引き、連続してN2Oによるプラズマ
処理(N2O=2800SCCM-0.4Torr-1.2KW-300℃)を行なっ
た。該プラズマ処理により、堆積後に該P-SiO膜75の表
層に堆積膜厚の20%に相当する0.20μm厚で存在するシ
リコン過剰層76(第2図に示すようにオージェ電子分析
で確認)をおおむねP-SiO膜に改質した。76′が膜質の
改善された部分である。
After surface cleaning by O 2 plasma ashing method and washing with running water, as shown in FIG. 1 (b), P-SiO film 75 with a thickness of 1.0 μm
Was deposited in the same plasma CVD conditions as described above, pull up the ultimate vacuum of the plasma CVD apparatus was conducted continuously N 2 O by plasma treatment (N 2 O = 2800SCCM-0.4Torr -1.2KW-300 ℃). By the plasma treatment, a silicon excess layer 76 (confirmed by Auger electron analysis as shown in FIG. 2) existing in a surface layer of the P-SiO film 75 after deposition with a thickness of 0.20 μm corresponding to 20% of the deposited film thickness is formed. It was modified to a P-SiO film. 76 'is the part with improved film quality.

次に第1図(c)に示すように、通常のフォトリソグラ
フィ法とRIE法により所定の位置にスルーホール77を形
成した後、通常のスパッタ法、フォトリソグラフィ法と
RIE法により所定のパターンを有する1.0μm厚のAl-Si-
Cuから成る第2層目の配線78を形成した。
Next, as shown in FIG. 1 (c), after forming through holes 77 at predetermined positions by the ordinary photolithography method and the RIE method, the ordinary sputtering method and the photolithography method are used.
1.0μm thick Al-Si- having a predetermined pattern by RIE method
A second wiring layer 78 made of Cu was formed.

次に、第1図(d)に示すように、トップ・パシベーシ
ョン膜79として、前述のプラズマCVD条件による1.0μm
厚のP-SiO膜を堆積し、該プラズマ処理を行なった後、
通常のフォトリソグラフィ法とRIE法により所定のボン
ディング・パッド開孔部を形成し本発明による二層配線
構造を完成した。
Next, as shown in FIG. 1D, as the top passivation film 79, 1.0 μm under the plasma CVD conditions described above is used.
After depositing a thick P-SiO film and performing the plasma treatment,
A predetermined bonding pad opening portion was formed by the usual photolithography method and RIE method to complete the two-layer wiring structure according to the present invention.

尚、上記実施例では、多層配線の層間絶縁膜を例として
いるが、パシベーション膜など半導体基板上に形成され
る無機絶縁膜であれば、どの段階で適応しても良い。
In the above-mentioned embodiment, the interlayer insulating film of the multi-layer wiring is taken as an example, but it may be applied at any stage as long as it is an inorganic insulating film formed on the semiconductor substrate such as a passivation film.

又、上記実施例では、無機絶縁膜としてプラズマCVD法
によるP-SiO膜を用いたが、形成法はプラズマCVD法以外
の減圧CVD法、常圧CVD法やECRプラズマCVD法などの化学
気相成長法あるいはスパッタ法などの物理成長であれば
良く、形成される膜種類もシリコン酸化膜、シリコン窒
化膜、シリコン炭化膜などのシリコン化合物による無機
絶縁膜あるいはシリコン化合物以外で半導体装置に適応
できる無機絶縁膜であれば良いことは云うまでもない。
Further, in the above embodiment, the P-SiO film formed by the plasma CVD method was used as the inorganic insulating film, but the forming method is a low pressure CVD method other than the plasma CVD method, a chemical vapor phase method such as the atmospheric pressure CVD method or the ECR plasma CVD method. Any physical growth such as a growth method or a sputtering method may be used, and an inorganic insulating film made of a silicon compound such as a silicon oxide film, a silicon nitride film, or a silicon carbide film, or an inorganic material other than a silicon compound that can be applied to a semiconductor device It goes without saying that any insulating film may be used.

更に、上記実施例で用いたP-SiO膜のようなシリコン化
合物では、膜表層部にシリコン過剰層が形成されるが、
シリコン化合物以外でも、前述のように軽い構成原子の
外部拡散により重い構成原子の過剰層が形成されること
は云うまでもない。
Further, in the silicon compound such as the P-SiO film used in the above example, a silicon excess layer is formed in the film surface layer portion,
Needless to say, other than silicon compounds, an excess layer of heavy constituent atoms is formed by the outdiffusion of light constituent atoms as described above.

又、本実施例では、P-SiO膜表層に形成されたシリコン
過剰層の改質のため、N2Oプラズマ処理を行ない、該シ
リコン過剰層を概ね正常なP-SiO膜としているが、軽い
構成原子の外部拡散による重い構成原子の過剰層を安定
な絶縁膜に改善することを目的としたプラズマ処理に
は、該重い構成原子と反応し、安定な絶縁膜を形成する
外部拡散した相対的に軽い元素と同種の少なくとも1種
類以上のより軽い原子を含むガス雰囲気であれば良く、
重い構成原子の過剰層が改質された膜質が安定な絶縁膜
で、該重い原子の過剰層下に形成された膜質と同等であ
れば良い。つまり、表層のシリコン過剰層の膜質改善の
ため、N2O以外のO2、N2、NO、NO2、CO、CO2、CH4、C2H8
どのSi原子と反応する、O、N、C原子を供給する少な
くとも1種類以上のガスによるプラズマ処理を行ない、
改質された膜質がP-SiO以外のP-SiN、P-SiCあるいはこ
れらの安定な中間的絶縁物質であれば良い。
In addition, in the present embodiment, N 2 O plasma treatment is performed to modify the silicon excess layer formed on the surface layer of the P-SiO film, and the silicon excess layer is a normal P-SiO film. The plasma treatment aimed at improving the excess layer of heavy constituent atoms by the outdiffusion of the constituent atoms into a stable insulating film is performed by reacting with the heavy constituent atoms to form a stable insulating film. A gas atmosphere containing at least one lighter atom of the same kind as the light element,
It suffices that the film quality obtained by modifying the excess layer of heavy constituent atoms is a stable insulating film and is equivalent to the film quality formed under the excess layer of heavy atoms. That is, in order to improve the film quality of the silicon-rich layer on the surface layer, O that reacts with Si atoms such as O 2 , N 2 , NO, NO 2 , CO, CO 2 , CH 4 , C 2 H 8 other than N 2 O, , Plasma treatment with at least one gas supplying N, C atoms,
The modified film quality may be P-SiN other than P-SiO, P-SiC, or a stable intermediate insulating material of these.

また、重い原子の過剰層の膜質改善のためのプラズマ処
理の条件は安定に絶縁膜が形成されるものなら良く、無
機絶縁膜の形成と必ずしも連続して行なう必要はない。
Further, the condition of the plasma treatment for improving the film quality of the excessive layer of heavy atoms is only required to form the insulating film in a stable manner, and it is not always necessary to continuously perform the formation of the inorganic insulating film.

なお、「重い」、「軽い」と云う意味は原子量の相対的
な差を示す。
The meanings of “heavy” and “light” indicate relative differences in atomic weight.

[発明の効果] 以上のように本発明は、プラズマCVD法などの化学気相
成長法あるいはスパッタ法などの物理成長法により形成
された無機絶縁膜表層に存在する、軽い構成原子が外部
拡散して重い構成原子が過剰となった不安定層を、該重
い構成原子と反応し、安定な絶縁膜の形成に必要な少な
くとも1種類以上の相対的に軽い原子を含むガス雰囲気
でプラズマ処理を行ない、過剰な重い原子に損失した軽
い原子と同種の相対的に軽い原子を補充し、安定な絶縁
膜層にすることを特徴とし、以下のような効果がある。
[Effects of the Invention] As described above, according to the present invention, light constituent atoms existing in the surface layer of an inorganic insulating film formed by a chemical vapor deposition method such as plasma CVD method or a physical growth method such as sputtering method are diffused out. Of the unstable layer containing excess heavy constituent atoms is reacted with the heavy constituent atoms, and plasma treatment is performed in a gas atmosphere containing at least one kind of relatively light atom necessary for forming a stable insulating film. The present invention is characterized by supplementing excess heavy atoms with relatively light atoms of the same kind as the lost light atoms to form a stable insulating film layer, and has the following effects.

無機絶縁膜表面のリーク・レベルが極めて低い。実施
例におけるP-SiO層間絶縁膜上の第2層目の配線間リー
クは、従来と同一測定条件(配線間隔1.5μm、印加電
界0.5MV/cm)で、0.8〜1.0pA/cmと従来例の約1/203〜1/
254と極めて低いレベルにある(第3図参照)。
The leak level on the surface of the inorganic insulating film is extremely low. The leakage between the wirings of the second layer on the P-SiO interlayer insulating film in the example is 0.8 to 1.0 pA / cm under the same measurement condition as the conventional one (wiring interval 1.5 μm, applied electric field 0.5 MV / cm), and the conventional example. About 1/203 ~ 1 /
It is at a very low level of 254 (see Fig. 3).

第4図に示すMIS構造による界面電荷密度Nss=1.1×1
011cm-2と従来例の約1/2であり、BT処理(1MV/cm-300℃
‐20分)後の変動量ΔNssは、ゲート電極陽極(+BT)
時でΔNss≒+6.5×1010cm-2、ゲート電極陰極(−BT)
時でΔNss=+0.52×1010cm-2(ほとんど増加なし)と
正常な正イオン可動型の挙動を示し、Nss、ΔNssのレベ
ルは共に低く、安定性、信頼性の向上を示している。
Interface charge density Nss = 1.1 × 1 according to the MIS structure shown in FIG.
0 11 cm -2 , which is about half that of the conventional example, and BT treatment (1MV / cm-300 ° C
After -20 minutes, the fluctuation amount ΔNss is the gate electrode anode (+ BT)
ΔNss ≒ + 6.5 × 10 10 cm -2 , gate electrode cathode (-BT)
ΔNss = + 0.52 × 10 10 cm -2 (almost no increase) and normal positive ion movable type behavior, and both Nss and ΔNss levels are low, indicating improved stability and reliability. .

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例の形成工程を示す断面図、第
2図は本発明によるシリコン過剰層膜質改善効果を示す
オージェ電子分析の結果の一例を示す特性図、第3図は
本発明及び従来による無機絶縁膜上配線間リーク測定結
果の一例を示す特性図、第4図はMIS構造半導体装置の
一例を示す断面図、第5図は従来の無機絶縁膜の形成工
程を示す断面図、第6図は従来のP-SiO膜表層にシリコ
ン過剰層の存在を示すオージェ電子分析の結果を示す特
性図、第7図は従来のシリコン過剰層のプラズマCVD条
件依存性の一例を示す特性図である。 71……半導体基板、72……第1層目の配線、73……P-Si
O膜、74……ポジ型フォトレジスト、75……P-SiO膜、76
……シリコン過剰層、77……スルーホール、78……第2
層目の配線、79……トップ・パシベーション膜。
FIG. 1 is a cross-sectional view showing a forming process of one embodiment of the present invention, FIG. 2 is a characteristic diagram showing an example of the result of Auger electron analysis showing the effect of improving the quality of a silicon excess layer film according to the present invention, and FIG. FIG. 4 is a characteristic view showing an example of leak measurement results between wirings on an inorganic insulating film according to the invention and the prior art, FIG. 4 is a sectional view showing an example of a MIS structure semiconductor device, and FIG. 5 is a sectional view showing a conventional inorganic insulating film forming process. 6 and 6 are characteristic diagrams showing the results of Auger electron analysis showing the existence of a silicon excess layer on the surface layer of a conventional P-SiO film, and FIG. 7 shows an example of the plasma CVD condition dependency of the conventional silicon excess layer. It is a characteristic diagram. 71 …… Semiconductor substrate, 72 …… First layer wiring, 73 …… P-Si
O film, 74 …… Positive photoresist, 75 …… P-SiO film, 76
…… Silicon excess layer, 77 …… Through hole, 78 …… Second
Wiring of the first layer, 79 ... Top passivation film.

フロントページの続き (56)参考文献 特開 昭54−2070(JP,A) 特開 昭55−113335(JP,A) 特開 昭60−54469(JP,A)Continuation of front page (56) Reference JP 54-2070 (JP, A) JP 55-113335 (JP, A) JP 60-54469 (JP, A)

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に無機絶縁膜を形成する半導
体装置の製造方法において、半導体基板上に無機絶縁膜
を形成する工程と、この工程により形成された無機絶縁
膜の相対的に重い構成元素と反応し、該無機絶縁膜と同
等の膜質の安定な絶縁膜の形成に必要な少なくとも1種
類以上の相対的に軽い構成元素を含むガス雰囲気でのプ
ラズマ処理を行う工程とを具備したことを特徴とする半
導体装置の製造方法。
1. A method of manufacturing a semiconductor device in which an inorganic insulating film is formed on a semiconductor substrate, the step of forming the inorganic insulating film on the semiconductor substrate, and the relatively heavy structure of the inorganic insulating film formed by this step. And a step of performing plasma treatment in a gas atmosphere containing at least one kind of relatively light constituent element necessary for forming a stable insulating film having a film quality equivalent to that of the inorganic insulating film. A method for manufacturing a semiconductor device, comprising:
【請求項2】無機絶縁膜を形成する工程とプラズマ処理
を行う工程が、半導体基板を大気に晒すことなく連続的
に行なわれることを特徴とする請求項1記載の半導体装
置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the inorganic insulating film and the step of performing the plasma treatment are continuously performed without exposing the semiconductor substrate to the atmosphere.
【請求項3】重い構成元素として少なくともSiを含むこ
とを特徴とする請求項1記載の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein at least Si is contained as a heavy constituent element.
【請求項4】相対的に軽い構成元素としてO、N、Cの
中の少なくとも1種類以上を含むことを特徴とする請求
項1記載の半導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of O, N, and C is contained as a relatively light constituent element.
JP63257682A 1988-10-13 1988-10-13 Method for manufacturing semiconductor device Expired - Fee Related JPH0691082B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63257682A JPH0691082B2 (en) 1988-10-13 1988-10-13 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63257682A JPH0691082B2 (en) 1988-10-13 1988-10-13 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02103935A JPH02103935A (en) 1990-04-17
JPH0691082B2 true JPH0691082B2 (en) 1994-11-14

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Country Status (1)

Country Link
JP (1) JPH0691082B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2659600B2 (en) * 1990-01-18 1997-09-30 三菱電機株式会社 Method for manufacturing semiconductor device
JP2888158B2 (en) * 1995-01-18 1999-05-10 日本電気株式会社 Manufacturing method of surface acoustic wave device
US6541369B2 (en) * 1999-12-07 2003-04-01 Applied Materials, Inc. Method and apparatus for reducing fixed charges in a semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS542070A (en) * 1977-06-07 1979-01-09 Toshiba Corp Manufacture for semiconductor element
JPS55113335A (en) * 1979-02-23 1980-09-01 Fujitsu Ltd Manufacture of semiconductor device
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