JPH02101772A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize high speed operation and high density integration by forming MOS transistors on an upper crystallized semiconductor layer and a lower semiconductor substrate, and commonly use a part of the source.drain and the gate of the respective transistors. CONSTITUTION:MOS transistors Q1 and Q2 laminated in the following manner constitute mutually electrodes of the other element. The source or the drain of the MOS transistor Q1 on a substrate 10 is laminated on the MOS of a SOI film and the gate electrode of the MOS transistor Q2, via an insulating film 30 between the substrate 10 and a semiconductor layer. On the contrary, the source or the drain of the MOS transistor Q2 is laminated on the gate electrode of the MOS transistor Q1. As a result, the integration degree can be remarkably increased by utilizing the lamination structure; the contact resistance of wiring parts and the delay time can be reduced; the number of processes of the wiring parts can be decreased.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is based on S 01 (S11icon On In5
The present invention relates to an MO3 type semiconductor device to which ulator technology is applied and a method for manufacturing the same.

(Prior Art) Conventionally, only MO5 type semiconductor devices using SOI technology have been used.

In such a method, it cannot be said that the advantages of the SOI stacked structure are effectively utilized, and problems that need to be improved remain. For example, in the method (■), the MOS element on the substrate and the M in the SOI film are
Wiring is required to connect the OS elements, and although the length of this wiring is shorter than when each element is formed two-dimensionally, it cannot be said to be sufficiently short. Further, it is necessary to conduct wiring around the MOS element, and the wiring area for this becomes a factor that impedes higher speed and higher integration of the element.

(Problems to be Solved by the Invention) As described above, although there is a conventional method of manufacturing an MO8 type semiconductor device using the SO2 technology, it has not been possible to fully utilize the inherent advantages of the Sol structure.

The present invention has been made in consideration of the above circumstances, and its purpose is to fully utilize the true advantages of the SOI stacked structure and apply it to circuit functions. The gist of the present invention is to form a MOS transistor in each of the upper recrystallized semiconductor layer and the lower semiconductor substrate via an insulating film, and to partially share the source, drain, and gate of each transistor. It is in.

That is, in the present invention, a single crystal semiconductor layer is provided on a semiconductor substrate via an insulating film, and two MOS
In an MO8 type semiconductor device in which a transistor is formed,
A source and a drain of a first MOS transistor are formed on the surface of the substrate, and one of the source and drain of a second MOS transistor is formed on the surface of the substrate.
The source and drain of the second MOS transistor are formed in the semiconductor layer, and one of the source and drain also serves as the gate of the first MOS transistor.

The present invention also provides a method for manufacturing a semiconductor device having the above structure, in which a single crystal semiconductor layer of a second conductivity type is formed on a semiconductor substrate of a first or second conductivity type via an insulating film, and then a single crystal semiconductor layer of a second conductivity type is formed on a semiconductor substrate of a first or second conductivity type. a first conductivity type diffusion layer formed on the surface of the semiconductor layer at a predetermined distance from each other and having a source and a drain, and one of the second conductivity type layers adjacent to the first conductivity type diffusion layer formed in the semiconductor layer as a gate; A MOS transistor is configured, in which a second conductivity type layer sandwiching a first conductivity type diffusion layer formed in the semiconductor layer is used as a source and a drain, and one of the first conductivity type diffusion layers formed in the substrate is used as a gate. This is a method for configuring a second MOS transistor.

(Function) According to the present invention, the MOS element (first MOS element) on the substrate is
The source or drain of the MOS transistor (S transistor) is the gate electrode of the MOS element (second MOS transistor) in the SOI film, or vice versa, the source or drain of the second MOS transistor is the gate electrode of the first MOS transistor,
The MOS transistors stacked one above the other serve as electrodes for other elements. Therefore, it is possible to significantly increase the degree of integration by using a stacked structure, and the first conductivity type diffusion layer, which becomes the source/drain region of the first MOS transistor and the channel region of the second MOS transistor, can be formed in the same layer. Since the required impurity diffusion layers of the substrate and the SOI film can be formed simultaneously using a mask, that is, the necessary impurity diffusion layers of the substrate and the SOI film can be formed by self-alignment, it is possible to reduce the number of patterning steps and the number of required masks. Furthermore, by making full use of the high degree of integration, which is an advantage of the stacked structure, the area occupied can be significantly reduced compared to the conventional technology.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a perspective view showing a schematic configuration of a MOS type semiconductor device according to an embodiment of the present invention. In the figure, reference numeral 10 denotes an n-type single crystal silicon substrate, and p+ type layers 21 and 22 are formed in the surface layer of this substrate 10 by impurity diffusion. p+
The mold layers 21 and 22 serve as source/drain regions when forming a MOS transistor. Note that the p1 type layer is 21°. Note that 60 in the figure indicates an oxide film for element isolation.

FIG. 2 shows a cross section showing the manufacturing process of the semiconductor device, in which a single crystal silicon layer 40 is formed. This silicon layer 40 has n+ type layers 41, 42 and p type layers 43 due to impurity diffusion.
is formed. The p-type layer 43 becomes the channel region of the MOS transistor, and the n-type layer 43 on both sides of the p-type layer 43
The + type layers 41 and 42 become the source and drain regions of the MOS transistor. In addition, the thin insulating film is MOS
This becomes the gate oxide film of the transistor.

Here, the n+ type layer 42 is arranged on the channel region 23 between the p+ type layers 21 and 22, and the p+ type layer 21 is arranged on the n1 type layer 4.
1.42 and below the channel region 43.

A first p-channel MOS transistor is constructed from the p1 type layer 21° 22 and the n+ type layer 42, and a second n channel MOS transistor is constructed from the n+ type layer 41° 42 and the p1 type layer 21. Specifically speaking, phosphorus is 130KeV', dose I x 1016c+
Ion implantation is performed under o-3 conditions to form a p-type layer 20 over the entire surface of the substrate 10. The purpose of this implantation of p-type impurity ions is to make the impurity concentration on the substrate surface uniform.

Thereafter, a polycrystalline silicon layer 40' is deposited on the gate oxide film 30 by the CVD method.

Next, the polycrystalline silicon layer 40' is recrystallized by annealing with an electron beam to form a silicon single crystal layer 40 as shown in FIG. 2(b). At this time, amorphous silicon may be recrystallized instead of polycrystalline silicon, and other energy beams such as a laser beam or an ion beam may be used instead of the electron beam. Furthermore, a recrystallization method using a tungsten heater or zone melting, or a recrystallization method using lamp annealing may be used. Alternatively, recrystallization may be performed by forming a protective film such as SiO□ on the top. After that, n
A type impurity is ion-implanted to form an n+ type layer.

Next, as shown in FIG. 2(C), a voltage at which n-type impurities are ion-implanted is selected. As a result, a p+ type layer 21. ．． 22 is formed, and a silicon layer 40 is formed.
A p-type layer 43 is formed thereon. Here, a p+ type layer (source◆drain) is formed on the substrate surface by ion implantation of n type impurities.
21 and 22 are formed, and by forming a p-type layer 43 on the silicon layer 40, n+-type layers (source/drain regions) 41 and 42 are formed on both sides of the layer 43.

That is, the sources and drains of the two MOS transistors are realized by self-aligned lines.

Next, as shown in FIG. 2(d), the mask 50 is removed, and only necessary portions of the silicon layer 40 are patterned into island shapes, and further element isolation is performed as necessary.

Note that instead of the step shown in FIG. 2(e), the silicon layer 40 may be patterned into an island shape in advance, and the ion implantation may be performed after forming a mask 50 as shown in FIG. 2(e). . Further, during this ion implantation, an oxide film or the like may be formed as a protective film on the side wall of the silicon layer 40.

A second MO3I-transistor (n-channel enhancement type) Q2 is formed, with 42 as a source and drain and the p+ type layer 21 as a gate.

In other words, the drain of transistor Q1 is
A configuration is realized in which the source of transistor Q2 also serves as the gate of transistor Q2. In this case, unlike the conventional device, the two transistors Q1. It becomes possible to stack Q2.

Next, an example in which the device of this embodiment is applied to a MOS inverter will be described. FIG. 3(a) is a cross-sectional view schematically showing the basic structure of a MOS inverter, and FIG. 3(b) is an equivalent circuit configuration diagram thereof. The drain of transistor Q is connected to the gate of transistor Q2, and their connection point becomes an input terminal. Further, the source of the transistor Q2 is connected to the gate of the transistor Q1, and the connection point thereof is grounded via a resistor R1. This resistance R1 is approximately the same size as the effective resistance of the channel, and is connected to ground here. This resistance R2 needs to be larger than R1, and here it is set to 20Ω.

In the above configuration, when the input signal is set to "H" and an input signal of IV is input, since the transistor Q2 is an n-channel, the closed gate opens and current flows from the drain to the source. At this time, the effective resistance of the channel is IKΩ, and the resistor R1 connected to the source is also grounded at IKΩ, so a gate voltage of 2.5V is applied to the gate of the transistor Q1. Since the transistor Q1 is an n-channel, the gate is closed and the output section connected to the source section is "
L” (OV), and the output signal is inverted.

On the other hand, when the input is "L", the input signal is 0. When IV is applied, the gate of transistor Q2 is closed, the potential of the source becomes OV, the gate of transistor Q1 becomes Ov, and the gate is opened. Then, the input signal 0. lV becomes the drain voltage, and current flows. The resistance connected to the source is sufficiently large compared to the effective resistance of the channel, and there is almost no voltage effect.
It was 20 picoseconds. This means that a high speed exceeding 30 picoseconds of the semiconductor device formed by the conventional method was achieved. Furthermore, when we compared the area occupied by the device, we were able to reduce it to less than 0% compared to the conventional device.

Thus, according to this embodiment, a MOS transistor is formed on the substrate and an SOI film, and a part of each electrode is also used, thereby providing a semiconductor device that has no signal delay and achieves high integration. be able to. Further, the impurity diffusion process for forming the source, drain, etc. can be performed in a self-aligned manner using the first and second MOS transistors, which has the advantage of simplifying the manufacturing process.

Note that the present invention is not limited to the embodiments described above. For example, the same effect can be obtained by using germanium, gallium arsenide, indium phosphide, or the like instead of the silicon substrate. Furthermore, although a single-crystal silicon wafer was used as the semiconductor substrate in the examples, a single-crystal semiconductor thin film obtained by recrystallization, such as SOS (Silicon O
n 5apphtre ) can also be used.

In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, MO8I is applied to each of the upper recrystallized semiconductor layer and the lower semiconductor substrate via the insulating film.
- By forming a transistor and sharing part of the source, drain, and gate of each transistor, SO
It is possible to realize a semiconductor device and a method for manufacturing the same, which fully utilizes the true advantages of the I-stacked structure and can achieve significantly higher speed and higher integration than conventional devices.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a schematic configuration of a MOS type semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of the above semiconductor device, and FIG. 3 is an inverter using the above semiconductor device. FIG. 2 is a schematic diagram and a circuit diagram showing the basic configuration. DESCRIPTION OF SYMBOLS 10... N-type single crystal silicon substrate, 20... P-type layer, 2.1.22... p''-ff layer (source/drain region), 23... P-type layer (channel region) , 30...
・Gate oxide film (insulating film) 40'... Polycrystalline silicon layer, 40... Single crystal silicon layer, 41.42...
n + type layer (source/drain region), 43... p type layer (channel region), 50... mask, 60... insulating film for element isolation %Q1... first MOS transistor (
p channel depletion type), Q2... second MOS transistor (n channel enhancement type), R+, R2... resistor. Applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka 2nd @

Claims (4)

[Claims] (1) In a MOS semiconductor device in which a single crystal semiconductor layer is provided on a semiconductor substrate with an insulating film interposed therebetween, and two MOS transistors are formed on these substrates and the semiconductor layer, the source and drain of the first MOS transistor are connected to the substrate. one of the source and drain also serves as the gate of the second MOS transistor, the source and drain of the second MOS transistor are formed on the semiconductor layer, and one of the source and drain is the first A semiconductor device characterized in that it also serves as a gate of a MOS transistor. (2) In a semiconductor device in which a single crystal semiconductor layer is provided on a semiconductor substrate via an insulating film, and desired elements are formed on these substrates and the semiconductor layer, a diffusion layer of a first conductivity type; and a diffusion layer of a second conductivity type provided at a predetermined distance in the semiconductor layer, one of the first conductivity type diffusion layers being a diffusion layer of the second conductivity type; one of the second conductivity type diffusion layers is located under the interlayer region, and one of the second conductivity type diffusion layers is located above the first conductivity type diffusion layer region, and the first conductivity type diffusion layer is used as a source and drain, and the second conductivity type diffusion layer is located under the interlayer region.
A first MOS transistor having one of the conductivity type diffusion layers as a gate, and a second MOS transistor having the second conductivity type diffusion layer as a source/drain and one of the first conductivity type diffusion layers as a gate. A semiconductor device characterized by comprising: (3) The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is a single-crystal silicon substrate or a single-crystal silicon layer formed on a single-crystal silicon substrate with an insulating film interposed therebetween. (4) forming a second conductivity type single crystal semiconductor layer on the first or second conductivity type semiconductor substrate via an insulating film; and providing a mask at a predetermined distance on the semiconductor layer; ion-implanting an impurity of one conductivity type to form a first conductivity type diffusion layer on the substrate surface and the semiconductor layer, respectively, and using the first conductivity type diffusion layer formed on the substrate surface as a source.
A first MOS transistor whose drain is one of the second conductivity type layers adjacent to the first conductivity type diffusion layer formed in the semiconductor layer is configured, and the first conductivity type diffusion layer formed in the semiconductor layer is configured as a first MOS transistor. A method for manufacturing a semiconductor device, comprising configuring a second MOS transistor in which the second conductivity type layers sandwiching the layers serve as a source and the drain, and one of the first conductivity type diffusion layers formed in the substrate serves as a gate.