JPH02100125A - Fifo memory circuit - Google Patents

Abstract

PURPOSE:To sufficiently display the capacity of a microprocessor by holding the data which is read out of a memory in accordance with a selection of plural read-out address automatic updating circuits, and switching a write operation and a read-out operation of each circuit by a permitting signal commanded from the outside. CONSTITUTION:By connecting the memory circuit to between microprocessors and inputting a write permitting signal SW from one microprocessor, write data DW can be written continuously in a memory in accordance with a write address which is updated automatically. Also, by inputting a read-out permitting signal SR from one microprocessor and inputting start addresses Aa, Ab to prescribed read-out address updating circuits 17, 18, the data can be read out of the memory in accordance with a read-out address which is updated automatically. These read-out data DRa, DRb are preread and held temporarily in holding circuits 19, 20, therefore, continuous read-out of a high speed can be executed. In such a way, although there are plural read-out paths, since a control circuit 11 selects them automatically, read-out of continuous data can be executed independently to each other.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a FIFO that is used to transfer digitized continuous data between microprocessors at high speed and to store data at high speed. Regarding memory circuits.

(Prior Art) Generally, FIFO (First-In First-Out) is used to transfer digitized continuous data between microprocessors.
) memory circuit or dual port RAM (D
ual Port Random Access Me
mmory) circuit is used.

However, although conventional FIFO memory circuits are excellent at passing continuous data, they cannot read the same data again. If it is necessary to reread the same data, a separate memory circuit is required, and additional processing such as data movement increases, resulting in a large amount of time loss when handling a large amount of data. .

In addition, a dual boat RAM circuit can read or reread stored data from two ports independently, but in order to read data, the microprocessor must manage the RAM address externally or internally. However, when dealing with a large amount of data, there is still a problem of large time loss.

(Problems to be Solved by the Invention) As mentioned above, conventional memory circuits such as FIFO memory circuits and dual port RAM circuits have a large loss in memory data writing and reading time, so it is difficult to use microprocessors. When digital signal processing is performed using a microprocessor, a significant processing delay occurs, and even if the processing speed of the microprocessor is high, it is not possible to fully utilize its capabilities.

This invention was made to solve the above problem.
It is an object of the present invention to provide a FIFO memory circuit that can read and write continuous data in the minimum operation unit of a microprocessor, and can fully utilize the capabilities of a high-speed processing microprocessor that processes signals in real time. purpose.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the FIFO memory circuit according to the present invention is capable of manually writing data into an area specified by a write address, and which is specified by a read address. a write address automatic update circuit that automatically updates the write address after the previous data has been written; a plurality of read address automatic update circuits that automatically update; an address control circuit that selectively derives addresses output from the write address automatic update circuit and the plurality of read address automatic update circuits to the memory; and the memory. a plurality of holding circuits that hold data read from the plurality of read address automatic update circuits in accordance with selections of the plurality of read address automatic update circuits; and a write/reader that switches the write operation and read operation of each of the circuits by an externally commanded permission signal. and a switching means.

(Operation) The FIFO memory circuit having the above configuration is connected between microprocessors, and by inputting a write enable signal from one microprocessor, write data is continuously written to the memory according to the write address that is automatically updated. can be included.

Further, by inputting a read permission signal from one of the microprocessors and manually inputting a start address to a predetermined read address update circuit, data can be read from the memory according to the automatically updated read address. Since this read data is pre-read and temporarily held in the holding circuit, high-speed continuous reading is possible. Although there are a plurality of such readout paths, continuous data can be read out independently of each other by automatically selecting one by the control circuit.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows its configuration, and reference numeral 11 in the figure is a control circuit that collectively controls the following circuits, sets their operation timing, and switches between the write state and read state. It is. This control circuit 11 sets the circuit to a write state by inputting a write permission signal SW from a microprocessor (not shown), and sets the circuit to a write state by inputting a read permission signal SR.
A control signal is output to each circuit such that the input of the reset signal R sets the circuit in the read state, and the input of the reset signal R returns the circuit to the initial state and sets the circuit in the write state.

In the write state, the write permission signal Sw is
1, this control circuit 11 updates the write address automatic update circuit 12, the address control circuit 13, and the RAM 14.
, sends a control command signal to the buffer circuit 15, and sets each circuit to a write operation state. The write address automatic update circuit 12 automatically updates write addresses sequentially, and the write addresses generated here are input to the RAM 14 through the address control circuit 13. This RAM1
4 has write data DW (write data input capo) 1B
The data are input via the buffer circuit 15 and written sequentially according to the write address.

In the read state, the read permission signal SR is
1, this control circuit 11 updates the first and second read address automatic update circuits 17 . Ig, address control circuit 13, RAM 14, first and second data holding circuits 1
9. Send a control command signal at 20, and set each circuit to read operation state. First and second address automatic update circuits 17
．． 18 are start addresses Aa each set externally.
, Ab are input, the read address is automatically updated sequentially from the address value. However, the starting address is Aa.

It is assumed that Ab is not input at the same time.

First or second read address automatic update circuit 17, 1
The read address generated in step 8 is sent to the address control circuit 13.
The data is input to the RAM 14 through. In this RAM 14, data is sequentially read out based on the input read address. This read data has starting addresses Aa and Ab.
The data is held in the holding circuits 19 and 20 on the side selected by . The read data D Ra +D, b held in this holding circuit I9 or 20 is read data output port 2.
1.22 to the required microprocessor (not shown). A write/read mode signal W/R outputted from the control circuit 11 is sent to a microprocessor (not shown), so that the state of the memory circuit can be known.

The operation of the above configuration will be described below with reference to FIGS. 2 and 3.

First, a write mode is set by inputting a reset signal R, and the address control circuit 13 selects a write address to enable data writing. Here, write data D is input to the RAM 14 via the buffer circuit 15 and written to the area designated by the write address. At the same time, the write address automatic update circuit 12 operates, the write address is updated, and preparation for the next write is completed. Since this operation is repeated sequentially, continuous write data can be continuously written into the RAM 14 without considering the address at all by automatically updating the write address.

When the write is completed and the read permission signal SR is input manually, the read mode is set, and the address control circuit 13 selects the first or second read address to enable data read. The mode of the memory circuit is confirmed by the write/read mode signal W/H output from the control circuit 11, and by selectively inputting the start address Aa or Ab, the first and second read address automatic update circuits 17 The start address is set at ゜18. However, as shown in FIG. 2, the starting address is based on the address next to the last written address.

Now, if the start address Aa is entered manually, the address control circuit I3 selects the set read address and sends it to the RAM 14. Therefore, the data in the area designated by the read address is read from the RAM 14, held in the holding circuit 21, and pre-read. After setting this start address, data is read. First, when reading is performed, the data held in the holding circuit 21 is read out from the data output port. When this reading is finished,
The read address is determined by the first read address automatic update circuit 1.
7 and input to the RAM 14 through the address control circuit 13. Therefore, the next data is read from the RAM 14. At this time, the data held in the holding circuit 19 has already been read, and the new read data is held in the holding circuit 19.

Since this operation is repeated sequentially, the RAM 14 is automatically updated without considering the address at all.
The continuous data DRa written in the RAM 14 can be continuously read out at high speed without worrying about the access time of the RAM 14. This is exactly the same when the start address Ab is input, and by automatically updating the read address, the continuous data DRb written in the RAM 14 can be read out continuously without considering all addresses.

FIG. 3(a) shows a write and read timing diagram of a conventional re-readable memory circuit. In this circuit, each setting of the write address At-A3 is followed by the setting of each write period Wl-W5. , after the mode switching period C ends, readout periods R1 to R5 are set, respectively, following the setting of read addresses A1 to A5. On the other hand, in the FIFO memory circuit of the above embodiment,
), the write periods Wl-W5 become continuous due to the automatic update of the write address, and after the mode period C and the start address setting period A have elapsed, the read periods R1-R5 become continuous due to the automatic update of the read address. That is, continuous data writing and reading in the FIFO memory circuit of this embodiment is executed at extremely high speed compared to the conventional circuit.

Furthermore, since this circuit has two systems of read ports, for example, as shown in FIG. , RAMI4 can be accessed using the address next to the last write address as the reference for the read address, so by setting the start address to "0" and "64", it is possible to access RAMI4 from address "0" or "64" independently from the two ports. Continuous data can be read from ``.

Therefore, when the FIFO memory circuit with the above configuration is used between microprocessors capable of high-speed operation, the reading and writing time of continuous data can be executed in the minimum operation unit of the microprocessor, so that a large amount of continuous data can be processed. Since it can be transferred at high speed and can be read again, it also has a data storage function and can read data independently and continuously from any address of a series of continuous data from two ports. It is extremely effective and can fully utilize the capabilities of a high-speed microprocessor that processes signals in real time. Furthermore, since it has a plurality of read paths, it is possible to read continuous data independently by setting the respective start addresses.

In the above embodiment, there is one write data input port and two read data output ports, but it goes without saying that the number of each port may be increased as necessary.

[Effects of the Invention] As described above, according to the present invention, continuous data reading and writing time can be executed in the minimum operation unit of the microprocessor, and the ability of the microprocessor to perform signal processing in real time can be fully utilized. It is possible to provide a FIFO memory circuit that can take full advantage of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing an embodiment of the FIFO memory circuit according to the present invention, FIG. 2 is a diagram for explaining the start address setting of the embodiment, and FIG. 3 is the operation timing of the embodiment. FIG. 3 is a timing diagram showing a comparison between the conventional circuit and the conventional circuit. 11... Control circuit, 12... Write address automatic update circuit, 13... Address control circuit, 14... RA
M. 15... Buffer circuit, 16... Write data input port, 17, 18... Read address automatic update circuit, 19.20... Holding circuit, 21.22... Read data output port, Sw.・Write permission signal, Sn・
...Read permission signal, R...Reset signal, Aa, A
b...Start address, DW...Write data, DR
a, DRb...read data, W/R...write/read mode signal. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A memory that can write input data into an area specified by a write address and read data from an area specified by a read address, and an automatic write address that automatically updates the write address after writing the previous data. an update circuit, a plurality of read address automatic update circuits that automatically update after completion of reading previous data based on an externally given start address, the write address automatic update circuit and a plurality of read address automatic update circuits; an address control circuit that selectively derives output addresses to the memory; a plurality of holding circuits that hold data read from the memory in accordance with selections of the plurality of automatic read address update circuits; A FIFO memory circuit comprising a write/read switching means for switching a write operation and a read operation of the circuit according to a permission signal commanded from the outside.