JPH0199217A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0199217A JPH0199217A JP25694787A JP25694787A JPH0199217A JP H0199217 A JPH0199217 A JP H0199217A JP 25694787 A JP25694787 A JP 25694787A JP 25694787 A JP25694787 A JP 25694787A JP H0199217 A JPH0199217 A JP H0199217A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode film
- solder
- plating
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910000679 solder Inorganic materials 0.000 claims abstract description 27
- 238000007747 plating Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000010953 base metal Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 description 12
- 238000005476 soldering Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体基板表面にオーム性電極を育し、組立
ての際の電極と導体の接続にはんだ付けが使用される半
導体装置の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for manufacturing a semiconductor device in which ohmic electrodes are grown on the surface of a semiconductor substrate and soldering is used to connect the electrodes and conductors during assembly. Regarding.
不純物拡散等の工程によってＰＮ接合などを形成したシ
リコン基板表面にオーム性接触をする電極膜を形成する
には、例えばニッケルめっきなどを施す、しかしこのよ
うな電極膜にリード線等をはんだ付けするときには、良
好なはんだ付は性が得られない、これは電極膜を設けた
シリコン基板あるいはシリコンチップを大気中に放置す
ることによって電極膜表面が酸化されるためである。そ
こで、従来は電極膜上に金めつきを施していた。To form an electrode film that makes ohmic contact on the surface of a silicon substrate on which a PN junction or the like is formed by a process such as impurity diffusion, nickel plating is applied, for example, but lead wires, etc. must be soldered to such an electrode film. In some cases, good soldering properties cannot be obtained because the surface of the electrode film is oxidized by leaving the silicon substrate or silicon chip provided with the electrode film in the atmosphere. Therefore, conventionally, gold plating was applied on the electrode film.
金は貴金属であるため、金めつき膜表面は酸化されに（
（、またはんだ付けの際会がはんだ層中に拡散してはん
だ中のすずと金との合金層が形成されるためはんだ性が
良好となる０以上の理由から卑金属電極膜上のめっきと
しては金が最適であった。Since gold is a precious metal, the surface of the gold-plated film will not be oxidized (
(Also, during soldering, the solder is diffused into the solder layer and an alloy layer of tin and gold in the solder is formed, resulting in good solderability.For the reasons above, it is not suitable for plating on base metal electrode films.) Gold was the best choice.
しかし、エレクトロニ多ス機器の需要増大に伴い、半導
体装置の低価格化に対する要求はきわめて厳しい、そこ
で金のような高価な材料を用いることは半導体装置のコ
スト低減に大きな障害となっていた。However, with the increasing demand for electronic devices, the demand for lower prices for semiconductor devices has become extremely strict, and the use of expensive materials such as gold has been a major obstacle to reducing the cost of semiconductor devices.
本発明の目的は、上記の障害を除き、半導体装置のコス
ト低減を可能にするため、金を使用しないで卑金属電極
に対する組立ての際のはんだ付けを容易にする半導体装
置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned obstacles and facilitates soldering during assembly to base metal electrodes without using gold, in order to reduce the cost of the semiconductor device. It is in.
上記の目的を達成するために、本発明の方法は、半導体
基板上の所定の領域上にその領域とオーム性接触をする
電極膜を卑金属により形成したのち、その電極膜上に２
〜５−の厚さにはんだをめっきするものとする。In order to achieve the above object, the method of the present invention involves forming an electrode film made of a base metal on a predetermined region on a semiconductor substrate and making ohmic contact with the region, and then disposing two electrode films on the electrode film.
The solder shall be plated to a thickness of ~5-.
電極膜上にはんだをめっきすることにより、はんだ膜が
電極膜の表面を覆うため電極膜の卑金属の酸化はおこら
ず、電極に対する導体の接続作業もはんだめっき上への
はんだ付けによって極めて容易になる。By plating solder on the electrode film, the solder film covers the surface of the electrode film, so oxidation of the base metal in the electrode film does not occur, and the work of connecting the conductor to the electrode is extremely easy by soldering on the solder plating. .
第１図はダイオード製造工程中のシリコン基板を示し、
Ｎ型基板１に酸化膜３をマスクにして不純物拡散アノー
ド層としてのＰ゛層２多数拡散したものである。１＆板
１の下面にもＮ°層１１が形成されている。２９層２お
よびＮ”１ｉｌｌにオーム性接触が得られるようにＮｉ
めっきにより電極膜４を被着する。この電極膜４上に膜
厚２〜５−のはんだ（Ｐｂ−５ｒ＋合金）めっきを施す
、このはんだめっき膜５の膜厚が２μより薄いとピンホ
ールの問題があり電極膜４が酸化すると考えられ、実験
ではばんだ膜厚が１−であると組立後の素子の引張り強
度が若干低下するという結果であった。またはんだ膜厚
が５μ以上になると次工程でシリコン基板をチップ状に
切断する際、はんだめっき層がやわらかいため切断がで
きないという問題となる。Figure 1 shows a silicon substrate during the diode manufacturing process.
A large number of P' layers 2 serving as impurity diffusion anode layers are diffused into an N-type substrate 1 using an oxide film 3 as a mask. An N° layer 11 is also formed on the lower surface of the plate 1. 29 layer 2 and N”1ill to obtain ohmic contact.
Electrode film 4 is deposited by plating. Solder (Pb-5r+alloy) plating with a thickness of 2 to 5 is applied to the electrode film 4. It is believed that if the thickness of the solder plating film 5 is thinner than 2μ, there will be a problem with pinholes and the electrode film 4 will be oxidized. In experiments, it was found that when the thickness of the solder film was 1-, the tensile strength of the assembled device was slightly lowered. If the thickness of the solder film exceeds 5 μm, a problem arises in that when cutting the silicon substrate into chips in the next step, the solder plating layer is too soft to cut.
よってはんだめっき膜５の膜厚は２〜５−が最適となる
。なお、電極膜４上にはんだを付ける手段としては予備
はんだがあるが、はんだ膜厚のばらつきが大きく、膜厚
の制御もできないので前述のような膜厚範囲を確保でき
ないため適用できない。Therefore, the optimum thickness of the solder plating film 5 is 2 to 5 -. Preliminary soldering is a means of applying solder on the electrode film 4, but it cannot be applied because the solder film thickness varies widely and cannot be controlled, making it impossible to secure the film thickness range as described above.
はんだめっき膜の組成すなわちＰｂ／Ｓｎ比は組立工程
で使用するはんだの組成と同じであることが望ましい、
またこのはんだめっきの方法は電解めっき、無電解めっ
きのいずれでもよい。It is desirable that the composition of the solder plating film, that is, the Pb/Sn ratio, be the same as the composition of the solder used in the assembly process.
The solder plating method may be either electrolytic plating or electroless plating.
このようにして得られたシリコン基板１ははんだ膜５に
よって電極膜４が覆われているため、電極膜表面が酸化
されることがなく、次の組立工程で接続不良がでること
はない、またはんだ膜５の表面は長期間大気中に放置し
ても次の組立工程においてはんだ付は性が損なわれるこ
とはない、これに関する実験として、はんだめっき後１
週間。Since the electrode film 4 of the silicon substrate 1 obtained in this way is covered with the solder film 5, the electrode film surface is not oxidized, and connection failures will not occur in the next assembly process. Even if the surface of the solder film 5 is left in the atmosphere for a long period of time, the soldering properties will not be impaired in the next assembly process.
week.
１ケ月、３ケ月と放置したものについて組立工程でのは
んだ付は性１組立後の引張り強度を評価したところ、ど
れも有意差はないという結果が得られた。さらに、組立
工程における導線、導体、プリント板とのはんだ付けは
、はんだどうしの接着となるため、はんだ付は性は金め
つきを施したものと同等かあるいはそれ以上に良好とな
る。When we evaluated the tensile strength after assembly for those that had been left alone for one month and three months, we found that there was no significant difference in soldering during the assembly process. Furthermore, since soldering between conductive wires, conductors, and printed circuit boards during the assembly process involves bonding the solders together, the soldering properties are as good as or better than those with gold plating.
本発明によれば、半導体基板の導電型領域にオーム性接
触する電極膜を卑金属で形成した際、その電極膜の表面
の酸化を防止し、組立工程での導体との接続のためのは
んだ付は性を向上させるため、電極膜上に膜厚２〜５μ
ｍのはんだめっき膜を設けることを含む製造方法により
、従来電極膜酸化防止のために用いた金の代わりに安価
なはんだを使用するため半導体装置の製造コストを大幅
に低減することができる。According to the present invention, when an electrode film that makes ohmic contact with a conductivity type region of a semiconductor substrate is formed of a base metal, oxidation of the surface of the electrode film is prevented, and soldering for connection with a conductor in the assembly process is prevented. To improve the properties, a film thickness of 2 to 5 μm is applied on the electrode film.
By the manufacturing method including providing a solder plating film of m, inexpensive solder is used instead of gold, which is conventionally used to prevent electrode film oxidation, and thus the manufacturing cost of the semiconductor device can be significantly reduced.
第１図は本発明の一実施例の工程中におけるシリコン基
板の断面図である。
１：シリコン基板、２ニアノ一ド層、４１１めっき膜、
５：はんだめっき膜。FIG. 1 is a sectional view of a silicon substrate during the process of an embodiment of the present invention. 1: Silicon substrate, 2 near anode layer, 411 plating film,
5: Solder plating film.
Claims (1)
触をする電極膜を卑金属により形成したのち、該電極膜
上に２〜５μｍの厚さにはんだめっきすることを特徴と
する半導体装置の製造方法。1) A semiconductor device characterized by forming an electrode film made of a base metal on a predetermined region on a semiconductor substrate and making ohmic contact with the region, and then plating the electrode film with solder to a thickness of 2 to 5 μm. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25694787A JPH0199217A (en) | 1987-10-12 | 1987-10-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25694787A JPH0199217A (en) | 1987-10-12 | 1987-10-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0199217A true JPH0199217A (en) | 1989-04-18 |
Family
ID=17299571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25694787A Pending JPH0199217A (en) | 1987-10-12 | 1987-10-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0199217A (en) |
-
1987
- 1987-10-12 JP JP25694787A patent/JPH0199217A/en active Pending
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