JPH0195535A - Wiring device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain optimum electric characteristics by calculating and specifying the allowable delay time by a circuit designer and by connecting wire within the time range. CONSTITUTION:Resistance value R and value C of load capacity 7, 8 are obtained according to the necessary length and width of wiring 3, 4 which are determined by a conventional wiring process. If the product of these values is not within the range of the specified delay time, the wiring width or the wiring length are changed to control the product within the specified range. If the product is within the range, the wiring width and the wiring length are changed to get the optimum electric characteristics within the range. In this way, wiring circuit considering electric characteristics which are calculated manually in existing techniques can be made automatically and a precision wiring device for semiconductor integrated circuit can be provided at extremely low costs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring bag WjK for a semiconductor integrated circuit.

[Conventional technology]

2. Description of the Related Art Conventional wiring devices for semiconductor integrated circuits include automatic wiring devices shown in FIGS. 2 and 3, for example.

Figure 3 is based on the channel wiring method, and Figure 4 is based on the line segment search method or maze method. In conventional wiring devices, it is difficult to weight each signal and to determine the delay value. Instead, the only thing that was being evaluated was how to minimize the area for each signal.

[Problem that the invention seeks to solve]

Conventional wiring devices for semiconductor integrated circuits can only use wiring of uniform width, so even if there is extra space, there are problems such as the inability to expand the wiring to provide a larger current capacity.

This invention was made to solve the above-mentioned problems, and the circuit designer calculates and specifies the allowable delay time, and connects the wires within that range to achieve the optimum electrical characteristics of the semiconductor. The purpose is to obtain integrated circuits.

[Means for solving problems]

The wiring device for semiconductor integrated circuits according to the present invention has the ability to maintain the wiring resistance within the specified allowable delay time range by the time constant T=Rno (T: delay time, R: resistance value, C: load capacitance value). The value (c) and the load capacitance value (c) are obtained from wiring data, and it is checked whether the product of these is within a specified delay time range. For wiring devices for integrated circuits, the wiring length, wiring width, and resistance value (0) are determined using the usual wiring methods (channel router, switch box router, maze method, etc.). If the product of delay time is not within the specified delay time range, suppress it within the specified range by changing the wiring width or wiring length, and if it is within the specified range, optimize the electrical characteristics within that range. (Maximum charge amount.

The wiring width and wiring length are changed to obtain the minimum resistance value.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) and +2) are semiconductor elements, and (3)
.

(4) is the wiring connecting the semiconductor elements (1) and +2), (5) and (6) are the resistance values of the wiring (3) and (4), and (7) and (8) are the wiring (3) , (4) indicates the capacitance value.

FIG. 2 is a flowchart showing the operation of the wiring device of the present invention.

As shown in the flowchart shown in Fig. 2, when determining the wiring (3) and (4) between the semiconductor elements (1) and +2), first, the delay time between the semiconductor elements (1) and +2) is determined. Determine if there is a specification.

If not, determine whether the minimum delay specification is sufficient and select NO.
In this case, use the minimum wiring width for wiring.

In addition, if YES, the wiring will have the shortest route and minimum capacitance value,
Switch to the wiring wire with the lowest resistance value and perform wiring.

In the case of delay time specification 6D, the wiring is connected with the minimum width, and the resistance value (supplement, capacitance value) within the minimum width wiring is calculated.
Find 0).

If this resistance value (6) and capacitance value (0) are smaller than or equal to the specified delay value, the minimum delay specified Y
As in the case of ES, wiring is performed using the shortest route and wiring wires with minimum capacitance and minimum resistance values.

If the resistance value (or capacitance value (C)) is larger than the specified delay value, increase the wiring width as much as possible and set the delay value T≧
Set so that it is within the range of R@O.

In this way, the wiring of the semiconductor integrated circuit is successively performed.

In the above embodiment, the wiring between semiconductor elements (1) and +2> was explained as an example of wiring (3) and (4), but it goes without saying that it can also be applied to printed circuit board wiring for board design. Nor.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to automatically create a wiring circuit that takes into account electrical characteristics, which had conventionally been calculated manually, and has the effect of providing a highly accurate wiring device for semiconductor integrated circuits at an extremely low cost. .

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a simplified plan view and an equivalent circuit diagram showing wiring of a semiconductor element showing an embodiment of the present invention;
FIG. 2 is a flowchart of the semiconductor integrated circuit wiring device of the present invention, FIG. 3 is a plan view showing wiring by a conventional semiconductor integrated circuit wiring device, and FIG. 4 is a plan view showing another conventional embodiment. In the figure, S73゜(1), (21 is the semiconductor element, (3), (4) are the wiring, (5), (6)
represents the resistance value, and (7) and (8) represent the capacitance value. In addition, the same symbols in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] In order to give an allowable delay time to each signal of a semiconductor integrated circuit, the resistance value and load capacitance value are automatically specified to suppress the delay time and reduce the wiring width and length within that range. A wiring device for semiconductor integrated circuits, characterized in that wiring is set to an optimum value.