JPH0748521B2 - Wiring method of integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method for an integrated circuit, and more particularly to a wiring area for dividing an area on a chip into a plurality of areas for wiring in an automatic layout of the integrated circuit. The present invention relates to a method of dividing a partition after inserting a pseudo block.

[Conventional technology]

When obtaining the schematic route of the wiring, the wiring graph shown in FIG. 2A showing the adjacency relationship of the wiring regions on the chip is created.
The vertices 8 of this graph indicate the intersections of the channel regions, and the vertices 9 correspond to some terminals of the blocks facing the channel regions. Each side of the graph corresponds to a channel region or a region on the block, and each side has a width and a length of the channel region. On this wiring graph, an optimum rough route is obtained according to the connection request of each wiring. In the example of FIG. 2A, the block Y is divided into two to finely express the wiring graph.

FIG. 2B is an example in which a schematic route of connection between the terminal x of the block X and the terminal y of the block Y is obtained. FIG. 2 (c) shows that the wiring was faithfully performed based on this schematic route. Since these areas purposely use the regions S1 and S2, the wiring results are circumvented. FIG. 2 (d) is an example of a desirable wiring result for this connection.
This does not use the rough path and part (S1, S2 area). Further, in some cases, as shown in FIG. 2 (e), when obtaining the optimum rough route, it is possible to obtain a route avoiding the area S2 unnecessarily.

In the prior art, if there is a difference equal to or more than the value at the block position on each side of the channel region like the region S, the wiring graph cannot express the necessary wiring result, and the chip size is small as a result of wiring. In some cases, it was not possible to request a rough route that would be short and long.

[Problems to be Solved by the Invention]

The above-mentioned conventional wiring graph creating method is the most suitable on the wiring graph because the necessary wiring result cannot be expressed when the difference between the positions of both ends or one side of the block row on each side of the channel region exceeds a certain value. There is a drawback that the rough route is not optimal in actual wiring.

[Means for Solving the Problems]

According to the wiring method of the present invention, as shown in FIG. 1, there is a difference in the positions of the block rows above and below (or to the left and right) of one or more connected horizontal or vertical channel regions. When there is more than a certain value, a pseudo block (which has no connection with wiring) is inserted in the empty area outside the inner block row to create a wiring graph.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

First, an embodiment of the present invention will be described with reference to FIG. Third
In FIG. 6A, focusing on the horizontal channel between the blocks X and Y, which is a part of the chip for wiring, the left end of the lower block X is inside the left end of the upper block Y. Pseudo block 2 in the empty area S
, And a wiring graph is prepared by the conventional method to obtain FIG. 3 (b). 12 in FIG. 3 (b) is the terminal x of the block X
And (c) is one of the schematic routes of the terminal y of the block Y, and wiring is performed based on this, and the wiring result shown in FIG.

By inserting a pseudo block, it is possible to create a wiring graph that can express the required wiring result, and the rough route can be evaluated accurately.

FIG. 4 shows another embodiment of the present invention. In this example, two types of wiring graphs shown in FIG. 4 (b) or FIG. 4 (c) can be created by the conventional method for the given block arrangement shown in FIG. 4 (a). Adopt one. In the wiring graph of FIG. 4 (b), the general route of terminals x ₁ and z is as shown by 15 in FIG. 4 (e), and in the wiring graph of FIG. 4 (c), the general route of y of the terminal x ₂ is The pattern turns around like 16 in FIG. 4 (f). According to the invention, a vertical channel (or block
Paying attention to the horizontal channel between ZY and block X, the pseudo block 2 is inserted in the empty area S below the block Z (or the empty area S on the left side of the block X).
The wiring graph of FIG. 4 (d) is obtained, and the 16 and 17 non-circumvented rough routes shown in FIG. 4 (g) can be expressed for both, and the rough route can be accurately evaluated.

〔The invention's effect〕

As described above, according to the present invention, it is possible to create a wiring graph capable of expressing a required wiring result by inserting a pseudo block in a large vacant area on each side of the connected channel area. The path can be evaluated accurately, which has the effect of reducing the chip size and the wiring length.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention, showing a part of a chip, FIGS. 2 (a) to 2 (e) are diagrams for explaining a conventional method, and FIG.
(A)-(c) is a figure explaining one Example of this invention, FIGS. 4 (a)-(g) is a figure for explaining another Example of this invention. 1 ... Block, 2 ... Inserted pseudo block, 3 ...
... Empty area, 4 ... Vertical channel area, 5 ... Horizontal channel area, 6 ... Connected channel area, 7 ... Block terminal, 8 ... Vertex indicating intersection of channel areas, 9 ... Terminal Representative vertices, 10 ... edges corresponding to the channel area, 11 ... edges corresponding to the area on the block, 12
…… Short path, 13 …… Wiring, 14 …… Through hole, 15…
… A general route connecting terminals x ₁ and y, 16 …… A general route connecting terminals x ₂ and z.

Claims (1)

[Claims] 1. Regarding automatic layout of an integrated circuit using an electronic computer, first, for a channel region, which is a region sandwiched between two blocks, and a region on each block, a set of regions through which each wiring passes is first defined. First, in the two-step wiring method in which the wiring is performed in each region based on the schematic route of each wiring, which is a set of the channel region through which each wiring passes and the region on the block, and the entire wiring is performed, one or When there is a difference in the position of the block rows above and below or to the left or right of the horizontal or vertical channel area that is connected two or more times, when there is a given value or more, a pseudo pattern is created in the empty area outside the inner block row. Method of integrated circuit characterized by inserting general blocks to obtain rough path