JPH02142159A - Method of wiring integrated circuit - Google Patents

Abstract

PURPOSE:To form a wiring graph by which a required wiring result can be expressed and to make it possible to evaluate approximate paths accurately by inserting a dummy block in a large vacant region at each end of connected channel regions. CONSTITUTION:When the difference between the positions of the ends of block lines at the upper and lower (or right and left) parts of one or two or more horizontal or vertical connected channel regions exceeds a given value, a dummy block (not connected to wirings) is inserted into a vacant region at the outside of the inner block line. Then a wiring graph is formed. The left end of the lower block X is inner than the left end of the upper block Y. Therefore, the dummy block 2 is inserted into the vacant region S. The wiring graph is formed by a conventional method. When wiring is performed along one approximate path 12 between a terminal (x) of the block X and a terminal (y) of the block Y, the wiring result without detour is obtained. When the dummy block is inserted, the approximate path can be accurately evaluated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a wiring method for integrated circuits, and in particular to a wiring area when an area on a chip is divided into a plurality of areas and wiring is performed in automatic layout of an integrated circuit. This paper relates to a method in which division is performed after inserting pseudo blocks.

[Conventional technology]

When determining the approximate route of the wiring, a wiring graph shown in FIG. 2(a) showing the adjacency relationship of the wiring areas on the chip is created.

The vertices 8 of this graph indicate the intersections of the channel regions, and the vertices 9 correspond to some terminals of the blocks facing the channel regions. Each side of the graph corresponds to a channel area or an area on a block, and each side has the width and length of the channel area. On this wiring graph, an optimal approximate route is determined according to the connection request for each wiring. In the example of FIG. 2(a), the wiring graph is expressed finely by dividing the block Y into two.

FIG. 2(b) is an example in which a schematic route for connecting terminal X of block X and terminal y of block Y is determined.

The wiring shown in FIG. 2(c) is performed faithfully based on this rough route, but since these areas are intentionally used in areas S1 and S2, the wiring results in detours. FIG. 2(d) is an example of the desired wiring result for this connection, which does not use the general route and a portion (area S1, S2). In some cases, Figure 2 (
As shown in e), it is unnecessary when determining the optimal rough route82
You may be able to obtain something that avoids this area.

In the conventional technology, if there is a difference of more than a value at the edge of the block on each side of the channel region, as in region S, the wiring graph cannot express the necessary wiring results, resulting in a small chip size and poor wiring. In some cases, it was not possible to find a rough route with a short length.

[Problem to be solved by the invention]

The conventional wiring graph creation method described above was not optimal on the wiring graph because it could not express the necessary wiring results when the difference between the positions of both ends or one of the block rows on each side of the channel region exceeded a certain value. There is a drawback that the approximate route is not optimal in actual wiring.

[Means to solve the problem]

In the wiring method of the present invention, as shown in FIG. If the value is greater than or equal to the specified value, a pseudo block (which has no connection to the wire) is inserted into the empty area outside the inner block row to create a wire graph.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

First, one embodiment of the present invention will be described with reference to FIG. Third
If we pay attention to the horizontal channel sandwiched between blocks X and Y, which is a part of the chip where wiring is performed, in Figure (a), we can see that the left end of the lower block X is on the inside compared to the left end of the upper block Y. Pseudo block 2 in empty area S
, and create a wiring graph using the conventional method as shown in Figure 3 (b).
).

12 in the 311th ffl(b) is one of the approximate routes between the terminal X of the block

By inserting pseudo blocks, it is possible to create a wiring graph that can express the necessary wiring results, and the rough route can be evaluated accurately.

FIG. 4 shows another embodiment of the invention. In this example, for the given block arrangement shown in Fig. 4(a), two types of wiring graphs, shown in Fig. 4(b) or Fig. 4(c), can be created using the conventional method, and the wiring program is Adopt one. In the wiring graph of FIG. 4(b), the approximate path of terminals x1 and 2 is 15 in FIG. 4(e), and in the wiring graph of FIG. figure(")
It becomes a twisted pattern like 16. According to the present invention, by focusing on the vertical channel between block 2 and block X (or the horizontal channel between block ZY and block Since pseudo block 2 is inserted into S), the wiring graph shown in Figure 4(d) is obtained, and the general route 16.17 without detours shown in Figure 4(g) is expressed for both. It is possible to accurately evaluate the rough route.

〔Effect of the invention〕

As explained above, the present invention can create a wiring graph that can express the necessary wiring results by inserting pseudo blocks into large empty areas at the edges of each side of connected channel regions. Path evaluation can be performed accurately, which has the effect of reducing chip size and wiring length.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining the present invention and shows a part of the chip, Figures 2 (a) to (e) are diagrams for explaining the conventional method, and Figures 3 (a) to (c) are diagrams for explaining the present invention. Diagram 4 for explaining one embodiment
Figures (a) to (g) are diagrams for explaining other embodiments of the present invention. 1...Block, 2...Inserted pseudo plot, 3...Empty area, 4...
- Vertical channel region, 5... Horizontal channel region, 6... Continuous channel region, 7...
・Terminal of the block, 8... Vertex indicating the intersection of channel areas, 9... Vertex representing the terminal,
10... Side corresponding to the channel area, 11...
...Side corresponding to the area on the block, 12...
...Rough route, 13...Wiring, 14...
-Through hole, 15... Schematic route connecting terminals x1 and y, 16... Schematic route connecting terminals X2 and 2. Agent Patent Attorney Susumu Uchihara (C) (ct) 茅cbn竿FURO TSUK1 NO・()AF4NOI, 4￥KAI55; -) (C) (ct) (g) Seat bar

Claims (1)

[Claims] Regarding automatic layout of integrated circuits using electronic computers,
For the channel region, which is the region between two blocks, and the region on each block, first find the set of regions that each wire passes through, and then calculate the channel region and the region on the block through which each wire passes. In a two-step wiring method that performs wiring in each area and then the entire wiring based on the general route of each wiring as a set, blocks located above, below, or to the left or right of one or more connected horizontal or vertical channel areas. An integrated circuit characterized in that when the difference in the position of the edge of a column is greater than or equal to a given value, a pseudo block is inserted into a vacant area outside the inner block column to find an approximate route. wiring method