JPH0193939A - Signal detector - Google Patents

Abstract

PURPOSE:To detect a specific bit, which is inserted to every n-th bit, with a small-scale circuit by detecting the specific bit included in one arbitrary sequence in P number of sequences and deciding all specific bits included in p sequences. CONSTITUTION:When detecting specific bits from the signal where the specific bit is inserted to every n-th bit, a serial-parallel converting means 2 converts the signal to p signal sequences by 1:p serial-parallel conversion so that the number of signals is the least common multiple of (n) and (p). A detecting means 5 detects positions of specific bits included in arbitrary one of p signal sequences to detect positions of all specific bits. Thus, the operation margin is extended without increasing the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for detecting a specific bit in a digital signal, and more particularly to a method for detecting the position of a specific bit from a signal into which the specific bit has been inserted.

(Prior art) Conventionally, when detecting and determining a specific bit from a high-speed signal sequence in which a specific bit is inserted every n bits, most of the detection circuit is Requires high speed operation.

Due to circuit operation, there may be cases where the operating margin is not sufficient.

In order to solve this problem, a method is generally known in which one sequence of signals is decomposed into a plurality of parallel signals by serial-to-parallel conversion, and specific bits are detected at a low speed. In this case, although the operating margin of one circuit increases, the disadvantage is that the scale of two circuits also increases.

FIG. 5 is an explanatory diagram showing a signal sequence in which a specific bit (indicated by ■ here) is inserted every nine bits, and FIG. 6 is a block diagram showing a signal detection device according to the prior art.

In FIG. 6, 62 is a serial/parallel conversion circuit, 66 to 6B are detection circuits, and 72 is a determination circuit.

When the specific bit (2) inserted into the input terminal 61 of the serial-to-parallel conversion circuit 62 is input, the three series outputs of the serial-to-parallel conversion circuit 62 are sent to signal lines 63 to 65, and become signals CHI to CH3. The signals on the distributed nine signal lines 63 to 65 are
They are shown in FIGS. 7 to 9, respectively. These signals exist corresponding to the fact that there are three initial phases of the 1/3 frequency division counter built into the serial/parallel conversion circuit 62.

No matter which of the signal lines 63 to 65 a specific bit is allocated to, in order to enable detection, detection circuits 66 to 68 are prepared for each signal, and from the detection circuits 66 to 68 to the signal line 69, detection circuits 66 to 68 are prepared for each signal.
Using the detection information above .about.71, the 1 determination circuit T2 determines the content of the specific bit.

(Problems to be Solved by the Invention) In the above-mentioned conventional technology, when detecting and determining a specific bit from a high-speed signal sequence in which a specific bit is inserted every n bits, signal processing is performed on one sequence. However, since most of the detection circuitry requires high-speed operation, it has the disadvantage of requiring the use of expensive elements.

In addition, since there are cases where sufficient operation merge/ is not obtained, if a serial/parallel conversion circuit is used to decompose the signals into multiple parallel signals and detect specific bits at low speed, inexpensive elements can be used, which reduces the operation margin. However, the drawback is that an increase in the scale of two circuits is unavoidable.

An object of the present invention is to perform serial-to-parallel conversion of a series signal in which a specific bit is inserted every n bits.

A 1-to-p serial-parallel conversion is performed, which is the least common multiple of n and p, and a specific bit included in any one of the p sequences is detected, and all specific bits that are t-z in the p sequence are It is an object of the present invention to provide a signal detection device configured to eliminate the above-mentioned drawbacks and increase the operating margin without increasing the scale of one circuit.

(Means for solving problems) The signal detection device according to the present invention includes serial-to-parallel conversion means.

Detection means.

When detecting a specific bit from a signal in which a specific bit is inserted every n bits, the serial/parallel conversion means converts the signal into n
This is for converting into a p-series signal sequence by 1:p serial-parallel conversion so that it becomes the least common multiple of and p.

The detection means is for detecting a specific bit position included in any one of the p-sequence signal sequences, and detecting all specific bit positions.

(Example) Next, one embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is an explanatory diagram showing a signal sequence in which a specific bit (indicated by ``9'' here) is inserted every nine bits, and FIG. 6 is a block diagram showing a signal detection device according to the prior art.

In FIG. 2, 2 is a serial-to-parallel conversion circuit, 5 is a detection circuit,
This is a 6μ judgment circuit.

The signal series shown in FIG. 1 is input to the input terminal 1 of the serial-to-parallel conversion circuit 2 shown in FIG. The serial-to-parallel conversion circuit 2 must have a 1:2 serial-to-parallel conversion function.

That is, one series of signals in which specific bits are inserted every n=9 bits must be decomposed into parallel signals by a 1:p serial-to-parallel conversion circuit such that the signal is the least common multiple of n and p. Therefore, p must be 2.

The two series of outputs sent from the serial/parallel conversion circuit 2 to the signal line 3.4 become CHI and CH2. There are two types of signals to be distributed, as shown in FIGS. 3 and 4, whereas there are two initial phases of the 1/2 frequency divider built in the serial-to-parallel conversion circuit 2.

If the relationship between n and p is selected as described above, specific bits are inserted every 9 bits into CHI and CH2 in both cases of FIGS. 3 and 4. Furthermore, CH
The relative phase relationship between the specific bits of I and CH2 is the same in both FIGS. 3 and 4. Therefore, for example, if a specific bit included in CH1 can be detected by the detection circuit 5, the specific bit will definitely exist in CH2 after 4 bits, and the detection information will be sent from the detection circuit 5 to the determination circuit 6 via the signal line T. If you transmit.

It becomes possible to determine specific bits allocated to CHI and CH2.

In this way, according to the present invention, there is no need to provide a detection circuit for each of CHI and CH2.

(Effects of the Invention) As explained above, the present invention provides the following advantages when performing serial-to-parallel conversion of a single series signal in which a specific bit is inserted every n bits.
A one-to-p serial-parallel conversion is performed, which is the least common multiple of n and p, and a specific bit included in any one of the p sequences is detected.

Determining all specific bits included in the p sequence i
'c has the effect that specific bits inserted every n bits can be detected with a small-scale circuit.

[Brief explanation of the drawing]

FIGS. 1 and 5 are explanatory diagrams showing signal sequences in which specific bits are inserted every nine pits, respectively. FIG. 2 is a block diagram showing an embodiment of a signal detection device according to the present invention. 3 and 4 are explanatory diagrams showing output signals of the serial-to-parallel conversion circuit of FIG. 2, respectively. FIG. 6 is a block diagram showing an example of a signal detection device according to the prior art. @Figures 7 to 9 are explanatory diagrams showing output signals of the serial-to-parallel conversion circuit shown in FIG. 6, respectively. 2.62...Serial-to-parallel conversion circuit 5.66-68...Detection circuit 6.72...Judgment circuit 1.61...Terminal 3, 4. 7. 63～65.69～71
・ ・ ・ Igo line patent applicant NEC Corporation agent Patent attorney Jusai Inoro 1 Figure 1 234 5678 No. 12345678 Pa 125 years old 2 years old 3 Figure 4th CHI 24681357 Oki 24681357 C
Hz 1357'82468 l 357. ! 24
68 Figure 5 125456711! , scale 91011', 21314
1516, 1718 ・O Figure 6 O Figure 7 O Figure 8 Figure 9

Claims (1)

[Claims] When detecting a specific bit from a signal in which a specific bit is inserted every n bits, the signal is converted into a p-series signal series by one-to-p serial-parallel conversion such that the signal becomes the least common multiple of n and p. It is configured to include a serial-to-parallel conversion means and a detection means for detecting a specific bit position included in any one of the p-sequence signal sequences and detecting all the specific bit positions. Characteristic signal detection device.