JPH0193228A - マルチフレーム同期回路用試験回路 - Google Patents
マルチフレーム同期回路用試験回路Info
- Publication number
- JPH0193228A JPH0193228A JP24986487A JP24986487A JPH0193228A JP H0193228 A JPH0193228 A JP H0193228A JP 24986487 A JP24986487 A JP 24986487A JP 24986487 A JP24986487 A JP 24986487A JP H0193228 A JPH0193228 A JP H0193228A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pseudo
- tnr2
- test
- tnr1
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 45
- 230000001360 synchronised effect Effects 0.000 title claims description 3
- 230000005540 biological transmission Effects 0.000 claims description 13
- 238000012544 monitoring process Methods 0.000 claims description 7
- 238000011144 upstream manufacturing Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 21
- 238000010586 diagram Methods 0.000 description 6
- 238000003780 insertion Methods 0.000 description 4
- 230000037431 insertion Effects 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 101000739577 Homo sapiens Selenocysteine-specific elongation factor Proteins 0.000 description 2
- 102100037498 Selenocysteine-specific elongation factor Human genes 0.000 description 2
- 241000613130 Tima Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Time-Division Multiplex Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24986487A JPH0193228A (ja) | 1987-10-05 | 1987-10-05 | マルチフレーム同期回路用試験回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24986487A JPH0193228A (ja) | 1987-10-05 | 1987-10-05 | マルチフレーム同期回路用試験回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0193228A true JPH0193228A (ja) | 1989-04-12 |
| JPH0561815B2 JPH0561815B2 (enrdf_load_stackoverflow) | 1993-09-07 |
Family
ID=17199325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24986487A Granted JPH0193228A (ja) | 1987-10-05 | 1987-10-05 | マルチフレーム同期回路用試験回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0193228A (enrdf_load_stackoverflow) |
-
1987
- 1987-10-05 JP JP24986487A patent/JPH0193228A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0561815B2 (enrdf_load_stackoverflow) | 1993-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5058104A (en) | Tdm demultiplexer with dedicated maintenance channels to indicate high-speed line faults to low speed circuits | |
| US5640387A (en) | Digital loop carrier apparatus for large volume digital signal transmission | |
| US4716561A (en) | Digital transmission including add/drop module | |
| US5159595A (en) | Ring transmission system | |
| US5265089A (en) | Loopback test circuit | |
| JP3478555B2 (ja) | 加入者系ディジタル伝送装置 | |
| US6917584B2 (en) | Channel reassignment method and circuit for implementing the same | |
| US4022979A (en) | Automatic in-service digital trunk checking circuit and method | |
| US5081619A (en) | Digital signal multiplex communication system having signal path monitoring function | |
| US4905228A (en) | Digital transmission channel framing | |
| US4924459A (en) | Digital transmission interconnect signal | |
| CA2083635C (en) | Digital signal hardware protection switching | |
| US6633537B1 (en) | Hitless path switching ring network, hitless path switching transmission system, node device for a hitless path switching ring network, and failure occurrence-time hitless path switching transmission method in a ring network | |
| DK171007B1 (da) | TDM-datatransmissionssystem | |
| US5768265A (en) | Duplex signal multiplexing system | |
| JPH0193228A (ja) | マルチフレーム同期回路用試験回路 | |
| CN100387001C (zh) | 一种用于测试芯片的虚级联延时对齐特性的系统及方法 | |
| US5710759A (en) | Switch protection arrangement | |
| EP0220808A2 (en) | Multiplexer for digital signals | |
| GB2280337A (en) | Multiplexing plesiochronous tributaries | |
| JPS5834076B2 (ja) | パイロツトシケンホウシキ | |
| JP3041868B2 (ja) | 高速回線障害通知方法および高速回線障害通知システム | |
| EP0212961A2 (en) | Digital transmission channel framing | |
| JP2744524B2 (ja) | 回線試験信号挿入方法およびデジタル回線試験装置 | |
| JP2821338B2 (ja) | ２次アラーム出力制御方法 |