JPH0193228A - Test circuit for multiframe synchronous circuit - Google Patents

Abstract

PURPOSE:To make the usage of a dedicated time slot on a multiplexing highway unnecessary by allocating a test bit for a pseudo normal test to confirm the normal operation of line supervisory information. CONSTITUTION:At the time of setting the pseudo normal state of up direction line supervisory information TNR1, a TNR1 pseudo normal setting part goes to a logic '1', and the first frame of a multiframe is fixed at '1' under the condition of a gate (1)4, and the frames from the first frame to the 8th frame of a multiframe pattern for pseudo normal test are fixed at '1's, and the TNR1 is detected at a TNR1 and 2 detection circuit 9. At the time of setting the pseudo normal state of down direction line supervisory information TNR2, a TNR2 pseudo normal setting part 8 goes to the logic '1', and output goes to a logic '0' at the position of a timing pulse T1 under the condition of a gate (2)5, and the TNR2 is set, and the TNR2 is detected at the TNR1 and 2 detecting circuit 9. In such a way, the TNR1 and 2 detecting circuit 9 detects an error, thereby, the normality of a circuit for the TNRs 1 and 2 can be tested.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to a test circuit for a multi-frame synchronization circuit, and more specifically, to a multi-frame synchronization test circuit in a digital transmission interface that transfers transmission line monitoring information manually input to an exchange. This relates to a circuit that tests the normality of the circuit.

(Prior art) Conventionally, this type of circuit was used in the "D70 type automatic switching machine [I
] Hardware (1)” Telecommunications Mutual Aid Foundation, February 1, 1981, p., 32o-p., 364, r.
D70 automatic switchboard [II] Hardware (2)” Telecommunications Mutual Aid Association, February 1, 1980, p.
320-p., 329. FIG. 3 shows an example of the configuration of a conventional circuit, which will be explained below.

First, an example of a digital multiplex interface and frame format used in the circuit shown in FIG. 3 for transferring line monitoring information detected in a transmission system will be explained with reference to FIGS. 4 and 5. FIG. 4 shows the 8M highway format, and FIG. 5 shows the 2M highway format. In these figures, the symbol 11G indicates the line setting unit (Handling group), and each HG has 1
Bit signal bits are assigned. Each HG signal bit takes a multiframe, and eight frames constitute a multiframe. The multi-frame synchronization bit F has a pattern that repeats "0" and "1" at the bit position every 8 frames under normal conditions, and the IIG is asynchronous. The V frame is a violation of “1”. Also, * is a device alarm, “0” is normal, “1”
is abnormal. Abnormal sending conditions were 11 people losing power, 2. F.S.O.
It is. The direction from the transmission terminal station to the exchange side is defined as upstream.

When a fault occurs in the uplink line, the transmission terminal station detects this, fixes the F bit (first frame) to "1", and notifies the exchange. The monitoring information transferred in this way is sent to TN.
Call it R.

When a failure occurs on the downlink transmission path, the monitoring information is transferred through the paired uplink transmission path. This information is transferred using bits defined in the eighth frame of the multiframe, and is called TNR2. TNR2 is "1" when normal and "0" when abnormal.

Next, the circuit configuration and operation of FIG. 3 will be described. The circuit shown in Figure 3 tests the normality of the circuit that detects TNR and TNR2.
WIFR) 11, a receiving section 12, a transmitting section 13, and a transmission highway interface (HWIFS) 14.

The receiving highway interface (HWIFR) 11 is 2
It receives four M highways and after phase synchronization, multiplexes them into 8M highway. The multiplex agent is shown in FIG. On the other hand, the transmission highway interface (HWIFS)
14 divides the 8M highway into four 2M highways. The separated side is also shown in FIG. 8 multiplexed at the receiving highway interface (H[FR) 11
Each time slot (hereinafter sometimes abbreviated as TS) of the M highway accommodates a TSO (accommodating HGs 1 to 5) shown in FIG.

However, the TSO of 2Mll1lO in Figure 6 is defined as a self-turnback time slot, and the TNRI and 2
This is used as a dedicated time slot for testing the normality of the detection circuit 12-5.

The receiving unit 12 includes a selector (SELA) 12-1. (S
ELB) 12-2, and a selection signal generator (TIMA) 12-3 for these selectors. (TIMB)12-4
and TNRI, 2 detection circuit 12-5. TNRI
, 2 detection circuit I2-5 is a selector (SELA) +2-
This is a circuit that detects TNRI and TNR2 of each of the outputs of IG.

The transmitter 13 includes a memory 13-1 and an MF pattern insertion circuit 1.
It consists of 3-2. The memory 13-1 has a capacity for 8 frames for each HG, and arbitrary data can be set from the 1st frame to the 8th frame, and is read out in synchronization with multi-frames, and the MP pattern insertion circuit 13-2 The multi-frame synchronization bit (“0”) is added to the first frame (F bit).
”, alternating numbers of “1”).

The output of the MF pattern insertion circuit 13-2 is connected to the transmission highway interface (HWIFS) 14, and the output of the MF pattern insertion circuit 13-2 is connected to the transmission highway interface (HWIFS) 14.
-5 is connected via a self-returning route 15 to test the normality of the terminal.

The selector (SELA) 12-1 is controlled by the selection signal generator (TIMA) 12-3 to select input 1 at the position of the self-loopback TS, and select input 0 at other TSs.

When testing the normality of the TNR1 detection circuit, selector (SELB) 12-2 selects input 1. Input signal logic “1”
Selection signal generator (TIMB) 12-4
The self-loopback TS is fixed at logic "1", and the TNRI,2 detection circuit 12-5 detects TNRl. The normality of the TNR1 detection circuit can be tested by the above operation.

When testing the normality of the TNR2 detection circuit, the selector (SELB) 12-2 at the position of the self-loopback TS selects the selection signal generator (TIMB) 12 to select 0 manually.
-4. HG of self-folding TS
In order to set logic “0” indicating TN112 to memory 1.
Logic "0" is written to the corresponding address of 3-1 (11G where the 8th frame is accommodated). With the above operation, TNRI
, 2 detection circuit detects TNR2 at the HG position of the self-returning TS.
can be detected and the normality of the TNR2 detection circuit can be tested.

(Problem to be Solved by the Invention) However, in the circuit configuration for testing the normality of the above-mentioned TNRI and TNR2 detection circuits, the IT
S is used, and memory is required to set TNR2. In this way, with the conventional circuit, TNRI
, the method of testing the TNR2 detection circuit has the problem that it occupies the ITS defined on the multiplex highway, increases the amount of hardware including memory, and requires complicated timing control.

The present invention provides an excellent test for multi-frame synchronization circuits that does not use memory to set the self-loopback TS and TNR2 described above, requires less hardware, and does not require a dedicated test TS on the multiplex highway. The purpose is to provide circuits.

(Means for Solving the Problems) The present invention is directed to a test circuit for a multi-frame synchronization circuit that tests the normality of a multi-frame synchronization circuit in a digital transmission interface, and in order to solve the problems of the prior art, Allocate test bits to perform a pseudo-normal test to confirm normal operation of TNR1 and TNR2, which are uplink and downlink line monitoring information, and create a multi-frame pattern for the pseudo-normal test at the bit timing position of the pseudo-normal test. Under the conditions of the first circuit to be inserted, the second circuit that generates a regular multi-frame pattern, the output pattern of the second circuit, and the signal that becomes logic "1" when TNR1 is pseudo-normal, a first gate for setting a TNR1 error in a multi-frame pattern for a normal test; and a signal that becomes logic "1" at the position of a frame in which TNR2 is accommodated in the second circuit.

Under the condition that TNR2 is pseudo-normal and the signal becomes logic “1”, T
A second gate is provided to set the NR2 error.

(Function) In the present invention, each technical means functions as follows. TNR
When setting 1 pseudo-normal, the function of the 1st gate causes the 2nd
A TNR1 error is set in the multi-frame pattern for the pseudo-normal test inserted by the first circuit under the conditions of the output pattern of the circuit and the signal that becomes logic "1" when TNR1 is pseudo-normal. On the other hand, when TNR2NR2 occurs, due to the action of the second gate, the second circuit generates a signal that becomes logic "1" at the position of the frame where TNR2 is accommodated, and a signal that becomes logic "1" when TNR2 is pseudo-normal.
A TNR2 error is set under the condition that the signal becomes 1". Then, the test is executed by detecting the error by the TNRI and TNR2 detection circuits. Therefore,
No memory is required for setting TNR2, and there is no need to use dedicated time slots on the multiplex highway, thus solving the problems of the prior art.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of the present invention, which includes a highway multiplexing section (MIX) 1, a selection circuit (SEL) 2, an MP synchronized putter destination generation section 3, and a gate (+) 4. , gate (2) 5, AND circuit 6, TNR1 pseudo-normal setting section (RITST) 7, and TNR2 pseudo-normal setting section (R2
TST) 8 and TNRI, 2 detection circuit 9.

Highway multiplex unit (MIX) 1 accommodates eight 8M highways in the format shown in Figure 4, and 11G1 to 1
1G20 is multiplexed for each highway. The format after multiplexing is shown in FIG. Each of the formats shown in Figure 2 +
1W bits biLo and lI are reserved bits. 1
(biL8 of W7 is used as a pseudo-normal test bit.

The Mli synchronization pattern generation unit 3 has a pattern in which the multiframe is composed of eight frames, the first frame is "0" and "1" alternating for each multiframe, and the second to eighth frames are fixed at "1". and gate (1) 4
It is output to. Further, from the generation unit 3, the pulse logic “1” (timing pulse TI) between one frame of the 8th frame to which TNR2 is assigned is sent to the gate (2) 5.
It is output to.

The TNRl, 2 detection circuit 9 is a highway IIWO~1I
This is a circuit that detects W7 (7) 1161 to 20 and TNRI and TNR2 of a multi-frame pattern for a pseudo-normal test.

The selection circuit (SEL) 2 uses a timing pulse logic "to select the multi-frame pattern (input 1) for the pseudo-normal test at the pseudo-normal test position (bit 8 of 'HW7)" in the multiplex format shown in FIG. 1” is supplied. In locations where the timing pulse is not logic "1", the output of the highway multiplexer (MIX) 1 (manual power 0) is selected. Input 1 of selection circuit (SEL) 2 is gate (
1) AND the outputs of 4 and gate (2) 5 using AND circuit 6.
This is a condition.

The gate (1) 4 receives the regular multi-frame pattern from the MF synchronization pattern generator 3 and the TNR1 pseudo-normal setting unit (R
This is an OR circuit that takes the output of ITST) 7 as input. Gate (2) 5 is timing pulse TI and TNR2N type 2
Pseudo-determinant part (R2TST) NAND with the output of 8 as input
It is a circuit.

TNRI pseudo-normal setting section (RITST) 7, TNR
The 2N type 2 pseudo constant section (R2TST) 8 sets pseudo normality of TNRI and TNRl by setting it to logic "1".

When setting TNR1 pseudo-normality, the TNRI pseudo-normal setting section (R
ITST) 7 becomes logic “1” and gate '(1)
Under condition 4, the first frame of the multi-frame is fixed to "1", and the multi-frame pattern for the pseudo-normal test is fixed to "1" from the first frame to the eighth frame, and the TNR
The I,2 detection circuit 9 detects TNR1.

When TNR2N is above 2 pseudo-constant, TNR2N type 2 pseudo-constant (R
2Ts'r) s becomes logic “1” and gate (2) 5
Under the condition of , the output is logic “0” at the timing pulse TI position.
”, TNRl is set, and the TNRI,2 detection circuit 9 detects TNRl.

With the above TNRI and TNR2 pseudo-normal settings, TNR
I, 2 detection circuit 9 detects an error, TNRI, TN
This means that the normality of the R2 detection circuit has been tested.

Although the above embodiment has been described using a specific frame configuration, it goes without saying that the present invention is applicable even if the number of monitoring signals, arrangement, pseudo-normal test timing position, etc. differ from the above embodiment.

(Effects of the Invention) As described above in detail, according to the present invention, the TN
In order to test the normality of the RI and TNR2 detection circuits, TN without defining a test TS on the multiplexed highway.
A first circuit that allocates test bits for a pseudo-normal test of Rl and TNRl and inserts a multi-frame pattern for a pseudo-normal test at a pseudo-normal test position, and a first circuit that independently inserts TNRI and TNRl into the multi-frame pattern. In order to set this, we provided a first gate that causes TNR1 to occur when TNR1 is pseudo-normal and a second gate that causes TNRl to occur when TNR2 is pseudo-normal.
can be set. Therefore, the TN used in the prior art
No memory is required to set Rl, and a reduction in the amount of hardware and simplification of control can be expected. Furthermore, TNRI, T
There is no need to use a dedicated time slot on the multiplexed highway for the NR2 pseudo-normal test, and the time slots on the highway can be expected to be used effectively.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram showing the format after multiplexing, Fig. 3 is a configuration diagram of a conventional circuit, and Fig. 4 is a diagram showing the format after multiplexing.
Figure 5 shows an example of the 8M highway format.
Figure 6 shows an example of the 2M highway format.
The figure is an explanatory diagram of the multiplexing agent/separating agent. 1...Highway multiplex unit (MIX) 2...Selection circuit (SEL) 3-MF synchronization pattern generation unit 4.5...Gate 7.8-TNIll, TNR2 pseudo-normal setting unit 9-T
NRI, 2 detection circuit

Claims (1)

[Claims] In a test circuit for a multiframe synchronization circuit that tests the normality of a multiframe synchronization circuit in a digital transmission interface, normal operation of TNR1 and TNR2, which are upstream and downstream line monitoring information, is confirmed. A first circuit that allocates test bits for performing a pseudo-normal test and inserts a multi-frame pattern for the pseudo-normal test at the bit timing position of the pseudo-normal test, and a second circuit that generates a regular multi-frame pattern. and a first gate for setting a TNR1 error in the multi-frame pattern for the pseudo-normal test under the conditions of the output pattern of the second circuit and a signal that becomes logic "1" when TNR1 is pseudo-normal. In the second circuit, a signal becomes logic "1" at the position of the frame where TNR2 is accommodated, and a signal becomes logic "1" when TNR2 is pseudo-normal.
A test circuit for a multi-frame synchronous circuit, characterized in that a second gate is provided for setting a TNR2 error under the condition that the signal is ``.''.