JPH0192834A - Microprogram controller - Google Patents

Abstract

PURPOSE:To attain the fine adjustment of a software instruction executing time by adding a circuit for detecting the end of a software instruction, a flop flop (FF) for invalidating the suppression of microinstruction execution and an AND circuit. CONSTITUTION:The instruction end detecting circuit 5, the FF 6, the AND circuit 7, and signal lines connected to the circuits 5, 7 are added. When the output of the circuit 5 displays the end of the software instruction, the FF 6 is set up and then reset by a 2nd microinstruction. When the FF 6 is in the set state, a suppression signal is validated, and in case of its reset state, the suppression signal is invalidated. Consequently, the execution can be adjusted at every software instruction.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a microprogram controller.

[Conventional technology]

Generally, a plurality of models are set for each type of information processing apparatus, and one means of setting differences between models is to provide a difference in the execution time of software instructions. That is, the upper model processes software instructions at high speed, and the lower model processes software instructions at low speed.

Several methods have been known for setting the execution time of software instructions for each model.

One method is to insert microinstructions that have no functional meaning between the end of one software instruction and the start of the next software instruction, that is, dummy steps, and change the number of dummy steps for each model. This is a method of setting the execution time of software instructions. Furthermore, it has a counter that increments every clock and a speed regulating register that can be set by a microinstruction, compares the counter and the speed regulating register, and executes software processing when a certain condition is met. In this method, the execution time of software instructions for each model is set by changing the value of the speed regulating register for each model.

[Problem that the invention seeks to solve]

The conventional method described above has one drawback: it is not possible to adjust the execution time for each software instruction because microinstructions that have no functional meaning are inserted or the inhibition of microinstruction execution is set independently of software instructions. was there.

[Failure to solve the problem]

A microprogram control device according to the present invention.

A microinstruction register that stores microinstructions.

A counter that increments every clock, a speed regulating register that can be set to an arbitrary value by a first microinstruction, and comparing the value of the counter and the value of the speed regulating register so that the two values have a predetermined relationship. a comparison circuit that generates an inhibition signal that instructs to inhibit execution of the microinstruction when the condition is satisfied; a detection circuit that detects the end of the software instruction; and a detection circuit that is set when the output of the detection circuit indicates the end of the software instruction.

Further, when the fritsuno flop reset by the second microinstruction and the fritsuno flop are in a set state, the inhibit signal is enabled.

and a circuit for disabling the inhibit signal when the fritsuno flop is in a reset state.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

For convenience of explanation, the prior art will first be explained with reference to FIG.

Here, it is assumed that both the counter 2 and the regulating register 3 have a size of 3 bits. Furthermore, assume that execution of one microinstruction is completed in one clock.

It is assumed that processing of one software instruction is achieved by executing multiple microinstructions.

A clock 100 is supplied to the microinstruction register 1, and microinstructions are loaded every clock. A clock 100 is supplied to the counter 2, and the counter 2 increments every clock, and the value is O→1→2→...→7
→0→1→2→... It changes in a cycle of 8 clocks.

A value unique to the model is loaded into the speed regulating register 3 by a microinstruction at the time of initial setting of the information processing system.

The output 22 of the counter 2 and the output 23 of the speed regulating register 3 are both supplied to the comparison circuit 4. Comparison circuit 4 is counter 2
The value of the output 22 of the speed governor register 3 is compared with the value of the output 23 of the speed governor register 3, and 1'' is output for the number of clocks indicated by the value of the output 23 of the speed governor register 3 out of 8 clocks in one cycle. When the value of the output 23 of the register 3 is 00, the output 24 of the comparator circuit 4 becomes 0''. Since the comparison circuit 4 can be realized with a relatively simple configuration, a circuit diagram and explanation thereof will be omitted.

Output 21 of microinstruction register 1 that directs the processing of software instructions. Output 24 of comparison circuit 4 and clock 1
00 is supplied to the software instruction processing unit 10.

When the output 24 of the comparison circuit 4 is 0'', the contents of the output 21 of the microinstruction register 1, that is, the software instruction processing microinstruction is executed by the software instruction processing unit 10, and the output 24 of the comparison circuit 4 is 11''. In this case, execution of the software instruction processing microinstruction by the software instruction processing unit 10 is inhibited.

Assuming that the upper model loads 0 into the speed control register 3 and the lower model loads 2, the software instruction processing microinstruction is not inhibited in the higher model and is executed every clock, and the lower model executes one cycle of counter 2. Since 2 clock inhibition signals are generated out of 8 clocks, 2/
The software instruction processing microinstruction will not be executed during the time 8. Therefore, the average execution time of software instructions in the lower model is 876 times that of the upper model.

Next, an embodiment of the present invention will be described with reference to FIG.

In this embodiment, in contrast to the prior art example shown in FIG.
A signal line connected to the instruction end detection circuit 5° flip-flop 6,7725, 6.7 surrounded by the dotted line in the figure was added. Since the circuits outside the dotted lines are the same as those in the prior art, explanations will be added for the parts inside the two-dotted lines.

The set terminal of the flip-flop 6 is connected to the output 25 of the instruction completion detection circuit 5 that detects the completion of processing of software instructions.
is supplied to the reset terminal of flip-flop 6,
The output 31 of microinstruction register l is supplied.

That is, the flip-flop 6 is set to ``1'' when the processing of the software instruction is completed, and the microinstruction register 1 is set to ``1''.
is reset to 10' if a particular microinstruction appears on the output 31 of the software instruction during software instruction processing.

One input of the AND circuit 7 is supplied with the output 26 of the 7-rig float f6, and the other input is supplied with the output 26 of the 7-rig float f6.

The output 24 of the comparator circuit 4 is supplied. Therefore.

When the output 24 of the comparison circuit 4 is 0'', the AND circuit 7
The output 27 of the AND circuit 7 becomes "0" regardless of the value of the output 26 of the flip-flop 6, and when the output 24 of the comparator circuit 4 is "1", the output 27 of the AND circuit 7 becomes "0" regardless of the value of the output 26 of the flip-flop 6. When the output of the frizzo flop 6 is 0'', the output is 0''.The output 27 of the AND circuit 7 is supplied to the software instruction processing unit IO.The output 27 of the AND circuit 7 is 0'' In this case, if the contents of the output 21 of the microinstruction register 1, that is, the software instruction processing microinstruction is executed by the software instruction processing unit 10, and the output 27 of the AND circuit 7 is 1'', the software instruction processing microinstruction is Execution in the software instruction processing unit 10 is suppressed.Adding a supplementary explanation, when the value of the flip-flop 6 is 1'', the software instruction processing microinstruction is inhibited by the value set in the speed regulating register 3. Execution is inhibited and flip-flop 6
When the value of is 0'', the inhibition of execution of the software instruction processing microinstruction by the speed regulating register 3 is disabled.

In this embodiment, only the output 25 of the instruction end detection circuit 5 is used as the flip-flop 60 set, but it may be possible to select by this output 25 or by a specific microinstruction. Further, the instruction end detection circuit 5 may detect the start of a software instruction instead of the end of a software instruction.

〔Effect of the invention〕

As explained above, the present invention can improve software by adding a circuit for detecting the end of a software instruction, a 7 rig for disabling microinstruction execution inhibition, and an AND circuit to the prior art. This has the effect that the instruction execution time can be finely adjusted.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a microprogram control device according to an embodiment of the present invention! FIG. 2 is a block diagram showing the configuration of a conventional microprogram control device. 1... Microinstruction register, 2... Counter, 3
. . . Speed control register, 4. Comparison circuit, 5. Instruction end detection circuit, 6. Flip-flop, 7. AND circuit. 10...Software instruction processing section, 21 to 27.31
and 100... connection line.

Claims (1)

[Claims] 1. In an information processing system that processes software instructions by executing multiple microinstructions, there is a microinstruction register that stores the microinstructions, a counter that increments every clock, and an arbitrary value that is incremented by the first microinstruction. a speed control register that can be set; and a comparison that compares the value of the counter with the value of the speed control register, and generates a suppression signal that instructs to suppress execution of the microinstruction when both values satisfy a predetermined relationship. a detection circuit for detecting the end of a software instruction; a flip-flop that is set when the output of the detection circuit indicates the end of the software instruction and reset by a second microinstruction; and the flip-flop a circuit that enables the inhibition signal when the flip-flop is in a set state, and disables the inhibition signal when the flip-flop is in a reset state;
A microprogram control device, characterized in that the execution time of a software instruction is controlled by inhibiting the execution of the microinstruction based on the values of the speed regulating register and the flip-flop.