JPH0421212B2 - - Google Patents
Info
- Publication number
- JPH0421212B2 JPH0421212B2 JP55131819A JP13181980A JPH0421212B2 JP H0421212 B2 JPH0421212 B2 JP H0421212B2 JP 55131819 A JP55131819 A JP 55131819A JP 13181980 A JP13181980 A JP 13181980A JP H0421212 B2 JPH0421212 B2 JP H0421212B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- signal
- power supply
- operation control
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 description 12
- 230000001360 synchronised effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 101000668165 Homo sapiens RNA-binding motif, single-stranded-interacting protein 1 Proteins 0.000 description 1
- 102100039692 RNA-binding motif, single-stranded-interacting protein 1 Human genes 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/12—Regulating voltage or current wherein the variable actually regulated by the final control device is ac
- G05F1/40—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices
- G05F1/44—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices semiconductor devices only
- G05F1/45—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices semiconductor devices only being controlled rectifiers in series with the load
- G05F1/455—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices semiconductor devices only being controlled rectifiers in series with the load with phase control
Description
【発明の詳細な説明】
本発明はシリコン制御整流素子の零クロススイ
ツチングを制御する運転制御回路に係り、特にそ
のシリコン制御整流素子の零のクロススイツチン
グにおける非同期入力方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operation control circuit for controlling zero cross switching of a silicon controlled rectifier, and more particularly to an asynchronous input method for zero cross switching of a silicon controlled rectifier.
以下、本発明について図面を参照して詳細に説
明する。第１図は本発明に係る運転制御回路を備
えた運転装置の部分回路図、第２図は同運転制御
回路における動作の流れの一実施例を示したフロ
ーチヤート、第３図は同タイムチヤートを示す。 Hereinafter, the present invention will be explained in detail with reference to the drawings. Fig. 1 is a partial circuit diagram of an operating device equipped with an operation control circuit according to the present invention, Fig. 2 is a flowchart showing an example of the flow of operation in the operation control circuit, and Fig. 3 is a time chart of the same. shows.
第１図において、１は制御負荷、２は前記制御
負荷１を制御するSCR、３は前記SCR２のゲー
ト信号の制限抵抗、４はインバータ、５は商用電
源、６は降圧整流部、７は直流安定化電源部、８
は電源クロツクの波形整形部、９は入力情報を与
えるスイツチ、１０は運転制御回路（通常はマイ
クロコンピユータで構成される）、１１は前記運
転制御回路１０の入力端子I1のプルダウン抵抗
で、運転装置はこれらより構成されている。 In FIG. 1, 1 is a control load, 2 is an SCR that controls the control load 1, 3 is a limiting resistor for the gate signal of the SCR 2, 4 is an inverter, 5 is a commercial power supply, 6 is a step-down rectifier, and 7 is a DC Stabilized power supply section, 8
9 is a waveform shaping section of the power supply clock, 9 is a switch that provides input information, 10 is an operation control circuit (usually composed of a microcomputer), and 11 is a pull-down resistor of the input terminal I1 of the operation control circuit 10. The device is composed of these.
この運転装置において、制御負荷１はSCR２
により零クロススイツチングするが、これは電源
クロツク波形整形部８より得られた出力が運転制
御回路１０のα端子に入力され、入力端子I1より
与えられる情報により出力端子O1が出力され、
出力O1がＨならばインバータ４が反転し、制限
抵抗３を通してゲート信号が流れる。ゲート信号
は（すなわち出力O1）は第２図のフローチヤー
トに示すように電源クロツクと同期がとれている
ため零クロススイツチングが可能である。 In this operating device, control load 1 is SCR2
This is because the output obtained from the power supply clock waveform shaping section 8 is input to the α terminal of the operation control circuit 10, and the output terminal O1 is output based on the information given from the input terminal I1 .
If the output O1 is H, the inverter 4 is inverted and the gate signal flows through the limiting resistor 3. Since the gate signal (ie, output O 1 ) is synchronized with the power supply clock as shown in the flowchart of FIG. 2, zero cross switching is possible.
第２図は一実施例として電源クロツクの１パル
ス毎に時間調整を行なうことによる電源非同期の
入力読み込み方法のフローチヤートを示したもの
である。このフローチヤートについて説明すれば
先ずステツプN1で出力O1の状態変化が必要か否
かを判定し、必要な場合はステツプN2に移り、
ここで電源クロツクが有るか否かを判定し、有る
場合にはステツプN3に移つて出力O1より指定モ
ードを出力する。またステツプN1の判定の結果
出力O1の状態変化が必要でない場合にはステツ
プN4に移り、ここで電源クロツクが有るか否か
を判定し、有る場合にはステツプN5に移る。ス
テツプN6では非同期カウンタが１か否かを判定
し、１の場合はステツプN7に移り、ここで非同
期カウンタを０にし、ステツプN8でt1時間調整
した後、ステツプN9で入力I1を読み込む。また、
ステツプN6で非同期カウンタが１でないと判定
した場合にはステツプN10に移つて、ここで非同
期カウンタに１を加えた後ステツプN9に移る。
ステツプN11では同一データＸ回継続か否を判定
し、継続の場合にはステツプN12に移つて入力状
態による指定された処理をする。また、同一デー
タＸ回継続でない場合はステツプN12以降の処理
に移る。 FIG. 2 is a flowchart showing a method of reading an input asynchronously from the power supply by adjusting the time for each pulse of the power supply clock as an embodiment. To explain this flowchart, first, in step N1 , it is determined whether or not a change in the state of the output O1 is necessary, and if it is necessary, the process moves to step N2 .
Here, it is determined whether or not there is a power supply clock, and if there is, the process moves to step N3 and outputs the designated mode from output O1 . If the result of the determination in step N1 is that a change in the state of the output O1 is not required, the process moves to step N4 , where it is determined whether or not there is a power supply clock, and if there is, the process moves to step N5 . In step N6 , it is determined whether the asynchronous counter is 1 or not. If it is 1, the process moves to step N7 , where the asynchronous counter is set to 0, and after adjusting for t1 time in step N8 , the input I is input in step N9 . Load 1 . Also,
If it is determined in step N6 that the asynchronous counter is not 1, the process moves to step N10 , where 1 is added to the asynchronous counter, and then the process moves to step N9 .
In step N11 , it is determined whether or not the same data is continued X times. If it is continued, the process moves to step N12 and processes specified according to the input state are performed. If the same data is not repeated X times, the process moves to step N12 and subsequent steps.
第３図は運転制御回路１０における動作のタイ
ムチヤートの一実施例を示したものであり、ａは
電源クロツクの状態変化のタイムチヤート、ｂは
出力O1の状態変化のタイムチヤート、ｃは通常
RAMを使用する非同期カウンタの内容（この場
合はφ、１）、ｄは入力I1の読み込みタイミング
を示す。 FIG. 3 shows an example of a time chart of the operation in the operation control circuit 10, in which a is a time chart of the state change of the power supply clock, b is a time chart of the state change of the output O1 , and c is a normal time chart.
The contents of an asynchronous counter using RAM (φ, 1 in this case), d indicates the read timing of input I1 .
本実施例ではｄの実線の部分で入力の読み込み
を行なうため、入力読み込みの実線で電源同期の
ノイズによる誤読み込みをしたとしても、ノイズ
の同期位置が次は破線の位置にあり、これよりt1
後に入力読み込みを行なうため正規の入力を読み
込むことができる。 In this embodiment, the input is read in the solid line part d, so even if there is an erroneous reading due to power synchronization noise on the solid line of the input read, the next noise synchronization position will be the broken line position, and from this it can be seen that t 1
Regular input can be read for later input reading.
また、t1の時間調整は運転制御回路１０の駆動
クロツク（通常マシンサイクル）を利用して、シ
ーケンスに影響を与えない命令（NO−
OPERATION、RAMのインクリメント命令）
の積み重ねにより容易に行なうことが可能であ
る。 In addition, the time adjustment for t1 uses the drive clock (normal machine cycle) of the operation control circuit 10 to execute an instruction that does not affect the sequence (NO-
OPERATION, RAM increment instruction)
This can be easily done by stacking.
尚、マイクロコンピユータの一部にはハードの
割り込み端子を持つているものもあり、この場合
は比較的零クロススイツチングが容易であるが、
しかしダイナツク表示を処理している場合、ハー
ドの割り込みがどのタイミングで行なわれるか不
明であるため、時には表示の明暗の差、チラツキ
等の原因となることもあり、本発明による方が有
利である。 Note that some microcomputers have hardware interrupt terminals, and in this case zero cross switching is relatively easy.
However, when processing a dynamic display, it is unknown at what timing a hardware interrupt will occur, which can sometimes cause differences in display brightness and flickering, so the present invention is more advantageous. .
従来は第２図に示したフローチヤートの破線の
部分を処理せずにシーケンス動作を行なうため入
力I1の読み込みタイミングが電源と同期され、電
源の同期ノイズに対して回路的に弱いが、本発明
によれば電源クロツクに対して入力I1の読み込み
タイミングを正規の入力信号と判断するＸ回の読
み込み回数の内少なくとも１回はずらして読み込
むことにより電源の同期ノイズに対する排除能力
を上げることができる。 Conventionally, the reading timing of input I1 was synchronized with the power supply in order to perform sequence operation without processing the part indicated by the broken line in the flowchart shown in Figure 2, and the circuit was vulnerable to synchronization noise of the power supply. According to the invention, the ability to eliminate synchronized noise of the power supply can be improved by shifting the reading timing of the input I1 relative to the power supply clock by at least one of the X number of times of reading to determine that it is a normal input signal. can.
第１図は本発明に係る運転制御回路を備えた運
転装置の部分回路図、第２図は同運転制御回路に
おける動作の流れの一実施例を示したフローチヤ
ート、第３図は同タイムチヤートを示す。
１：制御負荷、２：SCR、１０：運転制御回
路。
Fig. 1 is a partial circuit diagram of an operating device equipped with an operation control circuit according to the present invention, Fig. 2 is a flowchart showing an example of the flow of operation in the operation control circuit, and Fig. 3 is a time chart of the same. shows. 1: Control load, 2: SCR, 10: Operation control circuit.
Claims (1)
を導通制御し、このスイツチング素子の導通制御
により制御負荷の運転を制御するものにおいて、 運転制御情報の信号入力手段が接続される信号
入力端子と、波形整形された電源クロツク端子
と、上記スイツチング素子に運転制御信号を出力
する出力端子と、を備えるマイクロコンピユータ
を設け、 このマイクロコンピユータは、電源クロツクの
入力に応じて、予じめ定められたカウントを行う
カウンタ手段Ｎ６，Ｎ７，Ｎ１０と、 このカウンタ手段のカウント状態に応じて、電
源クロツクに対して零乃至１サイクル未満の予じ
め定められた時間設定を行うずれ時間設定手段Ｎ
８，Ｎ１０と、 電源クロツクの立ち上がりから上記ずれ時間設
定手段によつて設定された時間ずれたタイミング
で順次運転制御信号の入力の有無を読み込む信号
読み込み手段Ｎ９と、 上記読み込み手段により運転制御信号が入力さ
れたと判断した場合に、該信号が入力されたタイ
ミングから数回連続して信号が入力されたかを判
定する連続性判定手段Ｎ１１と、 該判定により、数回連続して信号が入力された
場合に、入力された運転制御信号に対応する負荷
制御信号を上記スイツチング素子に出力する制御
信号発生手段Ｎ１２，Ｎ１〜Ｎ５と、から構成し
た運転制御回路。[Scope of Claims] 1. In a device that controls conduction of a switching element in synchronization with a zero cross of a power supply, and controls the operation of a control load by controlling conduction of this switching element, a signal input means for operation control information is connected. A microcomputer is provided with a signal input terminal, a waveform-shaped power supply clock terminal, and an output terminal for outputting an operation control signal to the switching element. counter means N6, N7, N10 for performing a predetermined count; and a shift time setting for setting a predetermined time from zero to less than one cycle with respect to the power supply clock according to the counting state of the counter means. Means N
8, N10, signal reading means N9 for sequentially reading the presence or absence of input of the operation control signal at timings set by the time lag setting means from the rise of the power supply clock; a continuity determining means N11 for determining whether the signal has been input several times consecutively from the timing at which the signal was input when it is determined that the signal has been input; an operation control circuit comprising control signal generating means N12, N1 to N5 for outputting a load control signal corresponding to an input operation control signal to the switching element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55131819A JPS5757318A (en) | 1980-09-22 | 1980-09-22 | Operation control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55131819A JPS5757318A (en) | 1980-09-22 | 1980-09-22 | Operation control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5757318A JPS5757318A (en) | 1982-04-06 |
| JPH0421212B2 true JPH0421212B2 (en) | 1992-04-09 |
Family
ID=15066835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55131819A Granted JPS5757318A (en) | 1980-09-22 | 1980-09-22 | Operation control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5757318A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5112089A (en) * | 1974-07-19 | 1976-01-30 | Kazuaki Myake | GODOSABOSHISOCHI |
| JPS54140947A (en) * | 1978-04-25 | 1979-11-01 | Ricoh Co Ltd | Method of stabilizing ac power source |
| JPS54143851A (en) * | 1978-04-28 | 1979-11-09 | Ricoh Co Ltd | Method of controlling power source voltage |
-
1980
- 1980-09-22 JP JP55131819A patent/JPS5757318A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5112089A (en) * | 1974-07-19 | 1976-01-30 | Kazuaki Myake | GODOSABOSHISOCHI |
| JPS54140947A (en) * | 1978-04-25 | 1979-11-01 | Ricoh Co Ltd | Method of stabilizing ac power source |
| JPS54143851A (en) * | 1978-04-28 | 1979-11-09 | Ricoh Co Ltd | Method of controlling power source voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5757318A (en) | 1982-04-06 |
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