JPH018965Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a phase shift type position detection device, and is particularly aimed at stabilizing its output.

As a device for detecting the position of a detection target, there is a phase shift type position detection device using a phase shift type sensor. What is a phase shift type sensor? The reference AC signal is detected by detecting the position of the object (rotational position or linear position).
It generates an output signal whose phase is shifted according to the output signal. This type of phase shift type position detection device is shown in FIG. As shown in the figure, count 1
is a modulo M-adic (M is an arbitrary integer) and sequentially counts the high-speed clock pulse CP given from the clock generation circuit 2 at its falling edge. The M/quaternary frequency division stage output of the counter 1 is input to the sine/cosine generation circuit 3. This sine/cosine generating circuit 3 divides the output of the counter 1 and passes two types of rectangular waves with a phase shift of 90 degrees through a low-pass filter, and outputs signals of sinωt and cosωt. It has gained.
These output signals sinωt and cosωt are input to the primary sides 4a and 4b of the phase shift type sensor 4, respectively. As a result, an output signal sin(ωt+θ) having a phase difference θ corresponding to the position of the object to be detected is obtained from the secondary side 4c of the phase shift type sensor 4. At this time, the frequency of the output signals sinωt and cosωt is equal to the frequency of the clock pulse CP.
Therefore, one count of the counter 1 corresponds to a phase angle of 2π/M (radians). Furthermore, the output signal
sin(ωt+θ) is sent to the inverting input terminal of the comparator 6 for zero-cross detection via the capacitor _C1 . A reference voltage V _ref is applied to the non-inverting input terminal of this comparator 6, and as a result, a pulse signal S ₀ of “1” or “0” is generated in response to the positive or negative polarity of the output signal sin (ωt+θ). is now output. The D flip-flop circuit 7 is
The pulse signal S ₀ is input to the input terminal, and the clock pulse CP is input to the C input terminal, so that the rising edge from the Q output terminal corresponds to the rising edge of the pulse signal S ₀ , that is, the zero phase (or
Sends a latch signal S ₁ that is synchronized at 180 degrees phase). On the other hand, data D, which is the count content of the counter 1, is sequentially given to the latch register 8, and by inputting the latch signal _S1 , the data D at that time is latched and displayed as the output data _D0 of the position detecting device. The signal is sent to a device (not shown), etc.
At this time, the modulus number M of counter 1 is the output signal
Since it corresponds to one period of sinωt, the count value corresponds to the phase value, and for example, this output signal
It can be designed so that all bits of counter 1 are "0" when sinωt has zero phase. Thus, by latching the contents of the latch register 8 with the latch signal _S1 that rises in response to the zero cross of the output signal sin(ωt+θ) of the phase shift type sensor 4, data indicating the phase difference θ, that is, the position of the object to be detected, is obtained. Obtain data showing.

However, this technique has the following problems. That is, in the above phase shift type position detection device,
Counter 1 counts at the falling edge of the clock pulse CP, and at the rising edge, the output signal sin(ωt+
Since the pulse obtained from the output signal sin(ωt+θ) is sampled, the phase shift type sensor is placed at a position such that the rise of the pulse _S0 obtained from the output signal sin(ωt+θ) occurs exactly at the same time as the rise of the clock pulse CP. 4 stops, adjacent two values are output as output data at each sampling period.
It will be output randomly. This is the second
This will be further explained using the waveform diagrams shown in FIGS. Figure 2a shows clock pulse CP, Figure 2b shows counter 1.
The content of FIG. 2c shows the pulse signal S ₀ respectively. The phase shift sensor 4 is stopped at a position where the rising edge of the clock pulse CP and the rising edge of S ₀ occur simultaneously, but strictly speaking, the rising edge of S ₀ is caused by noise and other influences. Clock pulse randomly every cycle
Since the rising edge of CP may be earlier or later than the rising edge of CP, the output S ₁ obtained by sampling S ₀ by the clock pulse rises at a random time position such as A in Figure 2 d for each period of S ₀ . It rises and rises at the time position shown in Figure B,
Therefore, the output data is "3" when _S1 is A.
, and when S ₁ is B, it becomes "4", and "3"
and "4" will be output randomly at a period of S ₀ .

In this case, if the load is a digital circuit such as a microcomputer, processing is possible, but
In the case of a low-speed operation circuit such as a relay load, if the data changes frequently such as "3" or "4", there is a risk that the circuit will not be able to fully respond and will not operate at any numerical value.

In view of the above points, it is an object of the present invention to provide a phase shift type position detection device that can prevent unstable changes in output data as described above and stabilize it. The present invention, which achieves this object, is based on the technical concept of providing a temporal hysteresis characteristic. More specifically, since time only advances in a certain direction, 1 from the latch timing of the counter's "n"
If the pulse signal, which is the output of the comparator for zero-cross detection, rises after a delay of even 30 seconds, the rise of the pulse signal is forcibly delayed to some extent, and after that, it is latched according to the latch timing of "n+1" of the counter. By doing so, the rise of the pulse signal is prevented from remaining at the same time as the rise of the clock pulse.

Embodiments of the present invention will be described in detail below with reference to the drawings. Note that the same parts as those in FIG. 1 are given the same numbers and redundant explanations will be omitted. As shown in Figure 3,
This embodiment device newly includes a D flip-flop 9,
10 and a feedback resistor R _f are added. Of these, the D input terminal of the D flip-flop circuit 9 receives the output signal of the AND circuit 11, which is an AND condition of the pulse signal _S0 and the output of the D flip-flop circuit 7, and the clock pulse CP is input to the C input terminal of the AND circuit 11. A signal inverted by the inverter 12 is input. Further, the D flip-flop circuit 9 has a D input terminal of the D flip-flop circuit 10.
The Q output of the D flip-flop circuit 7 is input to the C input terminal thereof. The feedback resistor R _f is connected between the non-inverting input terminal of the comparator 6 and the Q output terminal of the D flip-flop circuit 10, and positively feeds back this voltage when the output terminal of the D flip-flop circuit 10 is in the "1" state. The reference voltage V _ref of the comparator 6 is made relatively high, and conversely, when the output terminal is in the "0" state, the reference voltage V _ref is made relatively low. At this time, the value of the feedback resistor R _f is selected so that the rise of the pulse signal S ₀ moves by T/4 (where T is the period of the clock pulse CP) due to the difference in the reference voltages.

The operation of this embodiment will be explained based on FIGS. 4a to 4n and FIGS. 5a to 5c. Note that Fig. 4a shows the contents of counter 1, Fig. 4b shows the clock pulse CP, Fig. 4c shows the pulse signal _S0 , and Fig. 4d
4 shows the latch signal S ₁ , FIG. 4 e shows the Q output of the D flip-flop circuit 9, FIG. 4 f shows the output of the D flip-flop circuit 10, and FIGS. 4 g to 4 j show the waveforms of the next sampling. 4k to 4n are the pulse signal S ₀ of the next sampling period, the latch signal S ₁ , the Q output of the D flip-flop circuit 9, and the D flip-flop circuit 10.
These are waveforms showing the outputs of . As can be understood by referring to FIG. 4f, when the output of the D flip-flop circuit 10 is in the "1" state,
The reference voltage V _ref of the comparator 6 is V _ref1 higher than the zero point, as shown by the dashed line in FIG. 5a.

Here, consider the following case. That is, as shown in FIGS. 4a to 4c, it is assumed that the rise of the pulse signal _S0 is almost simultaneous with the rise of the clock pulse CP, but earlier by a very small amount of time. At this time, the latch signal S1 rises at the rising edge of the clock pulse CP when the content of the counter 1 is " ₃ " as shown in FIG. 4a, so the content "3" of the counter 1 is latched in the register 8. Ru. And the pulse signal S ₀ is the output signal sin(ωt+
θ) falls again when it crosses V _ref1 in the positive direction, and accordingly, the latch signal _S1 also falls at the falling edge of the next clock pulse CP, returning to its original state. Next, when the output signal sin (ωt + θ) crosses the reference voltage V _ref1 in the negative direction, the signal
At this time, for example, due to fluctuations in the output signal sin (ωt + θ), the rise of the signal _{S 0 is} slightly delayed, and is later than the rise of the clock pulse CP when counter 1 is "3". If the signal S ₀ rises, the fourth
As shown in Figures g and h, the latch signal S ₁ is
It does not rise at the rising edge of the clock pulse CP when the counter 1 is "3", but rises at the rising edge of the clock pulse CP when the next counter 1 is "4", so "4" is latched in the register 8. At this time, the output of the AND circuit 11 is "1" from the time the pulse signal _S0 rises until the time the latch signal _S1 rises, and therefore the Q output of the D flip-flop circuit 9 is as shown in FIG. As shown, the clock pulse CP corresponding to the content of “3”
When the clock pulse CP falls, it rises and becomes the "1" state, and when the clock pulse CP corresponding to the content of "4" falls, it falls and becomes the "0" state again. Therefore, the output of the D flip-flop circuit 10 is the Q of the D flip-flop circuit 9, as shown in FIG.
The output falls at the rising edge of the latch signal _S1 in the "1" state, changing from the "1" state to the "0" state.
Therefore, the positive feedback of the reference voltage V _ref is canceled, and the reference voltage V _ref becomes a low value V _ref0 as shown by the solid line in FIG. 5a (zero potential in this example). Therefore, the next time the output signal sin (ωt+θ) crosses the reference voltage V _ref in the negative direction, if positive feedback to the reference voltage is still applied and V _ref = V _ref1 , the pulse Even if the rising edge of the signal _S0 could have returned to the time position shown in Figure 4c, the reference voltage
V _ref is changing from V _ref1 to V _ref0 , and even for the same output signal sin (ωt + θ), the rise of the pulse signal S ₀ is delayed by T/4 as shown in Fig. 4k. The rise of the pulse signal _S0 is always delayed from the rise of the clock pulse CP when the counter 1 is "3", so the latch signal _S1 is delayed from the rise of the clock pulse CP when the counter 1 is "4". stand up at the rise of
Therefore, the register 8 latches the counter content "4", and thereafter, as long as the phase difference θ does not change, the output of the D flip-flop circuit 10 is held at "0", and the reference voltage _Vref becomes _Vref0. The count value ``4'' is repeatedly sampled and latched accurately. Therefore, the output signal sin(ωt
+θ) or due to the influence of noise, etc.
Clock pulse at the rising edge of pulse signal S ₀
Even if the time position relative to the rising edge of CP fluctuates every cycle of the output signal, if the width of the fluctuation is smaller than 1/4 or T/4 of the clock pulse period T, the clock pulse will not be affected by the fluctuation. , stable output data can be sent. Phase difference θ
The rising edge of signal S ₀ becomes a clock pulse due to the movement of
When entering the first half period of CP, the signal _S1 rises before the Q output of the D flip-flop 9 rises, and the output of the D flip-flop 10 starts to rise. In this way, positive feedback is again applied to the reference voltage V _ref .

As specifically explained above with the examples,
According to the present invention, the timing of sampling the output signal of the phase shift type sensor is forcibly shifted so that the time relationship between the clock pulse and the output pulse does not remain at a position where the output data becomes unstable. Therefore, from now on, certain contents of the counter are forcibly latched, and as a result, the output data can be stabilized.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a general circuit configuration of a phase shift type position detection device, Figs. 2a to 2d are waveform diagrams showing waveforms of each part thereof, and Fig. 3 is an embodiment of the present invention. Block diagrams showing Figures 4a to 4
FIG. 5(n) is a waveform diagram showing the waveforms of various parts of the same embodiment, and FIGS. 5(a) to 5(c) are waveform diagrams for explaining the timing of the rise of the reference voltage and pulse signal in the same embodiment. 1... Counter, 4... Phase shift type sensor,
6... Comparator, 8... Latch register,
CP...Clock pulse, S ₀ ...Pulse signal, S ₁
... Latch signal, R _f ... Feedback resistor, V _ref ... Reference voltage, 7, 9, 10, 11, 12, R _f ... Circuit element constituting the output stabilization circuit.

Claims (1)

[Claims for Utility Model Registration] 1. A phase-shift type sensor that generates an output signal that is a phase-shifted reference AC signal according to the detection target position; a counting means that counts a predetermined clock pulse; an analog comparator that compares the phase with a reference voltage corresponding to the phase and outputs a pulse signal synchronized with a predetermined phase of the output signal; and a predetermined timing synchronized with the clock pulse in response to the output pulse signal of the analog comparator. a count value holding means for holding the count value of the counting means and obtaining data representing the detection target position; and a count value holding means for holding the count value in the count value holding means when the count value is held by the rising edge of the output pulse signal of the analog comparator or The predetermined phase is switched by determining whether it is the same as or later than the count period in which the falling edge occurred, and depending on this determination, the level of the reference voltage of the analog comparator is switched, whereby the analog comparator and an output stabilization circuit that provides a hysteresis characteristic to the generation condition of the output pulse signal. 2. When the output stabilization circuit determines that the count period in which the count value is held by the count value holding means is the same as the count period in which the rise or fall of the output pulse signal of the analog comparator occurs, the output stabilization circuit uses the first criterion. Claim 1 of the Utility Model Registration Claim: Selecting a voltage level, and selecting a second reference voltage level that delays the rise or fall timing of the output pulse signal of the analog comparator when it is determined that the voltage level is delayed. phase shift type position detection device. 3. The second reference voltage level delays the rise or fall timing of the output pulse signal of the analog comparator by approximately 1/4 period of the clock pulse compared to the first reference voltage level. A phase shift type position detection device according to Claim 2 of a certain utility model registration.