JPH0175398U - - Google Patents
Info
- Publication number
- JPH0175398U JPH0175398U JP1987171004U JP17100487U JPH0175398U JP H0175398 U JPH0175398 U JP H0175398U JP 1987171004 U JP1987171004 U JP 1987171004U JP 17100487 U JP17100487 U JP 17100487U JP H0175398 U JPH0175398 U JP H0175398U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- bit line
- potential
- memory device
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000003068 static effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Static Random-Access Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17100487U JPH064479Y2 (ja) | 1987-11-09 | 1987-11-09 | 半導体メモリ装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17100487U JPH064479Y2 (ja) | 1987-11-09 | 1987-11-09 | 半導体メモリ装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0175398U true JPH0175398U (enExample) | 1989-05-22 |
| JPH064479Y2 JPH064479Y2 (ja) | 1994-02-02 |
Family
ID=31462441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17100487U Expired - Lifetime JPH064479Y2 (ja) | 1987-11-09 | 1987-11-09 | 半導体メモリ装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH064479Y2 (enExample) |
-
1987
- 1987-11-09 JP JP17100487U patent/JPH064479Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH064479Y2 (ja) | 1994-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61170200U (enExample) | ||
| JPS6280897A (ja) | 半導体記憶装置 | |
| EP0262531B1 (en) | Semiconductor memory device having data bus reset circuit | |
| EP0187246A3 (en) | Precharge circuit for bit lines of semiconductor memory | |
| JPH0175398U (enExample) | ||
| US6188601B1 (en) | Ferroelectric memory device having single bit line coupled to at least one memory cell | |
| JPS6016035B2 (ja) | 増巾回路 | |
| JPH0690875B2 (ja) | 半導体記憶回路 | |
| JP2555156B2 (ja) | ダイナミックram | |
| JPH0510756B2 (enExample) | ||
| JPH0770224B2 (ja) | 同期式スタティックランダムアクセスメモリ | |
| JPH06103755A (ja) | 半導体記憶装置 | |
| JPH0152835B2 (enExample) | ||
| JPS6239298U (enExample) | ||
| JP2702265B2 (ja) | 半導体記憶装置 | |
| JPS5683887A (en) | Semiconductor storage device | |
| JPS5746390A (en) | Dummy cell circuit | |
| JPS62259294A (ja) | 半導体記憶装置 | |
| ES354131A1 (es) | Una disposicion de celula de almacenaje. | |
| JPS6431599U (enExample) | ||
| JPH01173392A (ja) | 半導体記憶装置 | |
| JPH0222469B2 (enExample) | ||
| JPH0296698U (enExample) | ||
| JPH0467298U (enExample) | ||
| JPS6122366U (ja) | ダイナミツクロジツク回路 |