JPH0172651U - - Google Patents
Info
- Publication number
- JPH0172651U JPH0172651U JP1987165883U JP16588387U JPH0172651U JP H0172651 U JPH0172651 U JP H0172651U JP 1987165883 U JP1987165883 U JP 1987165883U JP 16588387 U JP16588387 U JP 16588387U JP H0172651 U JPH0172651 U JP H0172651U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- bidirectional
- bidirectional memory
- trace
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002457 bidirectional effect Effects 0.000 claims description 9
- 239000000523 sample Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案に係るインサーキツト・エミユ
レータの一実施例を示す要部構成図、第２図は動
作を説明するためのタイムチヤートである。
１……ターゲツト・マイクロプロセツサ、２…
…メモリ、３……Ｉ／Ｏ装置、４……データ・バ
ス、５……アドレス・バス、６……制御線、７…
…双方向メモリ、８……ＣＰＵ用プローブ、９…
…双方向メモリ用プローブ、１０……第１の書き
込みタイミング回路、１１……第２の書き込みタ
イミング回路、１２……トレース・メモリ、１３
……双方向メモリ用トレース・メモリ。
FIG. 1 is a block diagram of a main part of an embodiment of an in-circuit emulator according to the present invention, and FIG. 2 is a time chart for explaining the operation. 1...Target microprocessor, 2...
...Memory, 3...I/O device, 4...Data bus, 5...Address bus, 6...Control line, 7...
...Bidirectional memory, 8...CPU probe, 9...
...Bidirectional memory probe, 10...First write timing circuit, 11...Second write timing circuit, 12...Trace memory, 13
...Trace memory for bidirectional memory.
Claims (1)
されるデータをトレース・メモリに取り込み、そ
の後そのトレース・メモリの内容を解析すること
によりターゲツト・マイクロプロセツサの動作を
調べることのできるインサーキツト・エミユレー
タにおいて、 前記ターゲツト・マイクロプロセツサが管理す
る双方向メモリのバス・データを取り出すための
双方向メモリ用プローブと、 この双方向メモリ用プローブを介して取り込ん
だ双方向メモリのバス・データに基づきサンプル
・クロツクを生成する書き込みタイミング回路と
、 前記サンプル・クロツクに基づき双方向メモリ
のバス・データが書き込まれる双方向メモリ用ト
レース・メモリと を具備したことを特徴とするインサーキツト・エ
ミユレータ。[Claims for Utility Model Registration] Investigating the operation of a target microprocessor by capturing data output to the bus of a target microprocessor into a trace memory and then analyzing the contents of the trace memory. The in-circuit emulator that can be used includes a bidirectional memory probe for retrieving bidirectional memory bus data managed by the target microprocessor, and a bidirectional memory bus data fetched via the bidirectional memory probe. An in-circuit emulator comprising: a write timing circuit that generates a sample clock based on data; and a bidirectional memory trace memory into which bus data of the bidirectional memory is written based on the sample clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987165883U JPH0172651U (en) | 1987-10-29 | 1987-10-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987165883U JPH0172651U (en) | 1987-10-29 | 1987-10-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0172651U true JPH0172651U (en) | 1989-05-16 |
Family
ID=31452771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987165883U Pending JPH0172651U (en) | 1987-10-29 | 1987-10-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0172651U (en) |
-
1987
- 1987-10-29 JP JP1987165883U patent/JPH0172651U/ja active Pending
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