JPH0157362B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a constant current circuit, and particularly to a constant current circuit that is turned on and off by a digital input signal. This relates to a constant current circuit with an I ² L structure.

I ² L is a new logic element with bipolar structure,
They have attracted a lot of attention in recent years, and are widely used in communication and measurement ICs, especially as logic elements that can coexist with linear circuits.

In addition, a so-called digital-to-analog conversion integrated circuit is used to convert digital signals to analog signals.
Since DAC is used, I ² L structure DAC is considered to be indispensable for future IC technology.

The purpose of the present invention is to meet such demands,
The object of the present invention is to provide a circuit that can obtain a constant output current through a switching operation in an IC having an I ² L structure.

A constant current circuit according to the present invention includes a first transistor with a common emitter whose collector terminal and base terminal are interconnected, and a first transistor with a common emitter whose base terminal is connected to the base terminal. The second transistor and the first transistor are of different types, and a third transistor has a common base and whose collector terminal is connected to the collector terminal of the first transistor, and a first transistor whose collector terminal is connected to the collector terminal of the third transistor, and A structure in which the base terminal of the first transistor is an input terminal, and the collector terminal of the second transistor is connected to an output terminal. The operating principle of the present invention will be summarized in accordance with an embodiment of the present invention with reference to FIG.

In Figure 1, transistor Q ₁ is a common emitter NPN transistor whose collector terminal and base terminal are interconnected, transistor Q ₂ is an emitter common NPN transistor whose base terminal is shared with transistor Q ₁ , and transistor Q ₃ is an emitter common NPN transistor. is a common-base PNP transistor connected to an external power supply through a resistor, and whose collector terminal is connected to the base terminals of transistors _Q1 and _Q2 .

The input signal is added to the base terminal 1 of the transistor Q ₁ , and the output current is the collector current I ₂ of the transistor Q ₂ .

Now, if input terminal 1 is grounded, transistors Q ₁ and Q ₂ are turned off and transistors
Collector current of Q ₂ does not flow. Also transistor
The collector current of Q ₃ flows through terminal 1 to the ground terminal.

Conversely, when terminal 1 is open, most of the collector current of transistor _Q3 flows to the ground terminal through transistor _Q1 . At this time the transistor
At the collector terminal of transistor Q ₂ , which shares a base terminal and an emitter terminal with Q ₁ , a current approximately equal to the collector current of transistor Q ₁ plus the emitter area ratio of transistors Q ₁ and Q ₂ is generated. It will flow. The collector current I ₁ of the transistor Q ₁ is approximately equal to the collector current I ₃ of the transistor Q ₃ , and I ₃ is determined by the external power supply V _cc and the resistor R according to the following equation.

I ₃ ≒V _cc −V _BE3 /R (1) However, V _BE3 is the voltage between the base and emitter terminals of the transistor Q ₃ .

Therefore, the collector current I ₂ of the transistor Q ₂ can be arbitrarily set by the resistor R from I ₂ =A ₂ /A ₁ ·V _cc −V _BE3 /R (2) assuming that V _cc is constant. However, A ₁ and A ₂ are the emitter areas of transistors Q ₁ and Q ₂ , respectively.

Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 2, three circuits shown in FIG. 1 are connected in parallel, sharing the external power supply terminal 2 and the connection terminal. Furthermore, the output transistors Q ₁₂ , Q ₂₂
The collector terminals of Q 32 and Q ₃₂ are commonly connected and connected to output terminal 3.

Now, assuming that only the input terminal 11 is open and the other input terminals 21 and 31 are grounded, the current I ₀ of the output terminal 3 is I ₀ =A ₁₂ /A ₁₁・V _cc −V _BE13 /R ₁ (3 ) becomes. However, A ₁₁ and A ₁₂ indicate the emitter areas of transistors Q ₁₁ and Q ₁₂ , respectively.

Also, if terminals 21 and 31 are open and only terminal 11 is grounded, I ₀ = A ₂₂ /A ₂₁・V _cc −V _BE23 /R ₂ +A ₃₂ /A ₃₁・V _cc −V _BE33 /R ₃ (4) becomes. However, A ₂₁ , A ₂₂ , A ₃₁ , and A ₃₂ represent the emitter areas of transistors Q ₂₁ , Q ₂₂ , Q ₃₁ , and Q ₃₂ , respectively.

As is clear from these, the resistances R ₁ and R ₂
and R ₃ values, or A ₁₂ /
It can be seen that by appropriately setting the values of A ₁₁ , A ₂₂ /A ₂₁ and A ₃₂ /A ₃₁ , a constant current output of a magnitude corresponding to the combination of input terminals to which logic signals are applied can be obtained.

Also, as shown in Figure 3, the resistors R ₁ , R ₂ and R ₃
It is also possible to replace R with a common resistor R.

As described above, according to the present invention, in the I ² L structure,
Moreover, a constant current circuit whose current value can be controlled by logic signal input can be obtained very easily.

Furthermore, it goes without saying that grounding or opening the input terminal can be accomplished by turning on and off an additional transistor or the like. Further, although FIGS. 2 and 3 illustrate the case where the number of input terminals is three, this does not limit the circuit to be configured to have any number of input terminals. Although the present invention is most suitable for devices with an I ² L structure, it can also be applied to ordinary linear transistors, or even if NPN and PNP are replaced.
Its effectiveness is obvious from its operating principle.

[Brief explanation of drawings]

1 to 3 are circuit diagrams showing first to third embodiments of the present invention, respectively. 1...Input terminal, 2...External power supply terminal, 3...
Output terminal, Q ₁ , Q ₂ ... NPN transistor, Q ₃ ...
...PNP transistor, R...resistance, _I0 ...output current, 11, 21, 31...input terminal, 2...external power supply terminal, 3...output terminal, _Q11 , _Q12 , _Q21 ,
Q ₂₂ , Q ₃₁ , Q ₃₂ ...NPN transistor, Q ₁₃ ,
Q ₂₃ , Q ₃₃ ... PNP transistor, R ₁ , R ₂ , R ₃ ...
...Resistance, I ₀ ...Output current common to Figure 2, R...Resistance.

Claims (1)

[Claims] 1. A first transistor of one conductivity type whose collector terminal and base terminal are interconnected and whose emitter is grounded; and a second transistor of one conductivity type whose base terminal is connected to the base terminal and whose emitter is grounded. and a third transistor of an opposite conductivity type whose collector terminal is connected to the collector terminal of the first transistor and whose base is grounded;
a resistor having a first terminal connected to the emitter terminal of the transistor and a second terminal connected to an external power supply, the base terminal of the first transistor being an input terminal, and the collector of the second transistor A constant current circuit characterized in that a terminal is connected to an output terminal.