JPH0155768B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides an inflow system in which the current ratio of current flowing out or flowing in from an output terminal depending on the state of a control signal does not change depending on the output terminal voltage. This relates to an outflow current generation circuit.

[Prior art]

FIG. 1 shows a conventional inflow/outflow current generation circuit. In this circuit, Q1 and Q2 are first and second transistors with the same emitter size and whose respective bases are connected to the same bias power supply Vb. Therefore, the collector current of transistor Q1
The following relationship holds between I1 and collector current I2 of transistor Q2.

I1=I2...(1) Q3 and Q4 are the third and fourth transistors that have the same base-to-emitter voltage and have an emitter area ratio of 1:n, and the collector current of transistor Q3 is If the collector current of Q4 is I4, the following equation holds true.

I4=nI3 (2) Furthermore, if the base current of the fifth transistor Q5 can be ignored, the following equation holds true.

I1=I3...(3) Therefore, when there is no control signal input and the sixth transistor Q6 is in the OFF state, the output
Io=I4-I2, that is, a current of (n-1)I1 flows out.

On the other hand, there is a control signal input, and the transistor Q
When Q6 is on, the current from transistor Q4 disappears, so Ii=I2, that is, the power of I1 flows into the output.

Therefore, the ratio of the inflowing current Ii to the outflowing current Io is 1:(n-1).

The above is a general explanation of the operation of the circuit shown in FIG. Depending on the effect, the current ratio of transistors Q1 and Q2 and the current ratio of transistors Q3 and Q4 will be the output voltage.
It will depend on Vout.

Next, let us consider how much the above current ratio changes due to this effect.

Assume that the Early effect of the NPN transistors Q1 and Q2 is that the above current ratio shifts by α every time the voltage between the collector and emitter changes by 1V. On the other hand, as an Early effect of the PNP transistors Q3 and Q4, it is assumed that the above current ratio shifts by β every time the voltage between the collector and emitter changes by 1V.

The voltage between the base and emitter of each transistor is
Vbe, and if the forward voltage drop of diode D1 is Vf, the voltage between the collector and emitter of transistor Q1 is Vcc-2Vbe, while transistor Q2
The collector-emitter voltage of is Vout. Therefore, the following equation holds.

I2={1+(Vout-Vcc+2Vbe)α}I1...(4) Also, the voltage between the collector and emitter of transistor Q3 is 2Vbe, and the voltage between the collector and emitter of transistor Q4 is Vcc-Vf-Vout.
Therefore, the following equation holds.

I4=n{1+(Vcc−Vf−Vout−2Vbe)β}I3
...(5) Therefore, the ratio between the outflow current Io and the inflow current Ii is as follows.

Io/Ii=I4-I2/I2 =n{1+(Vcc-Vf-Vout-2Vbe)β/1+(Vout
−Vcc+2Vbe)α−1 (n−1) {1+n/n−1(Vcc−Vf−Vout −2Vbe)β−(Vout−Vcc+2Vbe)α}
...(6) However, I3≒I1 The values of α and β are usually on the order of 1%/V, so the ratio of outflow current Io and inflow current Ii is 2.
It will change on the order of %/V. Therefore, when various control circuits are connected to the output terminal of this circuit, there is a problem that the performance of the control circuit is impaired due to fluctuations in the output terminal voltage.

[Summary of the invention]

The present invention has been made in view of these points,
first and second transistors each having a base and emitter commonly connected; and third and fourth transistors each having a base and emitter commonly connected and each collector connected to the collectors of the first and second transistors.
In the inflow/outflow current generation circuit, the inflow/outflow current generation circuit is configured to control the collector current of the fourth transistor to obtain an inflow/outflow current from an output terminal connected to the collector of the second transistor. At the collector of the second transistor, an input impedance reduces its input current to zero.
By connecting a buffer circuit with a high voltage gain that is as high as It is an object of the present invention to provide an inflow/outflow current generation circuit that can make the ratio of outflow currents independent of the value of the output terminal voltage.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 shows an inflow/outflow current generation circuit according to an embodiment of the present invention, and in the figure, Q1 is of the first conductivity type whose base is connected to the bias power supply Vb.
The first NPN transistor Q2 is a second NPN whose base is connected to the bias power supply Vb and whose emitter is connected to the emitter of the transistor Q1.
The transistor Q3 has a collector connected to the collector of the transistor Q1, and a second transistor whose collector and base are connected via the base and emitter of the transistor Q5 (emitter follower circuit).
A conductivity type, ie, PNP, transistor Q4 has a common base and emitter with this transistor Q3, and a fourth transistor whose collector is connected to the collector of the transistor Q2 through a diode D1.
11 is a PNP transistor whose input is connected to the collector of transistor Q2; 12 is a buffer circuit with very high input impedance and no voltage gain; 12 is composed of two diodes D2 and D3 connected in series; the output of buffer circuit 11 is This is a level shift circuit that shifts the voltage by a fixed value (2Vf), and its output is connected to the emitters of the transistors Q3 and Q4. By controlling the collector of the transistor Q4 with the transistor Q6, inflow or outflow currents Ii and Io are obtained at the output terminal connected to the collector of the transistor Q2. Further, the transistors Q3 and Q4 have the same base-to-emitter voltage, and have an emitter area ratio of 1:n.

In this embodiment, the power supply voltage of the mirror circuit (the emitter voltage of transistors Q3 and Q4) is connected to the output Vout of the buffer circuit 11 by the level shift circuit 12.
The sum of the forward voltage drops of the diodes D2 and D3 is Vout+2Vf. Here transistor Q
The voltage between the collector and emitter of transistor Q is
The value obtained by subtracting the base-emitter overvoltage Vbe of transistor Q3 and the base-emitter voltage Vbe of transistor Q5 from the emitter voltage Vout+2Vf of transistor Q4, ie, Vout+2Vf-2Vbe. The forward voltage drop Vf of the diode is the base of the transistor,
Since it is equal to the emitter voltage Vbe, the transistor Q
The voltage between the collector and emitter of 1 is Vout,
On the other hand, since the voltage between the collector and emitter of transistor Q2 is also Vout, transistors Q1 and Q2
The voltage between the collector and emitter of is always the same regardless of the value of the output voltage Vout. Therefore, the following equation holds true even when the Early effect is taken into account.

I2=I1 (7) Also, the voltage between the collector and emitter of transistor Q3 is 2Vbe, the voltage between the collector and emitter of transistor Q4 is Vf, and the following equation holds true.

I4=n{1-(2Vbe-Vf)β}I3...(8) Therefore, the ratio of the outflow current Io to the inflow current Ii is as follows.

Io/Ii=I4-I2/I2 =n{1-(2Vbe-Vf)β}-1...(9) Equation (9) shows that the ratio of inflow current Ii to outflow current Io is the output voltage
This shows that it is unrelated to the value of Vout.

In this embodiment circuit, a buffer circuit 11 having a very high input impedance and no voltage gain is connected to the collector of the transistor Q2 to which the output terminal is connected, and the output voltage of the buffer circuit 11 is set to a predetermined value. Since the voltage is shifted by the voltage and applied to the emitters of the transistors Q3 and Q4, the ratio of the inflow and outflow currents obtained at the output terminal can be made independent of the value of the output voltage. The fact that this current ratio is constant regardless of the output voltage means that, for example, the performance of a circuit that connects a capacitor to the output terminal to perform an integration function can be improved.

〔Effect of the invention〕

As described above, according to the present invention, the collectors of the first and second transistors, whose bases and emitters are commonly connected, are connected to the collectors of the third and fourth transistors, whose bases and emitters are commonly connected. In the inflow/outflow current generation circuit, the inflow/outflow current generation circuit is configured to control the collector current of the fourth transistor to obtain an inflow/outflow current to the output terminal connected to the collector of the second transistor. A buffer circuit whose input impedance is high enough to make its input current 0 and has no voltage gain is connected to the collector of the second connected transistor, and the output potential of this buffer circuit is shifted by a predetermined voltage. The above 3rd and 4th
Since the current ratio between the inflow and outflow currents can be kept constant regardless of the output terminal voltage, the performance of various circuits connected to the output terminal can be improved. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional inflow/outflow current generation circuit, and FIG. 2 is a block diagram of an inflow/outflow current generation circuit according to an embodiment of the present invention. Q1...first transistor, Q2...second transistor, Q3...third transistor, Q
4... Fourth transistor, Q5... Emitter follower circuit, Vb... Bias power supply, 11...
Buffer circuit, 12...Level shift circuit. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first transistor of a first conductivity type whose base is connected to a bias power source; and a first transistor of a first conductivity type whose base and emitter are commonly connected to the base and emitter of the first transistor. a second transistor; a third transistor of a second conductivity type, the collector of which is connected to the collector of the first transistor; the base of which is connected to the collector of the third transistor; a fourth transistor of the second conductivity type, the collector of which is connected in common with the collector of the second transistor;
a buffer circuit whose input is connected to the collector of the second transistor and whose input impedance is so high as to make the input power supply 0 and has no voltage gain, and which shifts the output potential of the buffer circuit by a predetermined value. a level shift circuit for applying a current control signal to the emitters of the third and fourth transistors; a control signal input terminal for applying a current control signal to the collector of the fourth transistor;
An inflow/outflow current generating circuit comprising: an output terminal taken out from the collector of the second transistor to obtain an inflow or outflow current to the circuit according to the control signal. 2. The inflow/outflow current generation circuit according to claim 1, wherein the base of the third transistor is connected to its collector via an emitter follower circuit.