JPH0154913B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a peak detection circuit suitable for use in an ACC circuit of a home VTR.

In a home VTR, the color signal is band-converted to the lower frequency band of the FM-modulated luminance signal and then recorded and reproduced. At this time, if the recording level of the color signal is too low, the S/N ratio will be poor, and if the recording level of the color signal is too high, the interference given to the luminance signal system cannot be ignored. As described above, there is an optimum value for the recording level of the color signal, and the maximum level of the color signal is usually set to be about -14 dB with respect to the recording level of the luminance signal. Therefore, an ACC circuit is essential in order to keep the input color signal level close to this optimum value even if the input color signal level varies.
During playback, the playback video signal is generally converted into a high frequency signal by an RF converter and then input from the TV tuner. In order not to deteriorate N, it is necessary to keep the addition ratio of the luminance signal and the color signal almost constant. Therefore, during playback,
ACC that reduces variations in reproduced color signal levels
A circuit is required. This ACC circuit is generally a circuit that detects the p-p value of a burst signal and controls the gain to keep it at a constant level. In order to detect the p-p value of this burst signal, conventionally, only the burst signal is separated from the color signal.
This was detected by peak detection. For this reason, for example, when using an integrated circuit, a circuit such as that shown in FIG. 1 has been used. In FIG. 1, 1 is a first input terminal to which a color signal is input, 2 is a second input terminal to which a burst gate pulse is input, 3 is an output terminal, and 4 is a second input terminal to which a burst gate pulse is input.
is a burst extraction circuit that extracts only burst signals,
5 is a peak detection circuit, C1 to C3 are capacitors, and E1 to C3 are capacitors.
E4 is a constant voltage source, Q1 to Q11 are transistors,
R1 to R10 are resistors.

Next, the operation shown in FIG. 1 will be briefly explained with reference to the waveform diagram shown in FIG. 2.

A color signal is input from the first input terminal. On the other hand, a burst gate pulse as shown in b is inputted from the second input terminal 2. Therefore, b
During the period when the pulse is at a high level, that is, during the burst signal period, the base potential of the transistors Q2 and Q3 becomes higher than the base potential of the transistors Q1 and Q4, so the collector current of the transistor Q2, that is, the transistor Q5 flows through the resistor R5.
Since the color signal is input to the base of the transistor Q5, a signal in this period, that is, a burst signal period, that is, a burst signal is output. On the other hand, during the period when the b pulse is at a low level, the base potentials of the transistors Q1 and Q4 become higher, so the collector current of the transistor Q4, that is, the transistor Q6 flows through the resistor R5. Since only a DC voltage is applied to this transistor Q6, a DC voltage is output during this period, that is, during the video signal period. Since the same DC bias is applied to transistors Q5 and Q6, the resistance
If the resistance values of R ₁ and R ₂ are made equal, the output DC voltage will be the same in these two periods, so only the burst signal is output to the emitter of transistor Q7 as shown in c. Capacity C2 transistor Q
8 is a clamp circuit for clamping the peak on the negative side of the DC bias of this output signal, and as a result, the negative peak of the burst signal is (E3) at the base of the transistor Q9, as shown in d.
−υ _be )V (here, υ _be is the base-emitter voltage of transistor Q8, which is approximately 0.7 V). Transistors Q9 and Q10 constitute a differential amplifier, and when the base voltage of transistor Q9 becomes higher than the base voltage of transistor Q10,
Collector current flows through transistor Q9, so collector current flows through transistor Q11,
Charge the capacitor C3 and increase the DC voltage. In other words, the p-p value of the burst signal supplied from the emitter of transistor Q7 is {E4-(E3-υ _be }V
When it is larger than {E4-(E3-υ be)}V, the DC voltage at the output terminal 3 is increased, but when it is smaller than {E4-(E3-υ _be )}V, only the resistor R10 is discharged, and the DC voltage at the output terminal 3 is decreased.

Therefore, if this output 3 controls a variable gain amplifier (not shown), transistor Q7
The p-p value of the burst signal at the emitter section of is approximately {E4-{E3-υ _be )}V.

In this way, the conventional peak detection circuit for ACC requires a burst sampling circuit, and if this circuit is not provided, when a color signal larger than the burst signal comes in during the video signal period, the pp value of this color signal will be It is controlled so that {E4-(E3-υ _be )}V. Furthermore, if the DC voltage changes by more than the pp value of the burst signal between the burst signal period and the video signal period, this burst sampling circuit will be controlled by this DC voltage change and will not operate normally. Therefore, the burst sampling circuit used in the integrated circuit requires a circuit as shown in FIG. 1, or a circuit as complex as that shown in FIG.

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, eliminate the need for a complicated burst signal extraction circuit, and
An object of the present invention is to provide a peak detection integrated circuit suitable for use in an ACC circuit of a home VTR.

Therefore, in the present invention, the DC voltage for clamping is increased only during the burst signal period so that the negative side clamp in the peak detection circuit works only with the burst signal.
The differential amplifier is also configured to operate only during the burst signal period, and the peak detection circuit is configured so that it does not operate at all even if a color signal larger than the burst signal is input.

Next, an embodiment of the present invention is shown in FIG. In FIG. 3, R11 and R12 are resistors, and Q12 is a transistor. FIG. 4 is a diagram showing an example of waveforms at each part in FIG. 3. Next, the operation of the present invention will be explained using FIGS. 3 and 4.

The burst gate pulse shown in FIG. 4a is input from the second input terminal 2. Therefore, the base of the transistor Q8, to which a constant DC bias E3 was conventionally always applied, is at 0V during the period when the burst gate pulse is at a high level, that is, during the burst signal period E3, and during the other video signal periods. Therefore, the negative peak of the burst signal is E3-
When it becomes lower than υ _be , transistor Q8 becomes conductive,
Capacitor C2 is charged and the negative side of the burst signal is clamped to voltage E3-υ _be . If the voltage E3-υ _be is sufficiently high, even if a color signal larger than the burst signal is input during the video signal period, the emitter of transistor Q8 will not fall below 0V, so the base and emitter of transistor Q8 will always be reverse biased. become a state. Therefore, since a loop for charging and discharging the capacitor C2 is not possible, the negative side of the burst signal of the color signal at the emitter of transistor Q8 is equal to the voltage E.
It remains clamped at 3-υ _be and is no longer affected by the video signal.

On the other hand, the transistor Q12 is made conductive only during the burst signal period by the burst gate pulse inputted from the second input terminal 2, and the operating current of the transistors Q9 and Q10 forming the differential amplifier flows. Therefore, during this period, if the base voltage of transistor Q9 is higher than the base voltage of transistor Q10, a current flows to the collector of transistor Q9, increasing the DC voltage at output terminal 3, as described above.
During the video signal period, transistor Q12 is non-conductive and no operating current flows through transistors Q9 and Q10. Therefore, even if the base voltage of transistor Q9 is higher than the base voltage of transistor Q10, no current flows to the collector of transistor Q9. . Therefore, even if a color signal larger than the burst signal is input during the video signal period, the DC voltage at the output terminal 3 is not affected at all. In this way, the peak detection circuit of the present invention operates only on the pp value of the burst signal even if the color signal is input as is.

In the example shown in FIG. 3, the base and emitter of transistor Q9 are reverse biased except during the positive peak of the burst, and no current flows between the base and emitter. Therefore, the collector junction saturation current flows into the base and charges the capacitance C2, which affects the clamping operation of the transistor Q8. Since this collector junction saturation current strongly depends on temperature (increases approximately twice for every 10° C. rise), the clamping ability of transistor Q8 has temperature characteristics, and the output level of the ACC circuit changes depending on temperature. To prevent this,
As shown in FIG. 5, it is effective to insert one stage of emitter follower circuit between the clamp section and the differential amplifier.

Further, the base of the transistor Q8 does not need to be lowered to 0V during the video signal period, but may be set sufficiently lower than the burst signal period so that clamping does not occur during the video signal period. Further, in the above example, the clamp voltage during the burst signal period is directly applied by the high level of the burst gate pulse, but this is of course only an example, and the clamp voltage can be changed in various ways. For example, as shown in Figure 6, a resistor _R15 is inserted between the reference voltage and the base of the transistor Q8, and a pulse of opposite polarity to the burst gate pulse shown in Figure 7b is used, and the resistor R15 is connected only during the signal period. Of course, it is also possible to apply a current to the base of the transistor Q3 so that the voltage E3 is applied during the burst signal period and the lower voltage R16/R15+R16E3 is applied during the signal period.

Also, the on/off of the current of the differential amplifier is shown in Figure 3.
Instead of the shape shown in the example of FIG. 5, the resistor R1 is connected to the emitter of the transistor Q15 as shown in FIG.
Needless to say, various methods are possible, such as inserting a transistor Q15 and turning the current ON and OFF in such a way that the operating current is determined by the voltage applied to the transistor Q15 and the resistor R19.

As explained above, the peak detection circuit of the present invention changes the clamp voltage of the clamp circuit between the burst signal period and the video signal period, and operates the subsequent differential amplifier only during the burst signal period, so the burst signal is separated and supplied. This eliminates the need for a complicated burst extraction circuit, and allows for an inexpensive integrated circuit with less chip area.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional peak detection circuit for an ACC circuit, FIGS. 2 a to e are waveform diagrams showing waveform examples of each part of FIG. 1, and FIG. 4a and 4b are waveform diagrams showing waveform examples of each part of FIG. 3, FIG. 5 is a circuit diagram showing the second embodiment of the present invention, and FIG. FIGS. 7a and 7b are waveform diagrams showing examples of waveforms at various parts in FIG. 6. 1...First input terminal, 2...Second input terminal, 3...Output terminal, Q8, Q9, Q11, Q1
2...Transistor, C2, C3...Capacity, R
8, R9, R10, R11, R12...Resistance, E
4... Constant voltage source.

Claims (1)

[Claims] 1 A first input terminal to which a burst gate pulse is input, a second input terminal to which a color signal including a burst signal is input, a base is connected to the first input terminal, and a capacitor is connected to the second input terminal. a clamp circuit that clamps the burst signal of the color signal by a burst gate pulse, and a pair of second and third transistors;
A color signal including the burst signal clamped by the above-mentioned clamp circuit is supplied to the base of one of the transistors, a differential amplifier that amplifies the burst signal, and a burst gate pulse are input, and conduction is performed by the burst gate pulse. A fourth transistor supplies an emitter current to the second and third transistors of the differential amplifier, and the burst signal amplified by the differential amplifier is supplied, and peak detection of the burst signal is performed to generate a DC voltage. A peak detection circuit comprising a DC voltage generation circuit.