JPS63141487A - Automatic chroma saturation control circuit - Google Patents

Automatic chroma saturation control circuit

Info

Publication number
JPS63141487A
JPS63141487A JP61287902A JP28790286A JPS63141487A JP S63141487 A JPS63141487 A JP S63141487A JP 61287902 A JP61287902 A JP 61287902A JP 28790286 A JP28790286 A JP 28790286A JP S63141487 A JPS63141487 A JP S63141487A
Authority
JP
Japan
Prior art keywords
circuit
peak detection
control circuit
bias voltage
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61287902A
Other languages
Japanese (ja)
Inventor
Akihiro Yoshizawa
昭浩 吉澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61287902A priority Critical patent/JPS63141487A/en
Publication of JPS63141487A publication Critical patent/JPS63141487A/en
Pending legal-status Critical Current

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  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To reduce power consumption by activating a peak detection bias voltage circuit only for a burst signal period. CONSTITUTION:A bias circuit driving control circuit 9 is added to a peak detection bias voltage circuit 3. A control pulse is inputted from an input terminal 10 to a bias circuit driving control circuit 9 and only when the control pulse exists in the burst signal period at a high level, the peak detection bias circuit 3 is operated. The peak detection circuit 4 detects only the burst signal component among the inputted chrominance signal component and gives the addition of the peak detection reference bias from the peak detection bias voltage circuit 3 to the peak value holding circuit 6. The output of the peak value holding circuit 6 is given to a hand amplifying circuit 2 via a comparison control circuit 7 to control the amplification gain.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はテレビジョン機器等の色復調回路に用いられる
自動彩度制御回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an automatic saturation control circuit used in color demodulation circuits of television equipment and the like.

従来の技術 近年、液晶テレビなどの携帯用テレビが発売され、今後
さらに拡大されると考えられる。携帯用テレビの課題の
ひとつに消費電力を低く押さえることが重要であり、と
りわけテレビジョン機器に使用されている種々のICの
消費電力を少なくすることが重要とされている。そのな
かで色復調回路に用いられる自動彩度制御回路は電力消
費が犬21・−/ きい回路のひとつに挙げられている。
BACKGROUND OF THE INVENTION In recent years, portable televisions such as liquid crystal televisions have been released, and it is expected that their use will further expand in the future. One of the challenges of portable televisions is to keep power consumption low, and in particular, it is important to reduce the power consumption of various ICs used in television equipment. Among these, the automatic saturation control circuit used in the color demodulation circuit is listed as one of the circuits with the highest power consumption.

以下、図面を参照しながら、上述したような従来の自動
彩度制御回路について説明を行う。
The conventional automatic saturation control circuit as described above will be described below with reference to the drawings.

第3図は従来の自動彩度制御回路のブロック図を示すも
のである。第3図において、2は入力信号を増幅して出
力する帯域増幅回路、3はピーク検波基準電圧を出力す
るピーク検波ノくイアスミ圧回路14はバースト信号振
幅の大きさを検出するピーク検波回路16はピーク検波
された出力信号を保持するピーク値保持回路、7は検出
されたピーク電圧値に応じて帯域増幅回路の増幅利得を
制御する比較制御回路である。同図において自動彩度制
御回路は、 ピーク検波バイアス電圧回路3゜ピーク検
波回路4.ピーク値保持回路6.比較制御回路7から成
っている。
FIG. 3 shows a block diagram of a conventional automatic saturation control circuit. In FIG. 3, 2 is a band amplification circuit that amplifies and outputs the input signal, 3 is a peak detection circuit that outputs a peak detection reference voltage, and IASMI pressure circuit 14 is a peak detection circuit 16 that detects the magnitude of the burst signal amplitude. 7 is a peak value holding circuit that holds the peak-detected output signal, and 7 is a comparison control circuit that controls the amplification gain of the band amplification circuit in accordance with the detected peak voltage value. In the figure, the automatic saturation control circuit includes: peak detection bias voltage circuit 3. peak detection circuit 4. Peak value holding circuit6. It consists of a comparison control circuit 7.

以上のように構成された自動彩度制御回路について、以
下その動作について説明する。
The operation of the automatic saturation control circuit configured as above will be described below.

まず第3図において、入力端子1より色信号が入力され
帯域増幅回路2で信号増幅された色信号が出力される。
First, in FIG. 3, a chrominance signal is inputted from an input terminal 1, and the chrominance signal amplified by a band amplification circuit 2 is outputted.

帯域増幅回路2から出力された色3 ′ −・ 信号は出力端子8とピーク検波回路4とへ送られる。ピ
ーク検波回路4では、入力された色信号成分の内、バー
スト信号成分のみを1パルス入力端子5から入力される
バースト信号抜き取り制御信号により、色信号より分離
して取り出す。取り出された信号成分はピーク検波基準
バイアス電圧に加えられピーク値を検出され検波電圧信
号が出力される。ピーク検波基準バイアス電圧は、ピー
ク検波バイアス電圧回路3で作り出される。ピーク検波
バイアス電圧回路3は電源電圧変動など種々の変動に対
して安定なバイアス電圧を出力する回路である。ピーク
検波回路4より出力された検波電圧信号はピーク値保持
回路6で映像信号の1H期間保持され1比較制御回路7
に検波電圧信号を伝える。比較制御回路7に伝えられた
検波電圧信号は、比較制御回路γ内の比較基準電圧と比
較され、比較結果に応じた制御信号が出力される。出力
された制御信号は帯域増幅回路の増幅利得を制御し入力
信号振幅変動にかかわらず常に安定した信号を出力端子
14に出力する。
The color 3'-- signal output from the band amplifier circuit 2 is sent to the output terminal 8 and the peak detection circuit 4. In the peak detection circuit 4, among the input color signal components, only the burst signal component is separated from the color signal and extracted by a burst signal extraction control signal input from the one-pulse input terminal 5. The extracted signal component is added to the peak detection reference bias voltage, the peak value is detected, and a detected voltage signal is output. The peak detection reference bias voltage is generated by the peak detection bias voltage circuit 3. The peak detection bias voltage circuit 3 is a circuit that outputs a stable bias voltage against various fluctuations such as power supply voltage fluctuations. The detected voltage signal outputted from the peak detection circuit 4 is held in the peak value holding circuit 6 for 1H period of the video signal, and then sent to the comparison control circuit 7.
The detected voltage signal is transmitted to the The detected voltage signal transmitted to the comparison control circuit 7 is compared with a comparison reference voltage within the comparison control circuit γ, and a control signal according to the comparison result is output. The output control signal controls the amplification gain of the band amplification circuit and always outputs a stable signal to the output terminal 14 regardless of input signal amplitude fluctuations.

発明が解決しようとする問題点 しかしながら、上記のよう々構成では、消費電力が大き
いため低消費電力用映像処理ICにとって適当なもので
はなかった。
Problems to be Solved by the Invention However, the above configuration consumes a large amount of power and is therefore not suitable for a low power consumption video processing IC.

本発明は上記問題点に鑑み、従来の構成回路の消費電力
に比べ大幅に電力削減をすることのできる自動彩度制御
回路を提供するものである。
In view of the above problems, the present invention provides an automatic saturation control circuit that can significantly reduce power consumption compared to conventional component circuits.

問題点を解決するための手段 上記目的を達成するだめに本発明の自動彩度制御回路は
、制御回路内で最も大きな電力消費をしているピーク検
波バイアス電圧回路に駆動制御回路を設はバースト信号
期間のみ前記バイアス電圧回路を前記駆動制御回路によ
って動作させるという構成を備えたものである。
Means for Solving the Problems In order to achieve the above object, the automatic saturation control circuit of the present invention uses a burst drive control circuit in which a drive control circuit is installed in the peak detection bias voltage circuit that consumes the largest amount of power in the control circuit. The bias voltage circuit is configured to be operated by the drive control circuit only during the signal period.

作用 本発明は上記した構成によって、駆動制御回路の入力端
子に印加されるパルス信号で駆動制御回路を動作させピ
ーク検波バイアス電圧回路の動作をバースト信号期間と
し、バースト信号期間外は動作を停止させることにより
、前記ピーク検波バ5 ・・−フ イアスミ圧回路の消費電力の時間的平均値を減少させ1
 自動彩度制御回路全体の消費電力の減少にもつながる
こととなる。
According to the above-described configuration, the present invention operates the drive control circuit with a pulse signal applied to the input terminal of the drive control circuit, operates the peak detection bias voltage circuit during the burst signal period, and stops the operation outside the burst signal period. By doing so, the time average value of the power consumption of the peak detection bar 5...--Fiasumi pressure circuit is reduced.
This also leads to a reduction in the power consumption of the entire automatic saturation control circuit.

実施例 以下本発明の一実施例について1図面を参照しながら説
明する。第1図は本発明の一実栴例における自動彩度制
御回路のブロック図を示すものである。第1図において
、1は映像色信号入力端子、2は帯域増幅回路13はピ
ーク検波バイアス電圧回路、4はピーク検波回路、5は
パルス入力端子、6はピーク値保持回路、7は比較制御
回路で1以上は第3図に示す従来例の構成と同じである
。9はバイアス回路駆動制御回路であって1パルス入力
端子10から入力されるパルス信号により、ピーク検波
バイアス電圧回路の動作制御信号を出力する回路である
。同図で、自動彩度制御回路は、帯域増幅回路2を除い
たブロック人で構成されて 。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to one drawing. FIG. 1 shows a block diagram of an automatic saturation control circuit in one practical example of the present invention. In FIG. 1, 1 is a video color signal input terminal, 2 is a band amplifier circuit 13 is a peak detection bias voltage circuit, 4 is a peak detection circuit, 5 is a pulse input terminal, 6 is a peak value holding circuit, and 7 is a comparison control circuit. 1 or more are the same as the configuration of the conventional example shown in FIG. Reference numeral 9 denotes a bias circuit drive control circuit, which outputs an operation control signal for the peak detection bias voltage circuit in response to a pulse signal input from the one-pulse input terminal 10. In the figure, the automatic saturation control circuit is composed of blocks excluding the band amplification circuit 2.

いる。There is.

以上のように構成された自動彩度制御回路について1以
下その動作について説明する。基礎的な6 ′・−・ 動作は、第2図に示されている従来の構成での動作と同
じであるので1従来の構成と異なる点について以下詳細
に説明する。従来と異なる点は1 ピーク検波バイアス
電圧回路3にバイアス回路駆動制御回路9を付加したこ
とである。第2図すに示される制御パルスをバイアス回
路駆動制御回路9にパルス入力端子10から入力させる
と、制御パルスがローレベルでピーク検波バイアス回路
3を停止させ、制御パルスがノ・イレベルで動作させる
という制御信号を出力する。制御ノくルスの幅Tは第2
図乙に示すバースト信号抜き取りノ々ルス(ノクルス入
力端子6に入力されるパルス)の幅T1 より幅T2広
いものが必要である。期間T2は、ピーク検波バイアス
電圧回路3を立ち上げ安定な状態にさせるだめの時間で
ある。したがってピーク検波バイアス電圧回路3の動作
期間はT(T、+T2  )のみとなり、消費電力の減
少へとつながる。
The operation of the automatic saturation control circuit configured as above will be described below. Since the basic operation is the same as that of the conventional configuration shown in FIG. 2, the differences from the conventional configuration will be described in detail below. The difference from the conventional method is 1. A bias circuit drive control circuit 9 is added to the peak detection bias voltage circuit 3. When the control pulse shown in FIG. 2 is inputted to the bias circuit drive control circuit 9 from the pulse input terminal 10, the control pulse stops the peak detection bias circuit 3 at low level, and operates at the control pulse at NO level. This control signal is output. The width T of the control noxle is the second
It is necessary to have a width T2 wider than the width T1 of the burst signal extraction node (pulse input to the node input terminal 6) shown in FIG. The period T2 is the time required to start up the peak detection bias voltage circuit 3 and bring it into a stable state. Therefore, the operating period of the peak detection bias voltage circuit 3 is only T (T, +T2), which leads to a reduction in power consumption.

発明の効果 以上のように本発明はピーク検波バイアス回路の動作期
間をバースト信号期間とすることにより、7 ・ −7 消費電力を削減することができ、実用的にきわめて有用
である。
Effects of the Invention As described above, the present invention makes it possible to reduce power consumption by 7·-7 by setting the operation period of the peak detection bias circuit to the burst signal period, and is extremely useful in practice.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における自動彩度制御回路を
示すブロック図1第2図a、bはバースト信号抜き取り
パルスおよびバイアス電圧回路駆動制御パルスの波形概
要図、第3図は従来の自動彩度制御回路を示すブロック
図である。 1・・・・・映像色信号入力端子、2・・・・・帯域増
幅回路、3・・・・ピーク検波バイアス電圧回路14・
・・・・・ピーク検波回路16・・・・・パルス入力端
子、6・・・・・ピーク値保持回路17・・・・・・比
較制御回路、8・・・・・・映像色信号出力端子、9・
・・・バイアス回路駆動制御回路、10・・・・・パル
ス入力端子。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第 
2 図
FIG. 1 is a block diagram showing an automatic saturation control circuit according to an embodiment of the present invention. FIG. FIG. 2 is a block diagram showing an automatic saturation control circuit. 1...Video color signal input terminal, 2...Band amplifier circuit, 3...Peak detection bias voltage circuit 14.
... Peak detection circuit 16 ... Pulse input terminal, 6 ... Peak value holding circuit 17 ... Comparison control circuit, 8 ... Image color signal output Terminal, 9.
...Bias circuit drive control circuit, 10...Pulse input terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person
2 Figure

Claims (1)

【特許請求の範囲】[Claims] ピーク検波バイアス電圧回路の駆動制御を行う駆動制御
回路を設け、バースト信号期間のみ前記ピーク検波バイ
アス電圧回路を動作させることを特徴とする自動彩度制
御回路。
An automatic saturation control circuit comprising a drive control circuit for controlling the drive of a peak detection bias voltage circuit, and operating the peak detection bias voltage circuit only during a burst signal period.
JP61287902A 1986-12-03 1986-12-03 Automatic chroma saturation control circuit Pending JPS63141487A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61287902A JPS63141487A (en) 1986-12-03 1986-12-03 Automatic chroma saturation control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61287902A JPS63141487A (en) 1986-12-03 1986-12-03 Automatic chroma saturation control circuit

Publications (1)

Publication Number Publication Date
JPS63141487A true JPS63141487A (en) 1988-06-13

Family

ID=17723197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61287902A Pending JPS63141487A (en) 1986-12-03 1986-12-03 Automatic chroma saturation control circuit

Country Status (1)

Country Link
JP (1) JPS63141487A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715593A (en) * 1980-07-02 1982-01-26 Hitachi Ltd Integrated circuit for peak detection
JPS6192093A (en) * 1984-10-12 1986-05-10 Hitachi Ltd Detecting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715593A (en) * 1980-07-02 1982-01-26 Hitachi Ltd Integrated circuit for peak detection
JPS6192093A (en) * 1984-10-12 1986-05-10 Hitachi Ltd Detecting circuit

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