JPH0153542B2 - - Google Patents
Info
- Publication number
- JPH0153542B2 JPH0153542B2 JP57028333A JP2833382A JPH0153542B2 JP H0153542 B2 JPH0153542 B2 JP H0153542B2 JP 57028333 A JP57028333 A JP 57028333A JP 2833382 A JP2833382 A JP 2833382A JP H0153542 B2 JPH0153542 B2 JP H0153542B2
- Authority
- JP
- Japan
- Prior art keywords
- facsimile signal
- input terminal
- comparator
- time constant
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimile Image Signal Circuits (AREA)
- Image Input (AREA)
Description
【発明の詳細な説明】
本発明はフアクシミリ信号二値化回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile signal binarization circuit.
従来のフアクシミリ信号二値化回路には例えば
第１図に示すものがある。図において、１は入力
端子、２は比較器、３は出力端子を示す。入力端
子１には第２図に示すフアクシミリ信号４が印加
され、この信号は比較器２の非反転入力端子
（＋）に印加されている。一方、比較器２の反転
入力端子（−）には直流電圧V1が印加されてい
る。 An example of a conventional facsimile signal binarization circuit is shown in FIG. In the figure, 1 is an input terminal, 2 is a comparator, and 3 is an output terminal. A facsimile signal 4 shown in FIG. 2 is applied to the input terminal 1, and this signal is applied to the non-inverting input terminal (+) of the comparator 2. On the other hand, a DC voltage V1 is applied to the inverting input terminal (-) of the comparator 2.
前記直流電圧V1を第２図のV1aに設定した時、
比較器２の出力端子に接続された出力端子３には
第２図に示す出力信号５が出力される。この時フ
アクシミリ信号４の中で４ａ及び４ｂは出力信号
５ａ，５ｂの如く白黒の情報として二値化される
が信号４ｃは出力信号５ｃのようになり、信号４
ｃの変化がなくなつてしまう。 When the DC voltage V 1 is set to V 1 a in FIG. 2,
An output signal 5 shown in FIG. 2 is output to an output terminal 3 connected to the output terminal of the comparator 2. At this time, in the facsimile signal 4, 4a and 4b are binarized as black and white information like output signals 5a and 5b, but signal 4c becomes output signal 5c, and signal 4
The change in c disappears.
又、比較器２の反転入力端子（−）に印加され
る電圧をV1bに設定すると、出力端子３には出力
信号６を生じる。この場合には信号４ａ及び４ｃ
は出力信号６ａ，６ｃの如く白黒の情報として二
値化されるが、信号４ｂは出力信号６ｂに示すよ
うに全くなくなつてしまう。 Further, when the voltage applied to the inverting input terminal (-) of the comparator 2 is set to V 1 b, an output signal 6 is generated at the output terminal 3. In this case signals 4a and 4c
is binarized as black and white information like the output signals 6a and 6c, but the signal 4b completely disappears as shown in the output signal 6b.
以上のように従来のフアクシミリ装置の二値化
回路では、第２図のフアクシミリ信号４が入力さ
れた時、反転入力端子（−）の電圧を変えること
により出力信号５又は６を得るが、同じ状態で信
号４ｂ及び４ｃを二値化信号として取り出すこと
が出来ない欠点があつた。 As described above, in the binarization circuit of the conventional facsimile device, when the facsimile signal 4 shown in Fig. 2 is input, the output signal 5 or 6 is obtained by changing the voltage of the inverting input terminal (-), but the output signal 5 or 6 is the same. There was a drawback that the signals 4b and 4c could not be extracted as binary signals in this state.
本発明の目的は、フアクシミリ信号にレベルの
違いがあつても正しく二値化動作できるようにし
たフアクシミリ信号二値化回路を提供することに
ある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a facsimile signal binarization circuit that can perform a correct binarization operation even if there is a difference in level of the facsimile signal.
本発明ののフアクシミリ信号二値化回路は、白
情報と黒情報を有するアナログのフアクシミリ信
号を一方の入力端に入力する比較器と、抵抗およ
びコンデンサを並列に接続し、その一方の接続部
を前記比較器の他方の入力端に接続した時定数回
路と、前記一方の入力端と前記一方の接続部との
間に接続したダイオードとを具備し、前記時定数
回路の他方の接続部に、前記フアクシミリ信号の
白レベルから所定量だけ黒レベル側に離れた電位
を与え、前記時定数回路の時定数を前記フアクシ
ミリ信号の最高画周波数の１〜３サイクル分と
し、前記黒情報のピーク値の変動にかかわらず、
そのピーク値よりも所定量だけ白レベル側に離れ
た電位を前記他方の入力端に与えて前記フアクシ
ミリ信号と比較して二値化出力を得るようにした
ことを特徴とする。 The facsimile signal binarization circuit of the present invention has a comparator that inputs an analog facsimile signal having white information and black information to one input terminal, and a resistor and a capacitor connected in parallel, and one connection point of the comparator is connected in parallel. a time constant circuit connected to the other input end of the comparator; and a diode connected between the one input end and the one connection part, the other connection part of the time constant circuit having: Applying a potential that is a predetermined amount away from the white level of the facsimile signal toward the black level, setting the time constant of the time constant circuit to 1 to 3 cycles of the highest image frequency of the facsimile signal, and increasing the peak value of the black information. Regardless of fluctuations,
The present invention is characterized in that a potential that is a predetermined amount away from the peak value toward the white level is applied to the other input terminal and compared with the facsimile signal to obtain a binary output.
以下に本発明の一実施例について図面を参照し
て説明する。第３図は本発明の一実施例であつ
て、１〜３は第１図と同様のものであり、７はダ
イオード、８は抵抗、９はコンデンサを示す。入
力端子１にはダイオード７のアノード側及び比較
器２の非反転入力端子（＋）が接続されており、
前記ダイオード７のカソード側には前記比較器２
の反転入力端子（−）、抵抗８及びコンデンサ９
が接続され、前記抵抗８及びコンデンサ９の他方
の電極はお互いに接続され、その接続点にはV2
なる電圧が印加されている。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows an embodiment of the present invention, in which 1 to 3 are similar to those in FIG. 1, 7 is a diode, 8 is a resistor, and 9 is a capacitor. The anode side of the diode 7 and the non-inverting input terminal (+) of the comparator 2 are connected to the input terminal 1.
The comparator 2 is connected to the cathode side of the diode 7.
Inverting input terminal (-), resistor 8 and capacitor 9
are connected, the other electrodes of the resistor 8 and capacitor 9 are connected to each other, and the connection point has V 2
A voltage is applied.
第４図は第３図の動作を示す波形図であつて、
４は第２図と同じフアクシミリ信号であり、波形
の下側は白レベル、上側は黒レベルを示してお
り、一走査中のある特定の区間について示してい
る。１０は出力端子３の出力を示す。 FIG. 4 is a waveform diagram showing the operation of FIG. 3,
4 is the same facsimile signal as in FIG. 2, the lower part of the waveform shows the white level, and the upper part shows the black level, and shows a certain section during one scan. 10 indicates the output of the output terminal 3.
入力端子１にフアクシミリ信号４が印加される
と、フアクシミリ信号が白レベルの時には比較器
２の反転入力端子（−）には抵抗８を通してV2
なる電圧が印加されている。フアクシミリ信号４
中の信号４ａが印加されると、コンデンサ９はダ
イオード７を通してただちに充電され、その電圧
V3はダイオード７の電圧降下による電圧VDだけ
低い電圧に達する。 When the facsimile signal 4 is applied to the input terminal 1, when the facsimile signal is at the white level, V 2 is applied to the inverting input terminal (-) of the comparator 2 through the resistor 8.
A voltage is applied. facsimile signal 4
When the signal 4a inside is applied, the capacitor 9 is immediately charged through the diode 7 and its voltage
V 3 reaches a voltage lower by the voltage V D due to the voltage drop across the diode 7.
前記フアクシミリ信号４ａが白レベルになる
と、コンデンサ９に充電された電荷は抵抗８を通
して放電される。この時、抵抗８及びコンデンサ
９により決定される放電時定数を最高画周波数の
１〜３サイクル程度に設定する。この結果、コン
デンサ９に充電された電荷は第４図の点線に示す
如く短時間で白レベルに接近するように下降し、
V2で一定になる。 When the facsimile signal 4a becomes white level, the charge stored in the capacitor 9 is discharged through the resistor 8. At this time, the discharge time constant determined by the resistor 8 and capacitor 9 is set to about 1 to 3 cycles of the highest image frequency. As a result, the electric charge charged in the capacitor 9 drops to approach the white level in a short time as shown by the dotted line in FIG.
It becomes constant at V 2 .
次にフアクシミリ信号が４ｂの如く振幅が小さ
くなつた場合、前記フアクシミリ信号４ｂが黒レ
ベルに向つて上つた時には、そのレベルからダイ
オード７の電圧降下のVDだけ引いた電圧がコン
デンサ９に充電される。この時にはフアクシミリ
信号４ｂの黒レベルが低いためコンデンサ９に充
電される電荷も少なく、コンデンサ９の端子電圧
は電圧V2からあまり変化しない。又、フアクシ
ミリ信号４が信号４ｃの如く白レベルが下がらな
い場合、フアクシミリ信号４ｃが黒レベルになつ
た時には４ａ，４ｂの場合と同様にしてコンデン
サ９にはダイオード７の電圧降下分VDだけ低い
電圧が現われ、黒レベルが下がつた時には点線の
如くコンデンサ９の端子電圧も下がる。 Next, when the amplitude of the facsimile signal 4b becomes small as shown in 4b, when the facsimile signal 4b rises toward the black level, the capacitor 9 is charged with a voltage subtracted by the voltage drop V D of the diode 7 from that level. Ru. At this time, since the black level of the facsimile signal 4b is low, the charge charged to the capacitor 9 is small, and the terminal voltage of the capacitor 9 does not change much from the voltage V2 . Also, if the white level of the facsimile signal 4 does not drop as in the signal 4c, when the facsimile signal 4c reaches the black level, the voltage drop across the capacitor 9 is lowered by the voltage drop V D across the diode 7, as in the case of 4a and 4b. When the voltage appears and the black level drops, the terminal voltage of the capacitor 9 also drops as shown by the dotted line.
以上のようにしてコンデンサ９の両端にはフア
クシミリ信号４の黒レベルの振幅に応じて変化す
る電圧１１を生じる。この信号は比較器２の反転
入力端子（−）に印加されているため、比較器２
の出力端子には第４図に示す出力１０が得られ
る。すなわち、フアクシミリ信号４の場合におい
て、信号４ａ，４ｂ，４ｃのそれぞれの電圧変化
を正しく二値化出来た出力１０を得ることができ
る。 As described above, a voltage 11 is generated across the capacitor 9 that changes depending on the amplitude of the black level of the facsimile signal 4. Since this signal is applied to the inverting input terminal (-) of comparator 2, comparator 2
An output 10 shown in FIG. 4 is obtained at the output terminal of. That is, in the case of the facsimile signal 4, it is possible to obtain an output 10 in which the voltage changes of the signals 4a, 4b, and 4c are correctly binarized.
本発明は以上説明したようにダイオード、抵
抗、コンデンサを付加して黒レベル検出回路を設
けることにより、従来二値化が困難であつた白黒
のレベル変化が少なく、且つ信号の変化が白レベ
ル付近及び黒レベル付近に混在するフアクシミリ
信号においても容易に白黒の情報として正しく二
値化できるフアクシミリ信号二値化回路が得られ
る。 As explained above, by adding a diode, a resistor, and a capacitor to provide a black level detection circuit, the present invention reduces level changes between black and white, which were difficult to achieve in the past, and allows signal changes to occur near the white level. A facsimile signal binarization circuit that can easily and correctly binarize facsimile signals mixed around the black level as black and white information can be obtained.
第１図は従来例を示す回路図、第２図は第１図
の動作を示す波形図、第３図は本発明の一実施例
を示す回路図、第４図は第３図の動作を示す波形
図である。
１……入力端子、２……比較器、３……出力端
子、４……フアクシミリ信号、５，６，１０……
二値化回路出力、７……ダイオード、８……抵
抗、９……コンデンサ、１１……コンデンサ端子
電圧。
Fig. 1 is a circuit diagram showing a conventional example, Fig. 2 is a waveform diagram showing the operation of Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a circuit diagram showing the operation of Fig. 3. FIG. 1...Input terminal, 2...Comparator, 3...Output terminal, 4...Facsimile signal, 5, 6, 10...
Binarization circuit output, 7...Diode, 8...Resistor, 9...Capacitor, 11...Capacitor terminal voltage.
Claims (1)
ミリ信号を一方の入力端に入力する比較器と、抵
抗およびコンデンサを並列に接続し、その一方の
接続部を前記比較器の他方の入力端に接続した時
定数回路と、前記一方の入力端と前記一方の接続
部との間に接続したダイオードとを具備し、前記
時定数回路の他方の接続部に、前記フアクシミリ
信号の白レベルから所定量だけ黒レベル側に離れ
た電位を与え、前記時定数回路の時定数を前記フ
アクシミリ信号の最高画周波数の１〜３サイクル
分とし、前記黒情報のピーク値の変動にかかわら
ず、そのピーク値よりも所定量だけ白レベル側に
離れた電位を前記他方の入力端に与えて前記フア
クシミリ信号と比較して二値化出力を得るように
したことを特徴とするフアクシミリ信号二値化回
路。1 A comparator that inputs an analog facsimile signal having white information and black information to one input terminal, a resistor and a capacitor connected in parallel, and one connection part of the comparator is connected to the other input terminal of the comparator. a time constant circuit; and a diode connected between the one input terminal and the one connection part, and the other connection part of the time constant circuit is connected to a black level by a predetermined amount from the white level of the facsimile signal. A potential far away from the level side is applied, and the time constant of the time constant circuit is set to 1 to 3 cycles of the highest image frequency of the facsimile signal, and regardless of fluctuations in the peak value of the black information, the time constant A facsimile signal binarization circuit characterized in that a potential that is a certain amount away from the white level side is applied to the other input terminal and compared with the facsimile signal to obtain a binarized output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57028333A JPS58146179A (en) | 1982-02-24 | 1982-02-24 | Binarizing circuit of facsimile signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57028333A JPS58146179A (en) | 1982-02-24 | 1982-02-24 | Binarizing circuit of facsimile signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58146179A JPS58146179A (en) | 1983-08-31 |
| JPH0153542B2 true JPH0153542B2 (en) | 1989-11-14 |
Family
ID=12245677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57028333A Granted JPS58146179A (en) | 1982-02-24 | 1982-02-24 | Binarizing circuit of facsimile signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58146179A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276878A (en) * | 1988-04-27 | 1989-11-07 | Ricoh Elemex Corp | Picture reader |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4875132A (en) * | 1972-01-10 | 1973-10-09 | ||
| JPS4975010A (en) * | 1972-10-19 | 1974-07-19 | ||
| JPS5210613A (en) * | 1975-06-23 | 1977-01-27 | Hitachi Denshi Ltd | Two-value conversion circuit of image signal |
-
1982
- 1982-02-24 JP JP57028333A patent/JPS58146179A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4875132A (en) * | 1972-01-10 | 1973-10-09 | ||
| JPS4975010A (en) * | 1972-10-19 | 1974-07-19 | ||
| JPS5210613A (en) * | 1975-06-23 | 1977-01-27 | Hitachi Denshi Ltd | Two-value conversion circuit of image signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58146179A (en) | 1983-08-31 |
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