JPS5856574A - Signal binarizing circuit - Google Patents

Abstract

PURPOSE:To attain a binary circuit without an error, by inputting an electric signal from a sensor to an integrating circuit, and inputting the integrated output to an effective area discriminating circuit, in a binary circuit of a floating slice level system. CONSTITUTION:Since an integration circuit 63 is inserted between an input terminal 1 and an effective area discriminating circuit 2, a pickup signal is integrated at an integration circuit 63 and sliced at a slice SL at the circuit 2 and convereted into an effective signal 59'. Thus, the notch in the effective signal caused by a ditch A to PP pit of pickup signal can be avoided. As a result, a pat mark slice signal 58' has a correct slice level to the pickup signal and a pat mark signal PS becomes a pat mark signal to be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binarization circuit that converts an analog signal into a binary signal, and more particularly to a signal binarization circuit that also performs effective discrimination of the analog signal to be binarized.

Conventionally, as a signal binarization method, there is a floating slice level method in which II (ii) is changed to binarize an input signal. However, in this method, even if the floating signal included in the input signal is an unnecessary signal, It has the disadvantage of following it.

As a method to solve this problem, there is a method of determining whether the human input signal is valid or invalid and converting only the valid region into binary data. Although the method for determining the valid area is improved against unnecessary floating signals, there are cases where the valid area is determined to be an invalid area (tJ').

FIG. 1 shows a conventional circuit configuration for determining a valid area and binarizing it. The input terminal l is the effective terminal discrimination circuit 20 human power 3 and 2
It is connected to the input 5 of the digitizing circuit 4. The output 6 of the valid area discrimination circuit 2 is connected to the valid person cuff of the binarization circuit 4. In addition, in the binarization circuit 4, the input terminal 5 is the input 9 of the upper envelope discrimination circuit 8, and the input terminal 11 of the lower envelope discrimination circuit 10.
．． It is connected to the first input 13 of the comparator 12.

Output 8' of the upper envelope line discrimination circuit 8, output 10'f' of the lower envelope line discrimination circuit 10! , the first one of the adder circuit 14, respectively.
, the output 17 of said adder circuit 14 enters the second input 18 of the comparator 12.

Output 19 of comparator 12 is connected to output terminal 20. The input signal input from the input terminal l is converted into an upper envelope signal by the upper envelope discrimination circuit 8.Similarly,
It is converted into a lower envelope signal by the lower envelope discrimination circuit 10.

The two signals enter the adder circuit 14, are added together, and then IKed by two. The output of the adder circuit 14 is a floating slice level. The controller] 2 compares the output of the adder circuit 14, that is, the floating null level signal, with the human input signal and outputs the result.

On the other hand, the effective region discrimination circuit 2 performs effective discrimination of the human signal, and includes an upper envelope discrimination circuit 8 and a lower envelope discrimination circuit 10.
Outputs whether or not envelope/connection discrimination is performed.

FIG. 2 shows in more detail the upper envelope discrimination circuit 8, the lower envelope discrimination circuit 10, and the addition circuit 14 shown in FIG. The input terminal 21 is connected to the anode 22 of the diode D8 and the cathode 23 of the diode D.

The cathode 24 of the diode D is connected to one terminal of each of the resistors R7, R8 and the capacitor CI, and the switch 5F,
are connected to one terminal of each.

Furthermore, the anode 25 of the diode D is connected to the resistors R3 and R4.
, one terminal of each of capacitor C3 and switch S
are connected to one terminal of W, respectively. Resistance R,
, R, and one end of the resistor R3 are connected to the operational amplifier op
is connected to the negative input 26 of.

The power supply 27 of the operational amplifier OP is grounded via a resistor R6. The other terminal of R3 is the output 28 of the operational amplifier OP.
It is connected to the. Operational amplifier O? Since the output 28 has the opposite polarity as it is, it is output to the output 29 as a threshold output through a polarity inversion circuit. Further, an FCC voltage of, for example, -12V is applied to the other terminals of the resistors R1 and C1. Further, ycc is applied to the other terminal of the switch SFI via a resistor R6.

Similarly, +rcc, for example, 12V is applied to the other terminals of the resistors R* and C1, and the voltage VCC is applied to the terminal of the switch SIF via the resistor R7. The valid signal input terminal 30 includes switches sr1, sty,
is connected to control terminals 31 and 32 of. switch sr
, , and sr open their contacts when a signal indicating validity is applied to the control terminals 31 and -32. The diode D1, the resistor R11, and the capacitor C3 are elements for detecting the upper envelope, and the mayode D, , and the capacitor C are elements for detecting the lower envelope, and each constitutes an integrating circuit. Resistors Rm and R4 are human resistances of the operational amplifier OP, and the gain of each input is determined by the resistance R
1, determined by the ratio of R4 and feedback resistor R1.

FIG. 3 shows a valid area discrimination circuit. The input 34 of the controller 33 is connected to an input terminal 35, and the other human power 36 is connected to one terminal 37 of a variable resistor Vr. +Vc and -FCC are applied to the other end of the variable resistor Vr.

The output 39 of the converter 33 is outputted to an output 40 as a valid/invalid signal.

FIG. 4 shows the operation of the circuit described above. The human signal is the fifth
This is an imaging signal 55 when a pad 51 and product probing marks (hereinafter referred to as PP marks) 52 of the semiconductor chip 50 shown in the figure are scanned 54 within a field of view 53. Imaging signal 55
In contrast, an upper envelope 56 and a lower envelope 57 are detected, and their average signal, ie, a base mark slice signal 58 is detected.

The output of the effective area discrimination circuit 2, that is, the effective signal 59 includes:
Since the depression (■) in the pp mark of the image pickup signal 55 is detected, the crack (■') occurs. This is because the depression ■ is below the slice level SL. Therefore, the upper and lower envelopes become the same as the imaging signal during that time, and a chip 60 occurs in the area that should be detected as a pad meeting mark signal @PS, which is not detected.

As mentioned above, the binarization circuit that uses the floating slice level method and the valid area discrimination at the same time has a sharp increase in thickness (the chip 60 that is not detected in the binarized output signal because it does not judge the changing signal as valid). There was a problem that this occurred.

The present invention is intended to solve the above-mentioned problems, and its object is to provide a signal binarization circuit that binarizes an input signal without error even when the amplitude changes rapidly and greatly.

The signal binarization circuit of the present invention is characterized by a sensor that converts external information into an electrical signal, a binarization circuit that converts the electrical signal from the sensor into 200 million signals, and a binarization circuit that converts the effective part of the electrical signal into 200 million signals. A valid area discriminator circuit is provided which discriminates and operates with a binarization circuit while it is valid, and when converting the electric signal to a binarization signal, the electric signal is manually integrated by the integrating circuit, and the electric signal is integrated by the integrating circuit. The output is manually input to the effective area discrimination circuit.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 6 shows one embodiment of the present invention, which differs from the conventional example shown in FIG. 1 in that the input terminal 1 and the effective area discrimination circuit 2
The point is that an integrating circuit 63 is inserted between them. That is, the input terminal 1 is connected to the input 61 of the integrating circuit 63,
Its output 62 is connected to the human power 3 of the effective area discrimination circuit 2.

FIG. 7 shows the integration circuit 60 and the effective area discrimination circuit 2 in detail. Effective area discriminator circuit 20 resistance R to human power shown in Figure 3
8. It has a configuration in which a capacitor C5 is added. That is, input terminal 1 is connected to comparator 33 via resistor R8.
is connected to one input 34 of the . Also, comparator 3
The human power 34 of No. 3 is grounded via a capacitor C3.

FIG. 8 shows the operation of the embodiment of the invention shown in FIG.

The image signal 55 is integrated by an integrating circuit 63 to obtain an integrated signal S2. The integral signal is sliced by the slice SL by the effective region discrimination circuit 2 and converted into an effective signal 59'.

When the present invention is used, the depression in the effective signal caused by the PP trace is eliminated, as is clear from comparison with the above-mentioned effective signal No. 59. That is, the lower envelope @56' and the lower envelope line 57' correctly detect the envelope even with respect to the depression (2) caused by the PP trace in the image pickup signal 55. As a result, the gt mark slice signal 58' is the imaging signal 55
The image signal 55 is sliced by the pad mark slice signal 58' and the signal is binarized, that is, the correct slice level is obtained. The spot mark signal PS' is the notch mark signal to be obtained.

As is clear from the above description, by using the present invention, the i-signal 60 of the pad mark signal conventionally shown in FIG. 4 is eliminated, and the captured gI signal is correctly binarized.

According to the present invention, an error-free floating slice level binarization circuit is possible.

In addition, in Fig. 4 and Fig. 8, the upper envelope @56.56'
, lower envelope M57.57', Nitmark slice!
-1'+58.58' is shown slightly shifted from the imaging signal in order to make the drawing easier to see.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a conventional binarization circuit, and Figure 2 is a diagram of a conventional binary conversion circuit.
Figure 3 is a detailed circuit diagram of the digitization circuit, Figure 3 is a detailed circuit diagram of the effective discriminator circuit, Figure 4 is a diagram showing the signals of a conventional binarization circuit, and Figure 5 is a /4' turn diagram of the IC chip. , FIG. 6 is a circuit configuration of the binarization circuit of the present invention, FIG. 7 is a circuit diagram showing in detail the integrating circuit and effective area discrimination circuit of the circuit diagram of the present invention, and FIG. 8 is a circuit diagram of the binarization circuit of the present invention. FIG. 3 is a diagram showing signals of a circuit. 2... Effective area discrimination circuit 8... Upper envelope discrimination circuit 10... Lower envelope discrimination circuit 12... Comparator 14... Addition circuit 63... Integration circuit

Claims (1)

[Scope of Claims] l) A sensor that converts external information into an electrical signal, and a binarization circuit that converts the electrical signal from the sensor into a binary signal;
An effective area discriminator circuit is provided for discriminating an effective part of the electric signal and operating a valid binarization circuit, and when converting the electric signal into a binary signal, the electric signal is input to an integrating circuit. A signal binarization circuit characterized in that the output of the integration circuit is inputted to an effective area discriminator circuit. 2. The signal binarization circuit according to claim 1, wherein the sensor is comprised of an imaging system that performs photoelectric conversion. 3) The binarization circuit includes an integrating circuit that creates a high-level envelope signal and a low-level envelope signal of the electrical signal, and an adder that adds and divides the outputs of the two integrating circuits. and a threshold forming circuit having a switch which is provided in parallel with the condenser in the integrating circuit via a resistor and is opened when the signal is in an effective region. .