JPS6159032B2 - - Google Patents
Info
- Publication number
- JPS6159032B2 JPS6159032B2 JP56155034A JP15503481A JPS6159032B2 JP S6159032 B2 JPS6159032 B2 JP S6159032B2 JP 56155034 A JP56155034 A JP 56155034A JP 15503481 A JP15503481 A JP 15503481A JP S6159032 B2 JPS6159032 B2 JP S6159032B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- input
- valid
- envelope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000003384 imaging method Methods 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Input (AREA)
- Facsimile Image Signal Circuits (AREA)
Description
【発明の詳細な説明】
本発明はアナログ信号を２値化信号に変換する
２値化回路に係り、特に２値化されるアナログ信
号の有効弁別をも行なう信号２値化回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binarization circuit that converts an analog signal into a binary signal, and more particularly to a signal binarization circuit that also performs effective discrimination of the analog signal to be binarized.
従来、信号２値化方式として入力信号を２値化
する為の閾値を変化させる浮動スライスレベル方
式がある。しかしながら前記方式は入力信号に含
まれる浮動信号が不必要な信号であつてもそれに
追従してしまう欠点を有している。 Conventionally, as a signal binarization method, there is a floating slice level method in which a threshold value for binarizing an input signal is changed. However, the above method has the drawback that even if the floating signal included in the input signal is an unnecessary signal, it follows it.
この問題を解決する方法として、入力信号の有
効無効を判別し、有効領域のみ２値化する方式が
ある。有効領域を判別する方式は、不必要な浮動
信号に対して改善されるが、有効領域を無効領域
として判断してしまう場合があつた。 As a method for solving this problem, there is a method of determining whether the input signal is valid or invalid and binarizing only the valid region. Although the method for determining a valid area is improved against unnecessary floating signals, there are cases where a valid area is determined to be an invalid area.
第１図は有効領域と判別して２値化する従来の
回路構成を示す。入力端子１は有効領域弁別回路
２の入力３と２値化回路４の入力５に接続されて
いる。有効領域弁別回路２の出力６は２値化回路
４の有効入力７に接続されている。又、２値化回
路４では入力端子５は上側包絡線弁別回路８の入
力９、下側包絡線弁別回路１０の入力１１、コン
パレータ１２の第１の入力１３に接続されてい
る。上側包絡線弁別回路８の出力８′、下側包絡
線弁別回路１０の出力１０′は、それぞれ加算回
路１４の第１、第２の入力１５，１６に入り、前
記加算回路１４の出力１７は、コンパレータ１２
の第２の入力１８に入る。コンパレータ１２の出
力１９は出力端子２０に接続される。入力端子１
より入つた入力信号は、上側包絡線弁別回路８に
よつて上側包絡線信号に変換される。同様に、下
側包絡線弁別回路１０によつて下側包絡線信号に
変換される。 FIG. 1 shows a conventional circuit configuration for determining a valid area and binarizing it. The input terminal 1 is connected to the input 3 of the valid area discrimination circuit 2 and the input 5 of the binarization circuit 4. An output 6 of the valid area discrimination circuit 2 is connected to a valid input 7 of the binarization circuit 4. Further, in the binarization circuit 4, the input terminal 5 is connected to the input 9 of the upper envelope discrimination circuit 8, the input 11 of the lower envelope discrimination circuit 10, and the first input 13 of the comparator 12. The output 8' of the upper envelope discrimination circuit 8 and the output 10' of the lower envelope discrimination circuit 10 are respectively input to the first and second inputs 15 and 16 of the addition circuit 14, and the output 17 of the addition circuit 14 is , comparator 12
into the second input 18 of. Output 19 of comparator 12 is connected to output terminal 20. Input terminal 1
The input signal received by the processor is converted into an upper envelope signal by the upper envelope discrimination circuit 8. Similarly, it is converted into a lower envelope signal by the lower envelope discrimination circuit 10.
前記２つの信号は加算回路１４に入り、加算さ
れさらに２分の１にされる。加算回路１４の出力
は、浮動スライスレベルとなる。コンパレータ１
２は、前記加算回路１４の出力すなわち浮動スラ
イスレベル信号と入力信号とを比較し出力する。 The two signals enter an adder circuit 14, where they are summed and further halved. The output of the adder circuit 14 is a floating slice level. Comparator 1
2 compares the output of the adder circuit 14, ie, the floating slice level signal, with the input signal and outputs the result.
一方、有効領域弁別回路２では入力信号の有効
弁別を行ない、上側包絡線弁別回路８、下側包絡
線弁別回路８、下側包絡線弁別回路１０に包絡線
弁別を行なうか否かを出力する。 On the other hand, the valid area discrimination circuit 2 performs effective discrimination of the input signal, and outputs to the upper envelope discrimination circuit 8, the lower envelope discrimination circuit 8, and the lower envelope discrimination circuit 10 whether or not envelope discrimination is to be performed. .
第２図は、第１図に示した上側包絡線弁別回路
８、下側包絡線弁別回路１０、加算回路１４をさ
らに詳細に示す。入力端子２１は、ダイオード
D1のアノード２２とダイオードD2のカソード２
３に接続される。 FIG. 2 shows the upper envelope discrimination circuit 8, lower envelope discrimination circuit 10, and addition circuit 14 shown in FIG. 1 in more detail. Input terminal 21 is a diode
Anode 22 of D 1 and cathode 2 of diode D 2
Connected to 3.
ダイオードD1のカソード２４は抵抗R1，R3、
コンデンサC1のそれぞれの一方の端子と、スイ
ツチSW1の一方の端子にそれぞれ接続される。
又、ダイオードD2のアノード２５は、抵抗R2，
R4、コンデンサC2のそれぞれの一方の端子とス
イツチSW2の一方の端子にそれぞれ接続される。
抵抗R3，R4の他の端子を抵抗R5の一端は、演算
増幅器OPの負入力２６に接続される。演算増幅
器OPの正入力２７は、抵抗R6を介して接地され
ている。R5の他端子は演算増幅器OPの出力２８
に接続されている。演算増幅器OPの出力２８
は、このままでは極性が反対なため、極性反転回
路を経て閾値出力として出力２９に出力される。
又、抵抗R1，C1の他の端子には、−Vcc例えば、−
12Vが印加されている。又、スイツチSW1の他の
端子には抵抗R6を介して−Vccが印加されてい
る。 The cathode 24 of the diode D 1 has resistors R 1 , R 3 ,
They are connected to one terminal of each of the capacitors C 1 and one terminal of the switch SW 1 , respectively.
Moreover, the anode 25 of the diode D 2 has a resistance R 2 ,
R 4 is connected to one terminal of each of capacitor C 2 and one terminal of switch SW 2 , respectively.
The other terminals of the resistors R 3 and R 4 and one end of the resistor R 5 are connected to the negative input 26 of the operational amplifier OP. The positive input 27 of the operational amplifier OP is connected to ground via a resistor R6 . The other terminal of R5 is the output 28 of the operational amplifier OP.
It is connected to the. Output 28 of operational amplifier OP
Since the polarity is opposite as it is, it is outputted to the output 29 as a threshold value output through a polarity inversion circuit.
In addition, the other terminals of the resistors R 1 and C 1 are connected to −Vcc, for example, −
12V is applied. Further, -Vcc is applied to the other terminal of the switch SW1 via a resistor R6 .
同様に、抵抗R2，C2の他端子には、＋Vcc例え
ば、12Vが印加され、スイツチSW2の他の端子に
は、抵抗R7を介して前記＋Vccが印加されてい
る。有効信号入力端子３０は、スイツチSW1，
SW2の制御端子３１，３２に接続されている。ス
イツチSW1，SW2は前記制御端子３１，３２に有
効を表わす信号が印加された時、接点を開放とす
る。ダイオードD1、抵抗R1、コンデンサC1は上
側包絡線を検出する素子であり、ダイオード
D2、抵抗R2、コンデンサC2は下側包絡線信号を
検出する素子であり、それぞれ積分回路を構成し
ている。抵抗R3，R4は、演算増幅器OPの入力抵
抗であり、各々の入力の利得は抵抗R3，R4と帰
還抵抗R5の比によつて決まる。 Similarly, +Vcc, for example, 12V is applied to the other terminals of the resistors R2 and C2 , and the +Vcc is applied to the other terminal of the switch SW2 via the resistor R7 . The valid signal input terminal 30 is connected to the switch SW 1 ,
It is connected to control terminals 31 and 32 of SW 2 . The switches SW 1 and SW 2 open their contacts when a signal indicating validity is applied to the control terminals 31 and 32. Diode D 1 , resistor R 1 , and capacitor C 1 are elements that detect the upper envelope;
D 2 , resistor R 2 , and capacitor C 2 are elements that detect the lower envelope signal, and each constitute an integrating circuit. Resistors R 3 and R 4 are input resistances of the operational amplifier OP, and the gain of each input is determined by the ratio of the resistors R 3 and R 4 to the feedback resistor R 5 .
第３図は、有効領域弁別回路を示す。コンパレ
ータ３３の入力３４は入力端子３５に、他の入力
３６には可変抵抗Vrの一つの端子３７が接続さ
れる。可変抵抗Vrの他の端には、＋Vccと−Vcc
が印加される。コンパレータ３３の出力３９は有
効、無効の信号として出力４０に出力される。 FIG. 3 shows a valid area discrimination circuit. The input 34 of the comparator 33 is connected to an input terminal 35, and the other input 36 is connected to one terminal 37 of a variable resistor Vr. The other end of the variable resistor Vr has +Vcc and -Vcc.
is applied. The output 39 of the comparator 33 is outputted to an output 40 as a valid/invalid signal.
第４図は、前述の回路の動作を示す。入力信号
は、第５図に示す半導体チツプ５０のパツド５
１、プロダクトプロービング痕（以下、PP痕と
呼ぶ）５２を視野５３内で走査５４した時の撮像
信号５５である。撮像信号５５に対し、上側包絡
線５６、下側包絡線５７を検出し、その平均信号
即ち、パツドマークスライス信号５８を検出す
る。 FIG. 4 shows the operation of the circuit described above. The input signal is applied to the pad 5 of the semiconductor chip 50 shown in FIG.
1. This is an image signal 55 when a product probing mark (hereinafter referred to as PP mark) 52 is scanned 54 within the field of view 53. An upper envelope 56 and a lower envelope 57 are detected for the imaging signal 55, and an average signal thereof, that is, a pad mark slice signal 58 is detected.
前記有効領域弁別回路２の出力即ち有効信号５
９には、撮像信号５５のPP痕に対するくぼみイ○
を検出している為に、きれつイ○′が生じている。
これは、くぼみイ○がスライスレベルSL以下にあ
るからである。その為に上側及び下側包絡線はそ
の間撮像信号と同じになつてしまい、パツド・マ
ーク信号PSとして検出しなければならない領域
にカケ６０が生じてしまいこれを検出していな
い。 The output of the valid area discrimination circuit 2, that is, the valid signal 5
9 shows the depression corresponding to the PP trace of the imaging signal 55.
Since this is detected, a break occurs.
This is because the depression I○ is below the slice level SL. Therefore, the upper and lower envelopes become the same as the imaging signal during that time, and a chip 60 occurs in the area that should be detected as the pad mark signal PS, which is not detected.
以上述べた様に、浮動スライスレベル方式と有
効領域弁別を同時に用いた２値化回路は、急激に
大きく変化する信号を有効と判断せず、２値化入
力信号に検出されないカケ６０が生じるという問
題点を有していた。 As mentioned above, a binarization circuit that uses the floating slice level method and valid area discrimination at the same time does not judge a signal that changes rapidly and greatly as valid, resulting in undetected chips 60 in the binarized input signal. It had some problems.
本発明は前記問題点を解決するものであり、そ
の目的は振幅が急激に大きく変化する場合におい
ても誤りなく入力信号を２値化する信号２値化回
路を提供することにある。 The present invention is intended to solve the above-mentioned problems, and its object is to provide a signal binarization circuit that binarizes an input signal without error even when the amplitude changes rapidly and greatly.
本発明の信号２値化回路の特徴とするところは
外部情報を電気信号に変換するセンサと前記セン
サからの電気信号を２値化信号に変換する２値化
回路と前記電気信号のうち有効部分を弁別し有効
の間２値化回路と動作させる有効領域弁別回路を
備え、前記電気信号を２値化信号に変換する場合
において、前記電気信号を積分回路に入力して積
分し、前記積分回路出力を有効領域弁別回路に入
力することである。 The signal binarization circuit of the present invention is characterized by a sensor that converts external information into an electrical signal, a binarization circuit that converts the electrical signal from the sensor into a binarized signal, and an effective portion of the electrical signal. and a valid area discriminator circuit that discriminates and operates as a binarization circuit while it is valid, and when converting the electrical signal into a binary signal, the electrical signal is input to an integrating circuit and integrated, and the integrating circuit The output is inputted to a valid area discrimination circuit.
以下、図面を参照して本発明の実施例を説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.
第６図は本発明の１実施例を示すもので、第１
図に示した従来例と異なる点は入力端子１と有効
領域弁別回路２間に積分回路６３が挿入されてい
る点である。すなわち、積分回路６３の入力６１
には入力端子１が接続され、その出力６２は有効
領域弁別回路２の入力３に接続される。 FIG. 6 shows one embodiment of the present invention.
The difference from the conventional example shown in the figure is that an integrating circuit 63 is inserted between the input terminal 1 and the effective area discrimination circuit 2. That is, the input 61 of the integrating circuit 63
The input terminal 1 is connected to the input terminal 1, and the output 62 thereof is connected to the input 3 of the valid area discrimination circuit 2.
第７図は積分回路６０と有効領域弁別回路２を
詳細に示す。第３図に示した有効領域弁別回路２
の入力に抵抗R8、コンデンサC3を付加した構成
となつている。すなわち、入力端子１は抵抗R8
を介してコンパレータ３３の一方の入力３４に接
続される。また、コンパレータ３３の前記入力３
４はコンデンサC3を介して接地されている。 FIG. 7 shows the integration circuit 60 and the effective area discrimination circuit 2 in detail. Effective area discrimination circuit 2 shown in Fig. 3
The configuration is such that a resistor R 8 and a capacitor C 3 are added to the input. In other words, input terminal 1 is resistor R 8
It is connected to one input 34 of a comparator 33 via a . In addition, the input 3 of the comparator 33
4 is grounded via capacitor C3 .
第８図は第６図に示した本発明の実施例の動作
を示す。撮像信号５５は積分回路６３によつて積
分され積分信号Siを得る。積分信号は有効領域弁
別回路２によつてスライスSLでスライスされ有
効信号５９′に変換される。 FIG. 8 shows the operation of the embodiment of the invention shown in FIG. The imaging signal 55 is integrated by an integrating circuit 63 to obtain an integrated signal Si. The integral signal is sliced into slices SL by the effective area discrimination circuit 2 and converted into an effective signal 59'.
本発明を用いた場合には前述の有効信号５９と
比較して明らかな様にPP痕によつて生じる有効
信号のくぼみが無くなつている。すなわち、上側
包絡線５６′、下側包絡線５７′は撮像信号５５の
PP痕によつて生じたくぼみイ○に対しても正しく
包絡線を検出している。その結果、パツドマーク
スライス信号５８′は撮像信号５５の正しいスラ
イスレベルとなり、パツドマークスライス信号５
８′によつて撮像信号５５をスライスし、２値化
した信号すなわちパツドマーク信号PS′は求める
べきパツドマーク信号となつている。 When the present invention is used, as is clear from the comparison with the above-mentioned effective signal 59, the dent in the effective signal caused by the PP trace is eliminated. That is, the upper envelope 56' and the lower envelope 57' correspond to the image signal 55.
The envelope is also correctly detected for depressions caused by PP marks. As a result, the pad mark slice signal 58' becomes the correct slice level of the imaging signal 55, and the pad mark slice signal 58' becomes the correct slice level of the imaging signal 55.
The image pickup signal 55 is sliced by 8' and the binarized signal, that is, the pad mark signal PS', is the pad mark signal to be obtained.
上述の説明から明らかな様に本発明を用いるこ
とにより従来第４図に示したパツドマーク信号の
かけ６０がなく正しく撮像信号を２値化してい
る。本発明によれば誤りのない、浮動スライスレ
ベル方式の２値化回路が可能となる。 As is clear from the above description, by using the present invention, the image signal is correctly binarized without the pad mark signal addition 60 shown in FIG. 4 in the prior art. According to the present invention, an error-free floating slice level binarization circuit is possible.
尚、第４図、第８図において、上側包絡線５
６，５６′、下側包絡線５７，５７′、パツドマー
クスライス信号５８，５８′は図面を見やすくす
る為、撮像信号より少しずらして表わしてある。 In addition, in FIGS. 4 and 8, the upper envelope 5
6, 56', lower envelopes 57, 57', and pad mark slice signals 58, 58' are shown slightly shifted from the imaging signal to make the drawing easier to see.
第１図は従来の２値化回路の構成図、第２図は
従来の２値化回路の詳細な回路図、第３図は有効
弁別回路の詳細回路図、第４図は従来の２値化回
路の信号を示す図、第５図はICチツプのパター
ン図、第６図は本発明の２値化回路の回路構成、
第７図は本発明の回路図の積分回路、有効領域弁
別回路を詳細に示す回路図、第８図は本発明の２
値化回路の信号を示す図である。
２……有効領域弁別回路、８……上側包絡線弁
別回路、１０……下側包絡線弁別回路、１２……
コンパレータ、１４……加算回路、６３……積分
回路。
Figure 1 is a configuration diagram of a conventional binary conversion circuit, Figure 2 is a detailed circuit diagram of a conventional binary conversion circuit, Figure 3 is a detailed circuit diagram of an effective discriminator circuit, and Figure 4 is a conventional binary conversion circuit. Figure 5 is a pattern diagram of the IC chip, Figure 6 is the circuit configuration of the binarization circuit of the present invention,
FIG. 7 is a circuit diagram showing in detail the integrating circuit and the effective area discrimination circuit of the circuit diagram of the present invention, and FIG. 8 is the circuit diagram of the second embodiment of the present invention.
It is a figure which shows the signal of a value conversion circuit. 2... Valid area discrimination circuit, 8... Upper envelope discrimination circuit, 10... Lower envelope discrimination circuit, 12...
Comparator, 14...addition circuit, 63...integration circuit.
Claims (1)
センサからの電気信号の上側包絡線信号と下側包
絡線信号を作成する回路と、該２つの包絡線信号
の平均信号を作成する回路と、該平均信号をスラ
イスレベルとして前記電気信号を２値化する２値
化回路と、前記電気信号のうち有効部分を弁別し
有効の間２値化回路を動作させる有効領域弁別回
路を備え、前記電気信号を２値化信号に変換する
場合において、前記電気信号を積分回路に入力し
て積分し、前記積分回路出力を有効領域弁別回路
に入力することを特徴とする信号２値化回路。 ２ 前記センサは光電変換を行う撮像系より成る
ことを特徴とする特許請求の範囲第１項記載の信
号２値化回路。[Claims] 1. A sensor that converts external information into an electrical signal, a circuit that creates an upper envelope signal and a lower envelope signal of the electrical signal from the sensor, and an average signal of the two envelope signals. a binarization circuit that binarizes the electric signal using the average signal as a slice level; and an effective area discriminator circuit that discriminates a valid portion of the electric signal and operates the binarization circuit while it is valid. When converting the electrical signal into a binary signal, the electrical signal is input to an integrating circuit and integrated, and the output of the integrating circuit is input to an effective area discrimination circuit. circuit. 2. The signal binarization circuit according to claim 1, wherein the sensor comprises an imaging system that performs photoelectric conversion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56155034A JPS5856574A (en) | 1981-09-30 | 1981-09-30 | Signal binarizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56155034A JPS5856574A (en) | 1981-09-30 | 1981-09-30 | Signal binarizing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5856574A JPS5856574A (en) | 1983-04-04 |
| JPS6159032B2 true JPS6159032B2 (en) | 1986-12-15 |
Family
ID=15597221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56155034A Granted JPS5856574A (en) | 1981-09-30 | 1981-09-30 | Signal binarizing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5856574A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6134040A (en) * | 1984-07-26 | 1986-02-18 | Toyota Motor Corp | Preparation of polypropylene resin composition |
| JPS62151071A (en) * | 1985-12-25 | 1987-07-06 | Nec Corp | Video signal processor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52151513A (en) * | 1976-06-11 | 1977-12-16 | Hitachi Ltd | Binary signal generation device |
-
1981
- 1981-09-30 JP JP56155034A patent/JPS5856574A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52151513A (en) * | 1976-06-11 | 1977-12-16 | Hitachi Ltd | Binary signal generation device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5856574A (en) | 1983-04-04 |
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