JP2915928B2 - Peak detector - Google Patents

Description

The present invention relates to a peak detector used, for example, in a part of a spectrum analyzer.

`` Prior art '' A signal separated into each spectrum component in a spectrum analyzer is supplied to a peak detection circuit, a detected peak value is converted into a digital signal by an AD converter, and the digital signal is stored in a memory. After reading out the memory, performing signal processing, converting the signal into an analog signal, and displaying the analog signal on a display device.

The peak detection circuit used in this case had the configuration shown in FIG. FIG. 3 shows a case where a positive peak is detected. An input signal from an input terminal 11 is compared with a detection output from an output terminal 13 by a differential amplifier 12. If the input signal is larger, a capacitor 15 is passed through a detection diode 14. The peak value of the input signal is charged at
Is supplied to the output terminal 13 through a high input impedance buffer circuit 16 composed of a source follower circuit. With this configuration, for example, in response to the input signal 17 of the input terminal 11, the output signal 18 of the output terminal 13 is held at the peak value of the input signal 17, and the capacitor 15
When both ends are short-circuited, the output signal 18 becomes zero.

"Problems to be Solved by the Invention" Detection Diode 14, Capacitor 15, and Buffer Circuit 16
The relationship between the leakage current i and the resulting leakage voltage e is Becomes t is time, and C is the capacitance of the capacitor 15.

Therefore, in order to maintain the output peak voltage for a long time, that is, to reduce the leak voltage e, the leak current i must be reduced or the capacitance C of the capacitor 15 must be increased. In order to reduce the leakage current i, the layout must be made of expensive components with little leakage and a layout with little leakage such as by providing a shield (guard ring) having the same potential as the output voltage. Then, charging becomes difficult, and the frequency band of the peak detection circuit becomes narrow.

In the case of the spectrum analyzer, if the display screen is swept once for 1000 seconds and displayed in 700 points in the sweep direction, the reset switch 19 is reset every 1.4 seconds, and the peak detection immediately before the reset is performed. Supply the output to the AD converter. Therefore, when a pulse is input immediately after reset or when the input level decreases after reset, it is necessary to hold the output peak voltage for 1.4 seconds. However, conventionally, it was difficult to maintain the output peak voltage for 1.4 seconds when trying to widen the frequency band of the peak detection circuit.

According to the present invention, a peak of an input signal is detected by a peak detection circuit and held by a capacitor, and a detection output of the peak detection circuit is sampled and held by a sample and hold circuit, and the sample and hold is performed. The output of the circuit and the output of the peak detection circuit are compared by a comparison circuit, and when the latter increases in absolute value, a sample / hold command is issued from the comparison circuit to the sample / hold circuit. The output of the sample and hold circuit becomes the output of the peak detector. Then, the peak detection circuit 21 is immediately reset by the reset pulse,
It is possible to detect the peak value of the input signal. And behind
In order to guarantee the operation time of the A / D converter (not shown), the delay circuit 29 takes a timing shorter than the time during which the peak value detected by the peak detection circuit 21 is substantially held, and The hold circuit is reset so that the peak value detected by the peak detection circuit 21 can be held by the sample hold circuit 22.

FIG. 1 shows an embodiment of the present invention. In the present invention, an input signal is supplied from an input terminal 11 to a peak detection circuit 21. The peak detection circuit 21 can detect the peak of the input signal and hold it in a capacitor, and can use the same configuration as the conventional peak detection circuit shown in FIG. The same reference numerals are given to the parts corresponding to the figures.

The output of the output terminal 13 of the peak detection circuit 21 is sampled and held by the sample and hold circuit 22. When the sample switch 23 is turned on, the sample and hold circuit 22 outputs the output of the output terminal 13 through the buffer circuit 24 to the holding capacitor.
25, and outputs the holding voltage of the holding capacitor 25 to the output terminal 27 through the buffer circuit 26.

Reset switch by reset pulse from terminal 28
19 is turned on, and this reset pulse
Is supplied to the sample switch 23 as a sample hold command through the OR circuit 31, and the switch 23 is turned on.

The output of the peak detection circuit 21 and the output of the sample and hold circuit 22 are compared by a comparison circuit 32. When the absolute value of the former is larger, a sample and hold command is issued to the sample and hold circuit 22. In this example, the positive peak of the input signal is detected, and the output of the peak detection circuit 21 is
, And the output of the sample-and-hold circuit 22 is supplied to the inverting input side of the comparison circuit 32.
Is supplied to the OR circuit 31.

As shown in FIG. 2A, the peak detection circuit 21 is reset, and the peak detection circuit 21 charges the capacitor 15 to the peak value of the input signal immediately after the reset. Then FIG. 2B
As shown in (2), a sample hold command is issued from the delay circuit 29, the output of the peak detection circuit 21 is held in the holding capacitor 25, and this held voltage is used as an output terminal as a peak detection output.
Output to 27. After the sample and hold, when the output of the peak detection circuit 21 becomes larger than the output of the sample and hold circuit 22 due to the rise of the input signal, the output of the comparison circuit 32 becomes a high level as shown by the dotted line in FIG. The hold command is supplied to the sample hold circuit 22 as a hold command, and the output of the peak detection circuit 21 charges the holding capacitor 25. Therefore, the output of the sample and hold circuit 22 becomes equal to the peak value of the input signal between resets.

When the reset cycle is set to 1.4 seconds as in the example of the spectrum analyzer, the delay amount of the delay circuit 29 is set to, for example, 7 microseconds. This delay amount is determined by the peak detection circuit 21
Is smaller than the time during which the peak value detected in step is substantially maintained.

According to this configuration, the capacitance C of the capacitor 15 of the peak detection circuit 21 is reduced, so that the frequency band of the peak detection circuit 21 is widened. The output of the peak detection circuit 21 is sampled and held by the sample and hold circuit 22 before the signal does not decrease. Since the output of the peak detection circuit 21 is DC, the sample-and-hold circuit 22 does not require a frequency band, and a long holding time can be obtained even if the capacity of the holding capacitor 25 is increased and configured with inexpensive components. . When the peak of the input signal rises after the sample hold immediately after the reset, a sample hold command is issued by the output of the comparison circuit 32, and a correct peak value can be detected.

In the above description, the present invention has been applied to the detection of a positive peak, but can be applied to the detection of a negative peak.

[Effect of the Invention] As described above, according to the present invention, the peak detection circuit 21
By providing the sample-and-hold circuit 22 and the comparison circuit 32, the frequency characteristics of peak detection can be widened, a long holding time can be obtained, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the relationship between a reset pulse and a sample and hold pulse, and FIG. 3 is a block diagram showing a conventional peak detection circuit.

Claims (1)

(57) [Claims] An input signal is input to one input terminal of an operational amplifier, and an output terminal of the operational amplifier is connected to an input terminal of a first buffer circuit via a backflow preventing diode, and the first buffer circuit is connected to the input terminal. An input terminal of the operational amplifier is grounded through a first capacitor, an output of the first buffer circuit is output as a peak detection signal, and a peak detection circuit input to the other input terminal of the operational amplifier; The output of the second buffer circuit is input to the third buffer circuit through a sample switch, and the input terminal of the third buffer circuit is grounded through a second capacitor.
A sample-and-hold circuit that outputs the output of the buffer circuit as a sample-and-hold signal, a reset switch that is connected in parallel with the first capacitor and is turned on by a reset pulse, and that receives the reset pulse, A delay circuit for delaying and outputting a time smaller than the time during which the peak value detected by the detection circuit is substantially held, and comparing the peak detection signal with the sample and hold signal, if the former is larger, A comparison circuit that outputs a sample-and-hold command; an OR circuit that performs an OR operation on an output of the comparison circuit and an output of the delay circuit; and an output side of the second buffer circuit and an input of the third buffer circuit The sample switch, which is interposed between the first side and the connection point of the second capacitor, is turned on by the output of the OR circuit. Peak detector, characterized in that the, the equipped.