JPH01500154A - surface mountable diode - Google Patents

surface mountable diode

Info

Publication number
JPH01500154A
JPH01500154A JP62503012A JP50301287A JPH01500154A JP H01500154 A JPH01500154 A JP H01500154A JP 62503012 A JP62503012 A JP 62503012A JP 50301287 A JP50301287 A JP 50301287A JP H01500154 A JPH01500154 A JP H01500154A
Authority
JP
Japan
Prior art keywords
conductive
region
junction
diode
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62503012A
Other languages
Japanese (ja)
Other versions
JPH0666409B2 (en
Inventor
ウォルターズ，セシル　ケント
Original Assignee
アンプ　インコーポレーテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アンプ　インコーポレーテッド filed Critical アンプ　インコーポレーテッド
Publication of JPH01500154A publication Critical patent/JPH01500154A/en
Publication of JPH0666409B2 publication Critical patent/JPH0666409B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12035—Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10174—Diode
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Rectifiers (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 表面取付は可能なダイオード 本発明は、最小のスペースで、かつ極めて簡単に表面へ容易に装着できる表面取 付は可能なダイオードに関するものである。[Detailed description of the invention] Diodes can be surface mounted The present invention provides a surface mount that can be easily attached to a surface in a minimum of space and in a very simple manner. The markings refer to possible diodes.

ダイオードは、過渡抑制デバイス、整流器、光源、光検出器および電圧基準とし て広く使用されている。多くの用途においては、ワイヤリード等を用いずに回路 板のような表面にダイオードを直接表面取付けできることが重要である。とくに 、過渡抑制素子としてバイポーラツェナーダイオードまたはユニポーラツェナー ダイオードが使用される時には、高い取付は密度がしばしば極めて重要である。Diodes serve as transient suppression devices, rectifiers, light sources, photodetectors and voltage references. is widely used. In many applications, circuits can be constructed without wire leads etc. It is important to be able to surface mount the diode directly onto a surface such as a board. especially , bipolar Zener diode or unipolar Zener as transient suppression element When diodes are used, high mounting density is often critical.

本発明は、ワイヤリードを必要とせず、必要な取付はスペースを最小にするため に超小型で容易に製造できる改良したダイオードに向けられたものである。The invention requires no wire leads and the required installation minimizes space. The present invention is directed toward improved diodes that are ultra-small and easily manufactured.

本発明の１つの面によれば、表面に取付けられるダイオードは、ベースと、この ベースから離れて延びる向き合う第１の面および第２の面とを形成する半導体素 子を含む。According to one aspect of the invention, a surface-mounted diode includes a base and a surface-mounted diode. a semiconductor element forming opposing first and second surfaces extending away from the base; Including children.

この半導体素子は、向き合っている面の間で電気的に相互に接続され、ベースか ら隔てられたｐ−ｎ接合を有する。The semiconductor device is electrically interconnected between facing sides and has a base. It has a p-n junction separated from the other.

第１の導電層が第１の向き合う面へ固定され、第１の導電層と第２の導電層の間 にｐ−ｎ接合が挾まれるように、第１の導電層に全体として平行に配置された第 ２の導電層へ第２の向き合う面を電気的に相互接続する手段が設けられる。各導 電層はそれぞれの露出された表面を形成し、導電層の各露出面が取付は表面のそ れぞれの隔てられている接点へ接触し、導電層の露出面が、取付は表面により形 成された取付は平面から離れる向きへ延びるように、ベースは取付は平面に平行 に向けられる。適当なはんだまたは導電性エポキシのような導電性固定剤の２つ の質量がそれぞれ１つの接点と、関連する導電層の露出面へおのおの固定されて すみ肉を形成する。固定剤は、流体状態にある時に毛管作用により露出面上へ動 くものが選択される。a first electrically conductive layer is secured to the first opposing surface, and between the first and second electrically conductive layers; a first conductive layer generally parallel to the first conductive layer such that the p-n junction is sandwiched between the first conductive layer and the first conductive layer; Means are provided for electrically interconnecting the second opposing surface to the second conductive layer. Each guide The conductive layer forms each exposed surface, and each exposed surface of the conductive layer The exposed surface of the conductive layer contacts the separated contacts, and the mounting is shaped by the surface. The base should be aligned parallel to the plane so that the attached attachment extends away from the plane. directed towards. Two conductive fixatives, such as a suitable solder or conductive epoxy. masses are each fixed to one contact and the exposed surface of the associated conductive layer. Form the fillet. When in a fluid state, the fixative moves onto the exposed surface by capillary action. A spider is selected.

導電層の露出面は半導体素子のベースと取付は表面の接点の両方を横切って延び ることが好ましい。ダイオードは、たとえば、過渡抑制デバイスとして使用する ユニポーラツェナーダイオードまたはバイポーラツェナーダイオードとすること ができる。ベースおよび接点から離れる向きに延びている導電層の露出面に固定 剤を直接取付けることによりダイオードの寸法と、コストおよび複雑さは全て最 少限に抑えられる。更に、鋭敏なｐ−ｎ接合が固定剤から分離され、それにより 、ｐ−ｎ接合に与える損傷を最少限に抑える。以下に説明する好適な実施例にお いては、ダイオードのいくつかの向きのうちの任意の１つをダイオードの機能を 妨げることなしに使用できるように、半導体素子の周縁部の周囲に対称的に位置 させられる３つまたはそれ以上のベースを半導体素子が形成する。これにより取 付は作業がかなり簡単となり、向きを誤ったダイオードに関連する製造上の諸問 題を少くする。The exposed surface of the conductive layer extends across both the base of the semiconductor device and the mounting surface contacts. It is preferable that Diodes are used as transient suppression devices, e.g. Must be a unipolar Zener diode or a bipolar Zener diode Can be done. Fixed to the exposed surface of the conductive layer extending away from the base and contacts Direct mounting of the diode minimizes diode size, cost and complexity. can be kept to a minimum. Furthermore, the sensitive p-n junction is separated from the fixative, thereby , minimizing damage to the p-n junction. The preferred embodiment described below The function of the diode can be changed by using any one of several orientations of the diode. Located symmetrically around the periphery of the semiconductor device for unobstructed use The semiconductor device forms three or more bases that are controlled. This allows This makes the process much easier and eliminates manufacturing issues related to misoriented diodes. Reduce the number of topics.

本発明の特徴の第２の面によれば、第１の外面と、第１の内面と、それらの第１ の外面と第１の内面の間に第１のｐ−ｎ接合を形成する手段とを形成する第１の 半導体素子を有する表面取付は可能なバイポーラダイオードが得られる。また、 第２の外面と、第２の内面と、それらの第２の外面と第２の内面の間に第２のｐ −ｎ接合を形成する手段とを形成する第２の半導体素子が設けられる。第１の手 段は、外面の間を延びるベースを形成する集積化されたユニットを形成するため に、第１の手段は第１の面と第２の面を外面の間に一緒に電気的に相互接続し、 かつ機械的に固定する。第１のｐ−ｎ接合と第２のｐ−ｎ接合は逆極性で向けら れる。第１のｐ−ｎ接合と第２のｐ−ｎ接合が第１の導電面と第２の導電面の間 に位置させられ、導電面がベースから離れて延びるように、第１の導電面と第２ の導電面が第１の外面と第２の外面に取付けられる。それらの導電面は、ベース の横を延びているそれぞれの取付は表面に表面取付けするために位置させられる 。導電面は互いに平行に向け、ベースをほぼ横切ることが好ましい。以下に説明 する好適な実施例においては、導電面はそれぞれのメタライズされた層を有する 。According to a second aspect of the features of the invention, a first outer surface, a first inner surface and a first means for forming a first p-n junction between the outer surface of the A surface-mountable bipolar diode with a semiconductor component is obtained. Also, a second outer surface, a second inner surface, and a second p between the second outer surface and the second inner surface; - a second semiconductor element forming means for forming an n-junction. first move The steps form an integrated unit that forms a base extending between the outer surfaces. the first means electrically interconnecting the first surface and the second surface together between the outer surfaces; and mechanically fixed. The first p-n junction and the second p-n junction are oriented with opposite polarity. It will be done. a first p-n junction and a second p-n junction between the first conductive surface and the second conductive surface; a first conductive surface and a second conductive surface such that the conductive surface extends away from the base; conductive surfaces are attached to the first outer surface and the second outer surface. Their conductive surface is the base Each installation extending horizontally is positioned for surface-to-surface mounting. . Preferably, the conductive surfaces are oriented parallel to each other and substantially transverse to the base. explained below In a preferred embodiment, the conductive surface has a respective metallized layer. .

本発明のダイオードは、たとえば、過渡抑制デバイスとして使用するバイポーラ ツェナーダイオードとして形成できる。本発明のバイポーラダイオードにより、 両方のｐ−ｎ接合がデバイスの中心近くに配置され、したがって良く保護される という大きな利点が得られる。ｐ−ｎ接合はそれぞれの内面の中心に設けられ、 ダイオードの電気的機能を変えることなしに、全体のバイポーラダイオードを反 対にひつくり返えして、導電面の間を延びる軸線を中心として回すことができる ように、全体のバイポーラダイオードは対称的である。このやり方が用いられる と、回路板上での向きの誤りが事実上無くされる。The diode of the invention can be used, for example, as a bipolar diode for use as a transient suppression device. It can be formed as a Zener diode. With the bipolar diode of the present invention, Both p-n junctions are placed near the center of the device and are therefore well protected This is a big advantage. A p-n junction is provided at the center of each inner surface, Reverses the entire bipolar diode without changing the electrical function of the diode. Can be rotated in pairs and rotated about an axis extending between the conductive surfaces As such, the entire bipolar diode is symmetrical. This method is used , errors in orientation on the circuit board are virtually eliminated.

本発明自体は、別の諸口的および付随する諸利点と一緒に、添附図面とともに下 記の詳しい説明を参照することにより最も良く理解されるであろう。The invention itself, together with other aspects and attendant advantages, is described below with reference to the accompanying drawings. It may be best understood by reference to the detailed description given below.

第１図は本発明の第１の好適な実施例を含むバイポーラダイオードの斜視図、 第２図は第１図のダイオードの中心線に沿って切断した縦断面図、 第３図は第１図のダイオードの製造の中間段階におけるダイオードの部品を示す ウェハーの斜視図、第４図はダイオードを取付ける前の第１図の回路板の平面図 、 第５図は本発明の第２の好適な実施例を含むユニポーラダイオードの平面図であ る。FIG. 1 is a perspective view of a bipolar diode including a first preferred embodiment of the present invention; Figure 2 is a longitudinal cross-sectional view taken along the center line of the diode in Figure 1; Figure 3 shows the components of the diode at an intermediate stage in the manufacture of the diode of Figure 1. A perspective view of the wafer, and Figure 4 is a top view of the circuit board in Figure 1 before the diodes are installed. , FIG. 5 is a plan view of a unipolar diode including a second preferred embodiment of the present invention. Ru.

図面を参照して、第１図および第２図は本発明の第１の好適な実施例を含むバイ ポーラツェナーダイオードの２つの図を示す。このダイオードは第１の半導体素 子すなわちダイ１と、第２の半導体素子すなわちダイ２とを含む。各半導体素子 １．２は、後で詳しく説明するように、それぞれのｐ−ｎ接合を構成する。それ ら２つの半導体素子１゜２はｐ−ｎ接合に隣接する接合領域において一緒に接合 される。各半導体素子１．２はそれぞれの外面４．５と、それぞれの内面３６． ３８と、少くとも１つのそれぞれのベース３１、８２とを構成する。図示のよう に、外面４．５は互いに平行に、かつベース３１．３２を横切るように向けるこ とが好ましい。Referring to the drawings, FIGS. 1 and 2 show a bibliometer containing a first preferred embodiment of the present invention. 2 shows two diagrams of a polar Zener diode. This diode is the first semiconductor element. a second semiconductor element or die 1; and a second semiconductor element or die 2. Each semiconductor element 1.2 constitutes each pn junction, as will be explained in detail later. that The two semiconductor devices 1゜2 are bonded together in the junction region adjacent to the p-n junction. be done. Each semiconductor element 1.2 has a respective outer surface 4.5 and a respective inner surface 36. 38 and at least one respective base 31,82. As shown In addition, the outer surfaces 4.5 are oriented parallel to each other and transversely to the base 31.32. is preferable.

次に、回路板の所定場所にダイオードをどのようにして取付けるかについて詳し く説明する。簡単にいえば、各外面４，５はそれぞれのメタライズ層を形成し、 それらのメタライズ層はそれぞれの印刷回路接点８，９に接触し、かつそれぞれ の印刷回路接点から離れて接方向に延びるために位置させられる。適切なはんだ または導電性エポキシのような材料で形成された接合ジヨイント６．７が外面４ ゜５をそれぞれの印刷回路接点８，９へ電気的および機械的に相互接続する。Next, learn more about how to install the diode in place on the circuit board. Explain in detail. Briefly, each outer surface 4, 5 forms a respective metallization layer, Those metallization layers contact respective printed circuit contacts 8,9 and each is positioned to extend tangentially away from the printed circuit contacts. suitable solder or a bonding joint 6.7 formed of a material such as conductive epoxy on the outer surface 4. 5 are electrically and mechanically interconnected to the respective printed circuit contacts 8,9.

このように、第１図と第２図のダイオードは、ワイヤボンド、クリップ、または その他の従来のリードアタッチメントを使用することなしに、経済的なやり方で 印刷回路板接点へ電気的に相互接続される。更に、不必要なバッケージング素子 は無くされ、ダイオードを印刷回路板接点８，９へ接続するために用いられるの は不働態化された半導体素子自体である。Thus, the diodes of FIGS. 1 and 2 can be wire bonded, clipped, or in an economical manner without the use of other traditional lead attachments. Electrically interconnected to printed circuit board contacts. Furthermore, unnecessary packaging elements are eliminated and are used to connect the diodes to the printed circuit board contacts 8, 9. is the passivated semiconductor element itself.

第２図は第１図のバイポーラツェナーダイオードの種々の部品素子を詳しく示す 横断面図である。このダイオードは双方向に動作して、所定の電圧しきい値より 高い信号をいずれの向きにも伝える。印刷回路板接点の一方８がコネクタのピン のような信号源へ接続され、他の接点９が接地されるものとすると、第１図と第 ２図の双方向ツェナーダイオードは、超小型に製造できる過渡抑制デバイスとし て使用するのに良く適する。下で指摘するように、本発明はバイポーラデバイス に使用することに限定されるものではなく、ユニポーラダイオードにも容易に使 用される。Figure 2 shows in detail the various components of the bipolar Zener diode of Figure 1. FIG. This diode operates bidirectionally to Transmits a high signal in either direction. One side of the printed circuit board contact 8 is the pin of the connector If it is connected to a signal source such as , and the other contact 9 is grounded, then Figs. The bidirectional Zener diode shown in Figure 2 can be used as a transient suppression device that can be manufactured in an ultra-small size. Well suited for use. As pointed out below, the present invention is a bipolar device. It is not limited to use in used.

第１図および第２図に示すように、図示のダイオードは２つの半導体素子１．２ で形成される。各半導体素子１゜２はシリコンのような半導体物質で構成され、 半導体素子１．２の外面４，５に全体として平行に向けられているそれぞれのｐ −ｎ接合ｔｏ、　１１をおのおのが構成する。それらのｐ−ｎ接合は内面３６． ３８上の領域１２．１３において熱酸化物５ｌｏ２で不働態化され、その不働態 化された領域は領域１４．１５において取付けられたホウけい酸ガラスで被覆さ れて、ダイオードが使用される環境においてｐ−ｎ接合１０゜１１の適切な保護 を行う。As shown in FIGS. 1 and 2, the illustrated diode consists of two semiconductor elements 1.2 is formed. Each semiconductor element 1゜2 is composed of a semiconductor material such as silicon, each p oriented generally parallel to the outer surface 4, 5 of the semiconductor element 1.2 -n junctions to, 11 respectively. Their p-n junctions are on the inner surface 36. Passivated with thermal oxide 5lo2 in region 12.13 on 38, its passivation The exposed area is covered with borosilicate glass installed in area 14.15. and proper protection of the p-n junction 10°11 in the environment where the diode is used. I do.

この実施例においては、半導体素子１，２は同一であって、通常のブレーナウェ ハー製造法で製造できる。この方法はウェハーで始まる。そのウェハーを処理し て多数の半導体素子１，２を形成する。種々の工程を終った後で、ウェハーを別 々の半導体素子１，２に切断すなわちさいの目に切る。最後の組立においてダイ オードをそれの側面で印刷回路板に取付けるから、製造においては比較的厚いウ ェハーを使用すると有利である。そのウニ／％−は低抵抗率の半導体基板で形成 することが好ましい。第２図においては、この基準はｎ″１１領域て参照符号１ ６．１７により識別されている。そのｎ＋領領域この実施例においては約０．０ １オーム−■の抵抗率を有することが好ましい。低抵抗率で、高濃度にドープさ れた基準を用いることにより寄生抵抗値は最低に保たれ、それにより、最終的に 得られたツェナーダイオードのダイナミックインピーダンスを減少させる。もち ろん、本発明のダイオードは第２図に示されているドーパントとは逆の種類のド ーパントで形成できること、すなわち、ｎ形を拡散されたｎ−ｐ接合とともにｐ ′″基板を使用できることを理解すべきである。In this embodiment, the semiconductor elements 1 and 2 are identical and are conventional brainer hardware. It can be manufactured using the har manufacturing method. The method begins with a wafer. process the wafer A large number of semiconductor elements 1 and 2 are then formed. After completing various processes, the wafers are separated. The semiconductor elements 1 and 2 are cut or diced into individual semiconductor elements 1 and 2. Die in final assembly Since the ode is attached to the printed circuit board on its side, relatively thick boards are used in manufacturing. It is advantageous to use a wafer. The urchin/%- is made of a low resistivity semiconductor substrate. It is preferable to do so. In FIG. 6.17. In this example, the n+ region is approximately 0.0 Preferably, it has a resistivity of 1 ohm-■. Highly doped with low resistivity By using established standards, the parasitic resistance values are kept to a minimum, which ultimately Decrease the dynamic impedance of the resulting Zener diode. rice cake Of course, the diode of the present invention may contain a dopant of the opposite type to that shown in FIG. - can be formed with a punt, i.e. an n-type along with a diffused n-p junction. It should be understood that ``'' substrates can be used.

半導体素子１，２の製造の第１の工程は、希望のツェナー電圧値すなわち希望の なだれ電圧値の制御を助ける抵抗率値のエピタキシャル付着層１８．１９を形成 することである。２０ボルトなだれ降伏デバイスの場合には、エピタキシャル層 １８．１９の抵抗率は約０．０３オーム−■で、厚さが約２４ミクロンであるこ とが好ましい。それからウェハーを熱酸化してＳＬＯ□の層を形成する。この実 施例ではそのＳ　ｉＯ２層の厚さは約１ミクロンである。次に、エツチングして 拡散窓を開くために第１のフォトリソグラフィ工程を行う。次に、適当なドーパ ント（この実施例ではほう素のような）を拡散窓の上に予め付着してから、拡散 による押しこみ工程を行ってｐ−ｎ接合をこの実施例では約８ミクロンの深さま で押しこむ。そのようなｐ−ｎ接合は２０ボルトなだれ降伏ダイオード層にとっ て適当であることが見出されている。押しこみ工程で形成されたｐ層のシート抵 抗値は正方形当り約２２オームであることが好ましい。The first step in manufacturing the semiconductor devices 1 and 2 is to obtain the desired Zener voltage value, that is, the desired Zener voltage value. Forming an epitaxial deposition layer 18, 19 with a resistivity value that helps control the avalanche voltage value It is to be. For a 20 volt avalanche device, the epitaxial layer 18.19 has a resistivity of approximately 0.03 ohm-■ and a thickness of approximately 24 microns. is preferable. The wafer is then thermally oxidized to form a layer of SLO□. This fruit In the example, the thickness of the SiO2 layer is about 1 micron. Next, etching A first photolithography step is performed to open the diffusion window. Next, a suitable dopa A substance (such as boron in this example) is pre-deposited on top of the diffusion window and then diffused. An indentation process is performed to form the p-n junction to a depth of about 8 microns in this example. Push it in. Such a p-n junction is suitable for a 20 volt avalanche diode layer. It has been found to be suitable. The p-layer sheet resistor formed in the indentation process Preferably, the resistance value is about 22 ohms per square.

この製造法の次の工程は、半導体素子１．２の希望の最終的な厚さを得るために ウェハーの裏面を研磨することである。それから、正方形当り約２オームのシー ト抵抗値を有する非常に高濃度にドープされた領域ｎ　”２０＋　２１を形成す るために表面エンハンス拡散すなわちりんゲッタ操作を行う。以下に説明するよ うに、この非常に高濃度にドープされた領域２０．２１により良好なオーミック 後ろ側接点が得られる。そのエンハンス操作は、全体のウェハー処理の終り近く で後ろ側メタライゼーション操作の一部として選択されたドープされたメタライ ゼーションを行う、他の低温ドーピング技術により行うこともできる。The next step in this manufacturing method is to obtain the desired final thickness of the semiconductor element 1.2. This involves polishing the back side of the wafer. Then a seam of about 2 ohms per square. forming a very heavily doped region n"20+21 with a high resistance value. A surface enhancement diffusion or phosphor getter operation is performed to achieve this. I will explain below This very heavily doped region 20.21 provides good ohmic A contact point on the back side is obtained. The enhancement operation is performed near the end of the entire wafer processing. Doped metallization selected as part of backside metallization operation in Other low temperature doping techniques can also be used.

表面エンハンス操作の後で、フォトリソグラフィ工程によりウェハーを再び選択 エツチングして、拡散工程中に成長させられた熱酸化物にオーミック接触窓を形 成する。次に、第２図に領域１４と１５で示すように、ホウけい酸ガラスの付加 層によりウェハーを更に不働態化する。そのガラス層を付着したとすると、次に 、最後のオーミック接触窓開口部を設けるために第３の選択的エツチング操作を 行うことがめられる。このオーミック接触窓開口部、領域２２゜２３内に、薄膜 蒸着技術でパラジウム層を付着する。それから、このパラジウム薄膜蒸着技術を 領域２２．２３において露出されているシリコンに焼結する。化学エツチングに より過剰のパラジウムをガラス１４．１５から除去する。その後で、比較的厚い 銀隆起接点２４．２５をパラジウムの上に電着する。After the surface enhancement operation, the wafer is reselected by a photolithographic process Etch to form an ohmic contact window in the thermal oxide grown during the diffusion process. to be accomplished. Next, the addition of borosilicate glass, as shown in areas 14 and 15 in FIG. The layer further passivates the wafer. Assuming that the glass layer is attached, then , a third selective etching operation to provide a final ohmic contact window opening. It is recommended to do so. Within this ohmic contact window opening, areas 22 and 23, a thin film Deposit the palladium layer using vapor deposition techniques. Then, using this palladium thin film deposition technology, Sinter into the exposed silicon in areas 22.23. For chemical etching More excess palladium is removed from the glass 14.15. After that, relatively thick Silver raised contacts 24,25 are electrodeposited onto the palladium.

典型的には、各隆起接点２４．２５の厚さは約０．０２５４ｍｍ　（約０．００ １インチ）である。Typically, each raised contact 24.25 has a thickness of about 0.0254 mm (about 0.00 mm). 1 inch).

最後に後ろ側のメタライゼーション層２６．２７をエンハンス層２０．２１の上 に付着する。印刷回路板接点８．９とメタライゼーション層２６．２７の間を延 びる適切なすみ肉２８．２９を確実に形成するために、メタライゼーション！２ １３．２７を選択して適当なはんだ流、またはその他の導電性接合物質流をそれ らの表面に付着する。メタライゼーション層２６゜２７は無電解ニッケルめっき または無電解金めっきで形成でき、またはクロームの蒸着層と、その上の銀の蒸 着層と、その上の金の蒸着技術とにより形成できる。また、はんだ被覆を含む他 のメタライゼーション層も使用できる。利用できる金属の完全な溶解、またはメ タライゼーション層２６゜２７の最終的な脱湿用（ｄｅｖｅｔｔＩｎｇ）を起す ことなしに、はんだにぬれることを促進するために層２［ｉ、　２７の相対的な 金属厚さを選択することがしばしば重要である。このようにして、メタライゼー ション層２６．２７が印刷回路板接点８，９に対してほぼ直角に向けられている 場合でも、メタライゼーション層２６．２７と印刷回路板接点８．９との間の良 好な接合の完全性を確保できる。メタライゼーション層２６、２７の１つの好適 な実施例は、ｎ一層２０．２１の附近からスタートして、下記の層を含む： １、クロムの７００オングストロ一ム層；２、クロムと銀の混合物の２０００オ ングストロ一ム層；３、２９００オングストロームの銀層；４、１８００オング ストロームの金層。Finally, add the back metallization layer 26.27 on top of the enhancement layer 20.21. Attach to. Extending between the printed circuit board contact 8.9 and the metallization layer 26.27 Metallization to ensure proper fillet 28.29 that expands! 2 13.27 and apply a suitable solder stream or other conductive bonding material stream to it. It adheres to the surface of Metallization layers 26 and 27 are electroless nickel plating Alternatively, it can be formed by electroless gold plating, or it can be formed by depositing a layer of chromium and a layer of silver on top. It can be formed by depositing a layer and depositing gold thereon. Also includes solder coating and other metallization layers can also be used. Complete melting of available metals or The final dehumidification of the talization layer 26°27 takes place. The relative values of layer 2 [i, 27] to promote solder wetting without Selection of metal thickness is often important. In this way, the metallizer layer 26,27 is oriented approximately at right angles to the printed circuit board contacts 8,9. Even if the contact between the metallization layer 26.27 and the printed circuit board contact 8.9 is Good bond integrity can be ensured. One preferred embodiment of metallization layers 26, 27 An example embodiment includes the following layers, starting at around 20.21 n layers: 1. 700 angstrom layer of chromium; 2. 2000 angstrom layer of chromium and silver mixture 1 Angstrom layer; 3, 2900 angstrom silver layer; 4, 1800 angstrom layer; Strom's Gold Layer.

クローム層はシリコンに良く接合し、銀層ははんだに良く溶解し、金層は銀層を 酸化から保護する。The chrome layer bonds well to silicon, the silver layer dissolves well in solder, and the gold layer bonds well to silicon. Protects from oxidation.

第３図はウェハー製造プロセスの終了時におけるウェハー２５の一部を示す。こ の段階においては、次にウエノ１−をのこぎりで、またはその他のやり方で個々 のダイすなわち半導体素子１．２に切断する。それら個々の半導体素子は希望の 形にでき、正方形、長方形、三角形、五角形および六角形のような形は全て適当 である。選択した形状とは無関係に、各半導体素子１．２は少くとも１つのベー ス３１゜３２を形成しなければならない。最終的に組立てられたダイオードがベ ース３１．３２の上にのせられるようにするために、それらのベースは適度に平 らである。FIG. 3 shows a portion of wafer 25 at the end of the wafer fabrication process. child In step 1, the pieces are then individually sawed or otherwise The semiconductor device 1.2 is cut into dies or semiconductor devices 1.2. Those individual semiconductor elements are Shapes such as squares, rectangles, triangles, pentagons and hexagons are all suitable. It is. Regardless of the chosen geometry, each semiconductor element 1.2 has at least one base. 31°32 must be formed. The final assembled diode Their bases should be reasonably flat so that they can rest on top of the base 31.32. It is et al.

ウェハーを個々の半導体素子１，２に切断した後で、２個の半導体素子１，２を 中心ボンド３０ではんだづけ、または導電性エポキシにより付着してバイポーラ ダイオードを組立てる。この実施例においては、中心ボンド３０は鉛が９５％、 すずが５％で構成され、融点が約３１５℃であるはんだである。はんだ円板を接 点２４と２５の間の場所に固定し、組立体を加熱して希望のボンドを形成する。After cutting the wafer into individual semiconductor elements 1 and 2, the two semiconductor elements 1 and 2 are Bipolar soldered with center bond 30 or attached with conductive epoxy Assemble the diode. In this embodiment, the center bond 30 is 95% lead; The solder is composed of 5% tin and has a melting point of about 315°C. Connect the solder disc It is secured in place between points 24 and 25 and the assembly is heated to form the desired bond.

ここで用いるはんだは、ダイオードを所定場所に取付けるために用いるはんだの 融点より高い融点を持つものを選択せねばならない。The solder used here is the same as the solder used to mount the diode in place. One must choose one with a melting point higher than the melting point.

２個の半導体素子１．２は、平らなｐ−ｎ接合１０と１１が互いに向き合うよう にして、回転して互いに整列させる。The two semiconductor elements 1.2 are arranged so that the flat p-n junctions 10 and 11 face each other. and rotate them to align them with each other.

メタライゼーション層２８．２７は相互間とｐ−ｎ接合１０．１１に対して平行 に、かつベース３１．３２に対して垂直に向けられる。このような構造により、 このバイポーラダイオードはベース３１．３２をそれぞれの印刷回路板接点８， ９の上に置き、鋭敏なｐ−ｎ接合＋０．１１を印刷回路板接点８，９のほぼ中間 に位置させて取付けることができる。このようにして、ｐ−ｎ接合１０．１１は 分離され、保護される。The metallization layers 28.27 are parallel to each other and to the p-n junction 10.11. and perpendicular to the base 31.32. With this structure, This bipolar diode connects the base 31, 32 to each printed circuit board contact 8, 9 and connect the sensitive p-n junction +0.11 approximately midway between printed circuit board contacts 8 and 9. It can be located and installed. In this way, the p-n junction 10.11 Separated and protected.

第１図と第２図に示されているダイオードは広い範囲の寸法および広い範囲の電 気的特性を持つようにして形成できる。下記の情報は１つの好適な実施例を構成 するために単に与えたものであって、もちろん本発明を限定するものでは決して ない工 Ａ、外面４，５の寸法：　０．０９１４ｃ＋ｎ　Ｘ　Ｏ，０９１４ｃｍ　；Ｂ、 外面４と５の間の距離：　０．１１４３ｃｍ　；Ｃ９領域２２と２３の間の距離 ：　０．００８　ａｍ　；Ｄ、降　伏　電　圧　：　２０Ｖ　。The diodes shown in Figures 1 and 2 can be used in a wide range of dimensions and in a wide range of voltages. It can be formed to have physical properties. The information below constitutes one preferred embodiment. They are provided merely to facilitate the understanding of the invention and are of course not intended to limit the invention in any way. No work A, dimensions of outer surfaces 4 and 5: 0.0914c+n X O, 0914cm; B, Distance between outer surfaces 4 and 5: 0.1143 cm; distance between C9 regions 22 and 23 : 0.008 am; D, yield voltage: 20V.

Ｅ、試験電流　：１ｍＡ； Ｆ、動作ビーク電圧　：　１５Ｖ　； Ｇ、動作ピーク電圧における洩れ電流＝１０μＡ　；Ｈ６最高ビークサージ電圧 ：　４０Ｖ　。E, test current: 1mA; F, operating peak voltage: 15V; G, leakage current at operating peak voltage = 10 μA; H6 maximum peak surge voltage : 40V.

１、最高ビークサージ電流：　２０Ａ　。1. Maximum peak surge current: 20A.

」、最高容量　：３００ｐｆ； に、ビークサージエネルギー消費： ０．００５ジニール（１０μ５ｅｃ） ０．０５　ジュール（１ｍｓｅｃ） 第１図と第２図のバイポーラツェナーダイオードは、メタライゼーション層２８ ．２７を印刷回路板のそれぞれの接点８．９へ電気的に相互接続する、はんだま たはエポキシのような物質のすみ肉で印刷回路板へ取付けられる。適当であるこ とが判明しているこの取付は作業の１つのやり方を以下に説明する。”, maximum capacity: 300pf; The beak surge energy consumption: 0.005 ginyl (10μ5ec) 0.05 Joule (1msec) The bipolar Zener diodes of FIGS. 1 and 2 have metallization layers 28 ．． 27 to the respective contacts 8.9 of the printed circuit board, electrically interconnecting them. It is attached to a printed circuit board with a fillet of a material such as epoxy or epoxy. Is it appropriate? One way of performing this installation, which has been found to be the case, is described below.

第１に、印刷回路板３４を清浄にしてから１００℃の炉の中で１時間乾燥し、そ れから適当なエポキシ３３を印刷回路板の接点８と９の間に付着する。このエポ キシ３３は硬化後は高い電気抵抗値を示す種類のものである。カルホルニア州カ ーデニア（Ｃａｒｄｃｎｉａ）所在のエイプルスティック社（Ａｂｌｅｓｔｌｃ ｋ　Ｃｏ、）により＾ｂｌｅｂｏｎｄ　７７−２ＬＴＣとして市販されている物 質がエポキシ３３として使用するのに適当であることが判明している。次に、中 央のはんだボンド３０が絶縁エポキシ３３の上に中心を置き、各メタライゼーシ ョン層２６゜２７がそれぞれの１つの接点８．９へ電気的に接触するように、組 立てられたダイオードを第２図に示すように印刷回路板の上に置く。次に、ダイ オードが取付けられている印刷回路板を炉の中に入れて絶縁エポキシ３３を硬化 する。絶縁エポキシ３３が硬化してから各メタライゼーション層２６゜２７には んだペーストを付着する。Ａ　Ｉ　ｐｈａブランドａｌｌフラックス（ＲＭＡ） 付きＡｌｐｈａブランド６０／４０はんだとして市販されている種類のはんだが 適当であることが判明している。次に、８０℃の適当な炉の中に１５分間入れて そのはんだペーストを硬化させてから、赤外線炉または気相はんだづけ機の内部 ではんだを再び融かして、メタライゼーション層２８．２７をそれぞれの接点８ ，９へ相互接続するすみ肉２８゜２９を形成する。このはんだの再融解作業では 中心はんだボンド３０を弱くすることがある高温にしてはならない。First, the printed circuit board 34 is cleaned and dried in a 100°C oven for one hour; A suitable epoxy 33 is then applied between contacts 8 and 9 of the printed circuit board. This epo The resin 33 is of a type that exhibits a high electrical resistance value after curing. california Ablestlc, located in Cardcnia. Commercially available as blebond 77-2LTC by K.Co. The quality has been found to be suitable for use as Epoxy 33. Next, inside The center solder bond 30 is centered on the insulating epoxy 33 and each metallization assembly so that the layer 26, 27 is in electrical contact with one contact 8.9 in each case. Place the erected diode on the printed circuit board as shown in FIG. Next, die Place the printed circuit board with the ord installed in the oven to harden the insulating epoxy 33. do. After the insulating epoxy 33 has cured, each metallization layer 26, 27 is Apply solder paste. AI pha brand all flux (RMA) The type of solder sold commercially as Alpha brand 60/40 solder is It has been found to be appropriate. Next, put it in a suitable oven at 80℃ for 15 minutes. Let that solder paste harden and then heat it inside an infrared oven or vapor phase soldering machine. Then melt the solder again and attach the metallization layers 28, 27 to each contact 8. , 9 to form fillets 28°29. In this solder remelting process, Avoid high temperatures, which can weaken the center solder bond 30.

はんだの再融解作業を行った後で、印刷回路板を清浄にし、試験してから、希望 によってはダイオードの上に封止エポキシを付着し、その封止エポキシを中心は んだボンド３０の周囲に流す。この封止エポキシを１５０℃で１時間加熱して硬 化し、それから印刷回路板を再び電気的に試験する。上記の非導電性を封止エポ キシとして使用できる。After performing the solder remelting operation, the printed circuit board must be cleaned, tested, and as desired. In some cases, a sealing epoxy is deposited on top of the diode, and the center of the sealing epoxy is Flow around the solder bond 30. This sealing epoxy is heated at 150℃ for 1 hour to harden it. and then electrically test the printed circuit board again. Epo seal the above non-conductive Can be used as a glue.

ある用途においては、上記８０／４０はんだペーストの代りに導電性エポキシを 使用することが好ましいことがある。In some applications, conductive epoxy may be used in place of the 80/40 solder paste described above. It may be preferable to use

この場合には、上記のはんだ再融解作業は省かれ、その代りに、使用する導電性 エポキシを硬化させるのに適当な炉内での硬化作業を用いる。適当な導電性エポ キシが前記エイプルスティック社によりＡｂｌｅｂｏｎｄ　８４−Ｉ　ＬＭＩＴ として市販されている。In this case, the solder remelting operation described above is omitted, and instead the conductive A suitable oven curing operation is used to cure the epoxy. suitable conductive epoxy Ablebond 84-I LMIT by Aplestick Co., Ltd. It is commercially available as.

以上説明した構造の１つの大きな利点は、ベース３１．３２として作用するメタ ライゼーション層２８．２７の間を延長する任意の側でバイポーラツェナーダイ オードを取付けることができることである。したがって、ダイオードを慎重に回 して位置合わせすることは不要である。更に、ダイオードの電気的性能に悪影響 を及ぼすことなしにダイオードをひつくり返えすことができる。それらの位置の 全てにおいて、接合領域３は印刷回路板接点８．９から上方に離れて配置され、 それにより、すみ肉２８．２９のはんだまたは導電性エポキシとｐ−ｎ接合１０ ．１１との望ましくない接触の可能性が低くなる。One major advantage of the structure described above is that the metal acting as the base 31.32 bipolar zener die on any side extending between the lization layers 28 and 27; It is possible to install an ord. Therefore, carefully rotate the diode. It is not necessary to perform alignment. Moreover, it has a negative effect on the electrical performance of the diode. The diode can be turned over without causing any damage. of those positions In all, the bonding area 3 is arranged upwardly away from the printed circuit board contacts 8.9; Thereby fillet 28.29 solder or conductive epoxy and p-n junction 10 ．． 11 is less likely to occur.

もちろん、以上説明したバイポーラツェナーダイオードに対しては多くの変更を 加えることができる。たとえば、放熱のため、および印刷回路板接点８，９への 接合面積を広くするために、メタライゼーション層２６．２７の上に希望の厚さ の金属パッドを置くことができる。更に希望によっては、接合領域３に保護被覆 を設けることができる。そのような保護被覆は特定の環境においては望ましいこ とがあり、たとえば、半導体素子１と２の間の接合領域３の中に流れこむことが でき、それから高温で乾燥できる半導体級ワニス、エポキシまたはポリイミド物 質を使用して保護被覆を設番ノることができる。また、上で指摘したように、ｐ ″″″基板出発し、それからｐ−ｎ接合を形成するために適当なｎ形ドーパント をドーピングすることにより、ドーパントの種類を逆にできる。Of course, there are many modifications to the bipolar Zener diode described above. can be added. For example, for heat dissipation and to printed circuit board contacts 8,9. To increase the bonding area, apply the desired thickness on top of the metallization layer 26.27. You can put a metal pad on it. Furthermore, if desired, a protective coating can be applied to the joining area 3. can be provided. Such protective coatings may be desirable in certain environments. For example, it may flow into the junction region 3 between the semiconductor elements 1 and 2. Semiconductor grade varnish, epoxy or polyimide material that can be made and then dried at high temperature Protective coatings can be installed using quality materials. Also, as pointed out above, p ″″″Start with the substrate and then add a suitable n-type dopant to form a p-n junction. By doping with , the type of dopant can be reversed.

また、本発明はユニポーラダイオードを製造するために用いることができる。第 ５図に示すように、これは、半導体素子２からｐ−ｎ接合を無くして簡単にした 半導体素子２′を形成することによって簡単に行うことができる。この簡単にし た半導体素子２′は、ｎ＋＋エンハンス表面を領域２３内に設け、かつエポキシ 領域１９を不要とすることを除いて、半導体素子２に非常に良く似ている。この 簡単にした半導体素子２′は、半導体索子１のｐ−ｎ接合から印刷回路板接点９ へ短絡路を構成するだけである。このようにして、２個の回路板接点８と９の間 のユニポーラｐ−ｎ接合路すなわち単−ｐ−ｎ接合路が得られる。もちろん、こ のユニポーラダイオードは、簡単にした半導体素子２′のように、前記ドーパン ト種とは逆のドーパント種で製造することもできる。The invention can also be used to manufacture unipolar diodes. No. As shown in Figure 5, this is simplified by eliminating the p-n junction from semiconductor element 2. This can be easily accomplished by forming the semiconductor element 2'. make this easy The semiconductor device 2' has an n++ enhanced surface within the region 23 and an epoxy It is very similar to semiconductor device 2, except that region 19 is not required. this The simplified semiconductor component 2' extends from the p-n junction of the semiconductor wire 1 to the printed circuit board contact 9. It only constructs a short circuit to. In this way, between the two circuit board contacts 8 and 9 A unipolar pn junction path or a single pn junction path is obtained. Of course, this In the unipolar diode, as in the simplified semiconductor device 2', the dopant It can also be produced with a dopant species opposite to the dopant species.

別の実施例においては、簡単にした半導体素子２′の代りに、同様な形状構造の ブロック金属導体を用いることができる。この金属ブロックのはんだ接合と導電 特性が適正に選択されたとすると、上記と同じ取付は技術を使用できる。In another embodiment, instead of the simplified semiconductor component 2', a similar geometrical structure can be used. Block metal conductors can be used. This metal block solder joints and conductivity Provided the characteristics are properly selected, the same installation techniques described above can be used.

以上の説明から、著しく簡単で、効果的かつコンパクトな表面取付は技術を可能 にするユニポーラダイオードおよびバイポーラダイオードについて説明したこと は明らかである。本発明は、整流器、信号ダイオード、ピンダイオード、ツェナ ーダイオード、過渡抑制ダイオード、およびその他の種類のダイオードを含めて 広範囲の二端子半導体デバイスに使用するのに適している。From the above description, it can be seen that a remarkably simple, effective and compact surface mounting technique is possible. What we have explained about unipolar and bipolar diodes is clear. The present invention is suitable for rectifiers, signal diodes, pin diodes, zener – including diodes, transient suppression diodes, and other types of diodes. Suitable for use in a wide range of two-terminal semiconductor devices.

したがって、以上の説明は本発明を限定するものではなくて例示的なものと見な すべきであること、および本発明の技術的範囲を決定しようと意図されているも のは、全ての均等物を含めて、下記の請求の範囲であることを理解されることを 意図するものである。Accordingly, the above description should be considered illustrative rather than limiting. and what is intended to determine the scope of the invention. It is understood that the following claims, including all equivalents, are: It is intended.

国際調査報告international search report

Claims (10)

【特許請求の範囲】[Claims] １．取付け面に平行におのおのが向けられている一対の隔てられている接点（８ ，９）を備える取付け表面（３４）の上に取付けるための表面取付けダイオード において、半導体素子（１）がベース（３１）と、このベースから離れて延び、 互いに向き合う第１の面（４）および第２の面（３６）を有し、前記半導体素子 （１）は、向き合う面（４，３６）の間に電気的に相互接続されて、ベース（３ １）から隔てられたｐ−ｎ接合（１０）と、第１の向き合う面（４）に合致する ために配置された第１の露出した導電層（２６）と、ｐ−ｎ接合（１０）が２つ の露出されている導電層（２６，２７）の間に挟まれるように、第１の露出され ている導電層（２６）に全体として平行に配置されている第２の露出されている 導電層（２７）へ第２の露出面（３６）を電気的に相互接続する手段と、導電性 固定剤の２つの質量（２８，２９）とを備え、各前記導電層（２６，２７）はそ れぞれの露出された導電面を形成し、導電層（２６，２７）の各露出面が、隔て られている接点（８，９）のそれぞれの１つに接触し、かつ取付け面から離れて 延びるように、前記ベース（３１）は取付け平面に平行に向けられ、各前記質量 は接点（８，９）のそれぞれ１つと関連する導電層（２６，２７）の露出面とに 固定されてすみ肉を形成し、前記固定剤は、流体状態にある時は、毛管作用によ り露出面の上へ動くように選択されることを特徴とする表面取付けダイオード。1. A pair of spaced contacts (8 , 9) for mounting on a mounting surface (34) comprising: in which a semiconductor element (1) is connected to a base (31) and extends away from the base; the semiconductor element has a first surface (4) and a second surface (36) facing each other; (1) are electrically interconnected between facing surfaces (4, 36) and base (3); 1) coincides with the p-n junction (10) separated from the first facing surface (4) a first exposed conductive layer (26) arranged for The first exposed conductive layer (26, 27) is sandwiched between the exposed conductive layers (26, 27). a second exposed conductive layer (26) disposed generally parallel to the conductive layer (26); means for electrically interconnecting the second exposed surface (36) to the conductive layer (27); two masses (28, 29) of fixative, each said conductive layer (26, 27) having its own forming respective exposed conductive surfaces, each exposed surface of the conductive layer (26, 27) contact one of each of the contacts (8, 9) attached and away from the mounting surface. As extending, said base (31) is oriented parallel to the mounting plane and each said mass on each one of the contacts (8, 9) and the exposed surface of the associated conductive layer (26, 27). fixed to form a fillet, said fixative, when in a fluid state, being absorbed by capillary action. A surface mount diode characterized in that the surface mount diode is selected to move over an exposed surface. ２．相互接続手段は、半導体素子（１）のｐ−ｎ接合とは逆極性の付加ｐ−ｎ接 合（１１）を備える請求の範囲第１項記載の表面取付けダイオード。2. The interconnection means includes an additional p-n junction of opposite polarity to the p-n junction of the semiconductor element (1). 2. A surface mount diode as claimed in claim 1, comprising: (11). ３．相互接続手段は、半導体素子（１）に形が一致する相互接続素子（２）を備 える請求の範囲第１項記載の表面取付けダイオード。3. The interconnection means comprises an interconnection element (2) conforming in shape to the semiconductor element (1). A surface mount diode as claimed in claim 1. ４．第１の外面（４）と第１の内面（３６）を有する第１の半導体素子（１）が それらの間に第１のｐ−ｎ接合（１０）を形成する手段を備え、第２の外面（５ ）と第２の内面（３４）を有する第２の半導体素子（２）がそれらの間に第２の ｐ−ｎ接合（１１）を形成する手段を備え、第１の手段は第１の内面と第２の内 面を外面の間で電気的に相互接続し、かつ機械的に一緒に固定して、外面の間を 延長するベースを構成する統合されたユニットを形成し、第１のｐ−ｎ接合（１ ０）と第２のｐ−ｎ接合（１１）は逆極性で向けられ、第１のｐ−ｎ接合と第２ のｐ−ｎ接合が第１の導電面と第２の導電面（２６，２７）の間に位置させられ 、導電面（２６，２７）がベースから離れて延びるように、第１の導電面と第２ の導電面（２６，２７）は第１の外面と第２の外面（４，５）の上に設けられ、 前記導電面は、ベースに沿って延長しているそれぞれの取付け表面へ表面取付け するために位置させられることを特徴とする表面取付け可能なバイポーラダイオ ード。4. A first semiconductor element (1) having a first outer surface (4) and a first inner surface (36) means for forming a first p-n junction (10) between them; ) and a second inner surface (34) with a second semiconductor element (2) having a second inner surface (34) between them. means for forming a p-n junction (11), the first means connecting the first inner surface and the second inner surface; The surfaces are interconnected electrically between the surfaces and mechanically secured together to connect the surfaces between the surfaces. The first p-n junction (1 0) and the second p-n junction (11) are oriented with opposite polarity, the first p-n junction and the second p-n junction (11) a p-n junction is located between the first conductive surface and the second conductive surface (26, 27). , the first conductive surface and the second conductive surface (26, 27) extend away from the base. conductive surfaces (26, 27) are provided on the first outer surface and the second outer surface (4, 5); The conductive surfaces are surface mounted to respective mounting surfaces extending along the base. A surface mountable bipolar diode characterized by being positioned to code. ５．導電面（２６，２７）は互いに平行に、かつベースをほぼ横切るように向け られる請求の範囲第１項または第４項記載のダイオード。5. The conductive surfaces (26, 27) are oriented parallel to each other and substantially across the base. A diode according to claim 1 or 4. ６．統合されたユニットのベースは、第１の接点と第２の接点（８，９）を構成 する取付け表面の上に設けられ、各前記接点はベースに平行に向けられ、かつ、 導電面（２６，２７）が接点（８，９）から離れる向きに横方向へ延びるように 導電面（２６，２７）のそれぞれ１つに接触し、導電性固定剤の第１のすみ肉お よび第２のすみ肉（２８，２９）が接点（８，９）とそれぞれの導電面（２６， ２７）の間に接合される請求の範囲第５項記載のダイオード。6. The base of the integrated unit constitutes a first contact and a second contact (8,9) each said contact is oriented parallel to the base, and The conductive surfaces (26, 27) extend laterally away from the contacts (8, 9). In contact with each one of the conductive surfaces (26, 27), the first fillet of the conductive fixative and second fillets (28, 29) connect the contacts (8, 9) with the respective conductive surfaces (26, 29). 27). The diode according to claim 5, which is connected between 27) and 27). ７．それぞれの第１の面（３６，３８）とそれらの第１の面に互いに平行に向け られたそれぞれの第２の面（４，５）をおのおの構成する第１の半導体素子およ び第２の半導体素子（１，２）と、導電層を構成し、第２の面（４，５）のそれ ぞれ１つの上におのおの位置させられた第１のメタライゼーション層および第２ のメタライゼーション層（２６，２７）と、半導体素子（１，２）のそれぞれ１ つの第１の面（３６，３８）と第２の面（４，５）の間におのおの位置させられ 、かつ電気的に相互接続された第１のｐ−ｎ接合および第２のｐ−ｎ接合（１０ ，１１）と、第１の半導体素子および第２の半導体素子（１，２）を一緒に機械 的に固定し、かつ電気的に相互接続して、第２の面（４，５）を、逆極性で向け られている第１のｐ−ｎ接合および第２のｐ−ｎ接合（１０，１１）に対して隔 てられて平行な関係に保持する手段とを備えることを特徴とする表面取付け可能 なバイポーラダイオード。7. the respective first faces (36, 38) and their first faces oriented parallel to each other; The first semiconductor element and the first semiconductor element constituting each of the second surfaces (4, 5) and the second semiconductor element (1, 2), forming a conductive layer, and that of the second surface (4, 5). a first metallization layer and a second metallization layer each positioned on a respective one; metallization layers (26, 27) and semiconductor elements (1, 2), respectively. each located between the first surface (36, 38) and the second surface (4, 5). , and a first p-n junction and a second p-n junction (10 , 11), the first semiconductor element and the second semiconductor element (1, 2) together by machine. and electrically interconnected, with the second surfaces (4, 5) oriented with opposite polarity. spaced apart for the first p-n junction and the second p-n junction (10, 11) and a means for holding the surface in parallel relationship. bipolar diode. ８．おのおの取付け面に平行に向けられている第１の接触面および第２の接触面 （８，９）の間に表面取付けされるバイポーラダイオードにおいて、第１の半導 体素子（１）は、間に第１のｐ−ｎ接合（１０）を構成する第１の半導体領域と 第２の半導体領域および第１の領域上の第１の導電面（２６）を備え、第２の半 導体素子（２）は、問に第２のｐ−ｎ接合（１１）を構成する第３の半導体領域 と第４の半導体領域および第３の領域上の第２の導電面（２７）を備え、第１の 手段（３０）が第１の半導体素子および第２の半導体素子（１，２）を一緒に機 械的に固定して、下面と少くとも第１の側面および第２の側面を有する統合され たユニットを構成し、第１の導電面および第２の導電面（２６，２７）は側面（ ４，５）のそれぞれの向き合う部分上に位置させられ、第１の手段（３０）は、 下面から隔てられた場所（３）において第２の領域と第４の領域を電気的に相互 接続する手段を備え、前記下面は接触面（８，９）を橋絡するために位置させら れ、各導電面（２６，２７）は接触面（８，９）のそれぞれ１つに接触し、かつ 取付け面に対して角度を成し、第２の手段（２８，２９）が各導電面（２６，２ ７）をそれぞれの接触面へ電気的に相互接続して、かつ物理的に固定し、前記第 ２の手段（２８，２９）は、流体状態にある時に毛管作用により導電面（２６， ２７）を横切って動く導電性金属を儀えることを特徴とするバイポーラダイオー ド。8. a first contact surface and a second contact surface oriented parallel to each mounting surface; In the bipolar diode surface-mounted between (8, 9), the first semiconductor The body element (1) has a first semiconductor region forming a first p-n junction (10) therebetween. a second semiconductor region and a first conductive surface (26) on the first region; The conductive element (2) is a third semiconductor region that constitutes a second p-n junction (11). and a fourth semiconductor region and a second conductive surface (27) on the third region; Means (30) machine the first semiconductor element and the second semiconductor element (1, 2) together. mechanically secured to the integrated base having a lower surface and at least a first side and a second side. The first conductive surface and the second conductive surface (26, 27) form a side surface ( 4, 5), the first means (30) comprising: The second region and the fourth region are electrically connected to each other at a location (3) separated from the lower surface. means for connecting, said lower surface being positioned to bridge the contact surfaces (8, 9); each conductive surface (26, 27) is in contact with a respective one of the contact surfaces (8, 9), and At an angle to the mounting surface, second means (28, 29) connect each conductive surface (26, 2 7) electrically interconnected and physically fixed to the respective contact surfaces; The second means (28, 29) conductive surfaces (26, 29) by capillary action when in a fluid state. 27) A bipolar diode characterized by having a conductive metal moving across it. Do. ９．第１と第３の各領域はそれぞれの外面（４，５）を構成し、第１の導電面お よび第２の導電面（２６，２７）は第１の領域および第３の領域の外面（４，５ ）の上にそれぞれの位置させられ、第２の領域と第４の領域は第１の領域と第３ の領域の上にそれぞれ中心を置かれ、第１の手段（３０）は、２つの第２の領域 および第４の領域が狭い間隔をおいて平行な関係で隔てられるように、第２の領 域と第４の領域の間に固定された導電性素子を備える請求の範囲第８項記載のバ イポーラダイオード。9. Each of the first and third regions constitutes a respective outer surface (4,5) and includes a first conductive surface and a third conductive surface. and the second conductive surfaces (26, 27) are connected to the outer surfaces (4, 5) of the first region and the third region. ), and the second region and the fourth region are respectively positioned above the first region and the third region. The first means (30) are respectively centered over the two second areas. and a second region such that the fourth region is separated in closely spaced parallel relationship. 9. The battery according to claim 8, comprising a conductive element fixed between the region and the fourth region. Ipolar diode. １０．第２の手段（２８，２９）の導電性物質が導電性素子と第２の領域および 第４の領域へ接触することを阻止するために、導電性素子と第２の領域および第 ４の領域は下面から隔てられる請求の範囲第９項記載のバイポーラダイオード。10. The conductive material of the second means (28, 29) is connected to the conductive element and the second region and the conductive element and the second region and the fourth region to prevent contact with the fourth region; 10. The bipolar diode of claim 9, wherein the region 4 is separated from the bottom surface.
JP62503012A 1986-05-02 1987-04-22 Surface mountable diode Expired - Lifetime JPH0666409B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US06/859,126 US4709253A (en) 1986-05-02 1986-05-02 Surface mountable diode
US859,126 1986-05-02
PCT/US1987/000894 WO1987006767A1 (en) 1986-05-02 1987-04-22 Surface mountable diode

Publications (2)

Publication Number Publication Date
JPH01500154A true JPH01500154A (en) 1989-01-19
JPH0666409B2 JPH0666409B2 (en) 1994-08-24

Family

ID=25330112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62503012A Expired - Lifetime JPH0666409B2 (en) 1986-05-02 1987-04-22 Surface mountable diode

Country Status (6)

Country Link
US (1) US4709253A (en)
EP (1) EP0266412B1 (en)
JP (1) JPH0666409B2 (en)
KR (1) KR960003856B1 (en)
DE (1) DE3780564T2 (en)
WO (1) WO1987006767A1 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3855533T2 (en) * 1987-12-28 1997-01-23 Fuji Electric Co Ltd Insulated gate semiconductor device
US5019535A (en) * 1989-03-28 1991-05-28 General Electric Company Die attachment method using nonconductive adhesive for use in high density interconnected assemblies
US5018989A (en) * 1990-09-21 1991-05-28 Amp Incorporated Electrical connector containing components and method of making same
US5094629A (en) * 1990-09-21 1992-03-10 Amp Incorporated Electrical connector containing components and method of making same
US5147223A (en) * 1990-09-21 1992-09-15 Amp Incorporated Electrical connector containing components and method of making same
US5455734A (en) * 1991-04-29 1995-10-03 Trw Inc. Insert device for electrical relays, solenoids, motors, controllers, and the like
US5590058A (en) * 1991-04-29 1996-12-31 Trw Inc. Battery monitor for unobstrusive installation with a battery connector
US5692917A (en) * 1991-04-29 1997-12-02 Trw Inc. Computer hardware insert device for software authorization
US5428288A (en) * 1991-04-29 1995-06-27 Trw Inc. Microelectric monitoring device
US5414587A (en) * 1991-04-29 1995-05-09 Trw Inc. Surge suppression device
GB2255675B (en) * 1991-05-10 1995-09-27 Technophone Ltd Circuit assembly
US5219296A (en) * 1992-01-08 1993-06-15 Amp Incorporated Modular connector assembly and method of assembling same
JP3337405B2 (en) * 1996-12-27 2002-10-21 シャープ株式会社 Light-emitting display element, method for connecting to light-emitting substrate, and method for manufacturing
JP2001217380A (en) * 2000-02-04 2001-08-10 Hitachi Ltd Semiconductor device and its manufacturing method
CN100452452C (en) * 2005-05-17 2009-01-14 财团法人工业技术研究院 Light emitting device with LED flipped side-structure
CN103137646A (en) * 2013-03-15 2013-06-05 中国科学院微电子研究所 Gating device unit for bipolar resistive random access memory cross array integration mode
US10879211B2 (en) 2016-06-30 2020-12-29 R.S.M. Electron Power, Inc. Method of joining a surface-mount component to a substrate with solder that has been temporarily secured
DE102023102962A1 (en) * 2023-02-07 2024-08-08 Ams-Osram International Gmbh METHOD FOR PRODUCING A DUAL-CHIP OPTOELECTRONIC COMPONENT AND DUAL-CHIP OPTOELECTRONIC COMPONENT

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3300710A (en) * 1963-01-23 1967-01-24 Dalton L Knauss Voltage reference circuit with low incremental impedance and low temperature coefficient
CH466427A (en) * 1967-12-04 1968-12-15 Bbc Brown Boveri & Cie Fuses with fusible links for electrical devices, in particular semiconductor elements
US3736475A (en) * 1969-10-02 1973-05-29 Gen Electric Substrate supported semiconductive stack
JPS5310862Y2 (en) * 1972-12-28 1978-03-23
US4075649A (en) * 1975-11-25 1978-02-21 Siemens Corporation Single chip temperature compensated reference diode and method for making same
JPS52137279A (en) * 1976-05-12 1977-11-16 Hitachi Ltd Semiconductor device for optical coupling
US4136349A (en) * 1977-05-27 1979-01-23 Analog Devices, Inc. Ic chip with buried zener diode
US4213806A (en) * 1978-10-05 1980-07-22 Analog Devices, Incorporated Forming an IC chip with buried zener diode
US4412376A (en) * 1979-03-30 1983-11-01 Ibm Corporation Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation
JPS55156482U (en) * 1979-04-26 1980-11-11
JPS5644591A (en) * 1979-09-20 1981-04-23 Shinobu Akima Pipe body for heat exchanger
US4349394A (en) * 1979-12-06 1982-09-14 Siemens Corporation Method of making a zener diode utilizing gas-phase epitaxial deposition
US4319257A (en) * 1980-01-16 1982-03-09 Harris Corporation Low thermal coefficient semiconductor device
JPS572560A (en) * 1980-06-06 1982-01-07 Hitachi Ltd High voltage semiconductor device
US4516223A (en) * 1981-08-03 1985-05-07 Texas Instruments Incorporated High density bipolar ROM having a lateral PN diode as a matrix element and method of fabrication
US4450021A (en) * 1982-02-22 1984-05-22 American Microsystems, Incorporated Mask diffusion process for forming Zener diode or complementary field effect transistors
JPS5975659A (en) * 1982-10-22 1984-04-28 Fujitsu Ltd Manufacture of semiconductor device
US4473941A (en) * 1982-12-22 1984-10-02 Ncr Corporation Method of fabricating zener diodes

Also Published As

Publication number Publication date
DE3780564T2 (en) 1993-03-11
DE3780564D1 (en) 1992-08-27
KR960003856B1 (en) 1996-03-23
KR880701464A (en) 1988-07-27
WO1987006767A1 (en) 1987-11-05
US4709253A (en) 1987-11-24
JPH0666409B2 (en) 1994-08-24
EP0266412A1 (en) 1988-05-11
EP0266412B1 (en) 1992-07-22

Similar Documents

Publication Publication Date Title
JPH01500154A (en) surface mountable diode
CA1068829A (en) Integrated test and assembly device
US4693770A (en) Method of bonding semiconductor devices together
US3903590A (en) Multiple chip integrated circuits and method of manufacturing the same
US6469397B2 (en) Resin encapsulated electrode structure of a semiconductor device, mounted semiconductor devices, and semiconductor wafer including multiple electrode structures
JPH10326806A (en) Semiconductor device and its manufacture
JPS60206087A (en) Method of producing small-sized electronic power source
JPS62202548A (en) Semiconductor device
JP2956786B2 (en) Synthetic hybrid semiconductor structure
JPH10242383A (en) Semiconductor device
JPS62113452A (en) Power semiconductor device
JP3758331B2 (en) Shunt resistor element for semiconductor device, mounting method thereof, and semiconductor device
JP2003124262A5 (en)
JPS6351538B2 (en)
JP3238825B2 (en) Surface mount type semiconductor device
US5887338A (en) Method for producing a temperature sensor with temperature-dependent resistance
KR20090031289A (en) Flip chip structure and method of manufacture
US3678346A (en) Semiconductor device and method of making the same
JPS58210643A (en) Semiconductor device
JPH0846248A (en) Thermoelectric element and its manufacture
JP2882009B2 (en) IC mounting method
JPH1079461A (en) Semiconductor integrated circuit device and manufacturing method thereof
JPH10242085A (en) Manufacture of semiconductor device
JPS615535A (en) Semiconductor device
JPS63220554A (en) Submount and its manufacture