JPH0147924B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an output buffer circuit.

In linear circuits such as operational amplifiers,
In order to facilitate connection with other circuits, an output buffer circuit with low output resistance is often required. One way to lower the output resistance of an output circuit including MOSFETs is to provide negative feedback to the common source circuit. An example of an output buffer circuit based on this method that has been widely used in the past is shown in FIG.

In Figure 1, MOSFET1 constitutes a source-grounded circuit with MOSFET2 as the load.
The signal V ₁ applied to the gate electrode of MOSFET 1 is amplified and an output signal V ₀ is output to the output terminal 6.
Among these, the MOSFET 2 may be another element that operates as a load element. The MOSFET 3 is a source follower circuit that receives the output signal V ₀ as an input and uses the MOSFET 4 as a load, and functions to feed back the output signal V ₀ to the gate electrode of the MOSFET 1 forming the source common circuit. On the other hand, MOSFET 4 operates as a source-grounded circuit with MOSFET 3 as a load for input signal V _IN , and outputs an amplified signal to the drain electrode side of MOSFET 4. Configure a source common circuit for input signal V _IN
The output of MOSFET 4 and the output of MOSFET 3 which constitutes the source follower circuit for the output signal V ₀ are as follows:
They are synthesized at the connection point 7 between the drain electrode of MOSFET 4 and the source electrode of MOSFET 3. In this case, the source common circuit inverts the phase of the input signal voltage and outputs it, but since the input and output of the source follower circuit have the same phase, they are combined at the connection point 7.
The output signals of MOSFETs 3 and 4 are in opposite phase to each other,
Feedback by the source follower circuit consisting of MOSFETs 3 and 4 becomes negative voltage feedback, and as a result, the output resistance of this output buffer circuit becomes low. Also
Since the amount of negative feedback due to the source follower of MOSFET 3 is approximately 1, the voltage gain of the negative feedback amplifier circuit composed of MOSFETs 1, 2, and 3 is also approximately 1, and the input signal V _IN of the output buffer circuit in FIG.
The voltage gain between the output signals _V0 is approximately equal to the gain of the common source circuit composed of MOSFETs 3 and 4. It is well known that the voltage gain of the common source circuit of MOSFETs 3 and 4 is approximately expressed as gm4/gm3, where gm3 and gm4 are the mutual conductances at the operating points of MOSFETs 3 and 4, respectively. The voltage gain of the output buffer circuit is determined by the mutual conductances gm3 and gm4 of the MOSFETs 3 and 4 at their respective operating points.

However, in such an output buffer circuit, the operating points and operating ranges of the input signal V _IN and output signal V ₀ are determined by the conditions of the externally connected circuit, so the operating points of MOSFETs 3 and 4 must be optimized. As a result, the voltage gain of such output buffer circuits is often limited to a relatively low value, a disadvantage of previous circuits requiring high gain.

The present invention aims to overcome this drawback and provide an output buffer circuit with a voltage gain much greater than that of the prior art, while keeping the output resistance as low as before.

According to the present invention, the first load element has one end connected to a first power source, and the first load element has a drain electrode connected to the other end of the first load element and a source electrode connected to the second power source. MOSFET with a drain electrode connected to the first power source and a gate electrode connected to the first power source.
a second MOSFET whose drain electrode is connected to the drain electrode of the first MOSFET and whose source electrode is connected to the gate electrode of the first MOSFET;
a third MOSFET whose drain electrode is connected to the source electrode of the MOSFET and whose gate electrode is connected to the third power supply; and a fourth MOSFET whose drain electrode is connected to the source electrode of the third MOSFET and whose source electrode is connected to the second power supply.
MOSFET, and a second load element having one end connected to the first power supply and the other end connected to the drain electrode of the fourth MOSFET,
An output buffer circuit is obtained in which the gate electrode of the fourth MOSFET serves as an input terminal and the drain electrode of the first MOSFET serves as an output terminal.

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 2 shows a simplified circuit configuration of an embodiment of the present invention, and in order to facilitate comparison with the conventional example shown in FIG. 1, the same numbers in the 10s are used for corresponding reference numbers. There is.

In FIG. 2, the MOSFET 12 has its drain electrode and gate electrode connected as a first load element to a drain electrode V _DD as a first power source, and
A drain electrode and a source electrode of the MOSFET 11 are respectively connected to a source electrode of the MOSFET 12 and a source power source V _SS serving as a second power source. The drain electrode of the second MOSFET 13 is connected to the drain electrode _VDD , the gate electrode and the source electrode are connected to the drain electrode and the gate electrode of the third MOSFET 11, respectively.
The drain electrode of MOSFET 20 is connected to the MOSFET 20.
The gate electrode is connected to the bias power supply V _B as the third power supply, and the gate electrode is connected to the third source electrode, and the fourth
The drain electrode of MOSFET 14 is connected to the MOSFET 14.
20, the source electrode is connected to the source power supply V _SS . The MOSFET 21 serves as a second load element, with its drain electrode and gate electrode connected to the drain power supply V _DD , and its source electrode connected to the drain electrode of the MOSFET 14. The gate electrode of the MOSFET 14 is connected to the input terminal 15 to receive an input signal. receiving, said MOSFET11
The drain electrode of is connected to the output terminal 16 to send out an output signal.

As seen in Figure 2, MOSFET11, 12,
MOSFET 13 is connected in the same way as MOSFETs 1, 2, and 3 in FIG. 1, and its operation is completely the same. Therefore, the output resistance and voltage gain of the circuit constituted by these MOSFETs 11, 12, and 13 are the same as those of the corresponding circuit shown in FIG. MOSFET
14 is configured to operate as a source-grounded circuit for the input signal V _IN , and MOSFET 20 is a gate-grounded circuit whose gate electrode is fixed by an appropriate bias power supply V _B , and its source electrode and drain electrode are connected to the drain electrode of MOSFET 14, respectively. ,
It is connected to the source electrode of MOSFET13.
In other words, MOSFET14 and 20 are MOSFET13
It operates as a cascode amplifier circuit with a load of
The input signal V _IN is amplified and output to the connection point 17 between the MOSFETs 13 and 20. The voltage gain of this cascade amplifier circuit is MOSFET 3 in FIG.
Similar to the voltage gain of the common source circuit by 4,
If the mutual conductances at the respective operating points of MOSFETs 13 and 14 are gm13 and gm14, they are approximately expressed as gm14/gm13. Also, the signal V ₁₁ at this connection point 17 is connected to the MOSFET.
14, 20, and 13 and the output of the source follower circuit for the output signal V ₀ by MOSFET 13, that is, the signal to which voltage negative feedback from the output signal V ₀ is added is also the first. This is similar to the signal V ₁ at the connection point 7 of MOSFETs 3 and 4 in the figure. MOSFET21
operates as a load element that increases the drain current to the MOSFET 14.

As is clear from the above explanation, the basic operation function of the output buffer circuit shown in FIG. 2 is the same as that of the conventional example shown in FIG.
By adding , it is possible to improve the operation of the amplifier circuit that determines the voltage gain, especially the operation of the source common circuit using the MOSFET 14, and achieves high performance with less influence from externally connected circuits. That is, by inserting a gate grounding circuit for MOSFET 20 with its gate electrode set to an appropriate voltage V _B , the operations of MOSFETs 13 and 14 are mutually isolated, and the drain current of MOSFET 14 is appropriately increased by the load element of MOSFET 21. By making it possible to
This not only increases the degree of freedom in selecting the elements used as MOSFETs 13 and 14, but also allows the operating conditions of both to be set close to the optimum.
Since the mutual conductance gm14 of MOSFET 14 in its operating state also increases in proportion to the increase in its drain current, the ratio gm14/gm13 of the mutual conductance of MOSFETs 3 and 14, which determines the voltage gain of this output buffer circuit, is
It is possible to make it much larger than gm4/gm3 in the conventional example shown in the figure.

It goes without saying that the same effect can be obtained even if the MOSFETs 12 and 21 in FIG. 2 are replaced with other elements that function as load elements.

As described above, according to the present invention, it is possible to obtain an output buffer circuit having a much larger voltage gain while having an output resistance comparable to that of the conventional circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing a conventional example, and FIG. 2 is a circuit configuration diagram of an embodiment of the present invention. In the figure, 1, 2, 3, 4, 11, 12, 1
3, 14, 20, 21...MOSFET, 5, 15
...Input terminal, 6,16...Output terminal, 7,17
... Connection point, 8, 9, 18, 19, 22 ... Voltage source.

Claims (1)

[Claims] 1 A first load element having one end connected to a first power source, and a first insulated gate electric field having a drain electrode connected to the other end of the first load element and a source electrode connected to a second power source. effect transistor (hereinafter
(abbreviated as MOS FET), the drain electrode is connected to the first power supply, and the gate electrode is connected to the first power supply.
a second MOSFET connected to the drain electrode of the MOSFET and a source electrode connected to the gate electrode of the first MOSFET;
a third MOSFET whose drain electrode is connected to the source electrode of the MOSFET and whose gate electrode is connected to the third power supply; and a fourth MOSFET whose drain electrode is connected to the source electrode of the third MOSFET and whose source electrode is connected to the second power supply.
MOSFET, and a second load element having one end connected to the first power supply and the other end connected to the drain electrode of the fourth MOSFET,
The gate electrode of the MOSFET is used as the input terminal and the first
An output buffer circuit characterized by using the drain electrode of a MOSFET as an output terminal.