IE902894A1 - Integrable differential amplifier - Google Patents

Abstract

An integratable differential amplifier consists of a first and of a second amplifier branch having in each case one CMOS inverter which is connected in series between two current source field-effect transistors (Q11, Q12 and, respectively, Q21, Q22). The gate electrodes (G) of the current source field-effect transistors are connected to one another and are connected to the centre tap of the CMOS inverter arranged in the first amplifier branch. An extremely low common-mode gain of the differential amplifier can be achieved by dimensioning the transistors used.

Description

Siemens Aktiengesellschaft Integrable differential amplifier The invention relates to an integrable differen5 tial amplifier in accordance with the preamble of Patent Claim 1.

As one of the intrinsically most important basic transistor circuits, the differential amplifier is encountered in the most varied embodiments, both in analog and in digital technology. Differential amplifiers can be implemented using bipolar or using field effect transistors, the latter being better suited for highly integrated circuits by reason of a simpler integrability.

A differential amplifier consists in principle of two symmetrically constructed direct voltage amplifiers, which are supplied from a common constant current source. In many circuit variants, the constant current source is replaced by a so-called current mirror of two gate20 coupled or base-coupled transistors.

Basic knowledge on differential amplifiers and current mirror circuits can be gained from the relevant specialist literature, e.g. Halbleiterschaltungstechnik (Semiconductor circuit engineering), U. Tietze, CH.

Schenk, 9th edition, Springer Verlag 1989.

Deviating from an ideal differential amplifier, which merely amplifies the difference of two input voltages, the differential amplifiers that can be implemented in practice have two amplifying components, that is to say the desired differential amplification and a so-called, common-mode gain, which is generally regarded as undesired. The common-mode gain is to be seen in that the output voltage of the differential amplifier varies when the two input voltages are varied in like fashion by one and the same voltage value.

It is the object of the present invention to develop a differential amplifier according'to the preamble of Patent Claim 1 in such a way that by dimensioning the transistors employed an extremely low common-mode gain can be achieved.

This object is achieved according to the invention by means of the features specified in the charac5 terizing part of Patent Claim 1.

The invention is based upon the realisation that because of the dependence of the drain-source voltage upon current, the current mirror that is employed in known differential amplifiers and consists of two gate10 coupled field effect transistors does not have an ideal response, with the result that the gains of the two amplifier inputs, referred to the differential amplifier output, deviate from one another.

An essential advantage of a differential amplif15 ier constructed according to the invention consists in that the circuit design offers so many degrees of freedom for dimensioning the transistors that the gains of the two amplifier inputs can be matched, without there being any displacement in the other operating points, such as the switching thresholds, for example.

Advantageous developments of the invention follow from the subclaims.

The differential amplifier is advantageously symmetrically constructed using further current source transistors, as a result of which two polarity variants, as in the case of known differential amplifiers, are no longer necessary.

Two illustrative embodiments of the invention are explained below in more detail with reference to the drawings, wherein FIG. 1 shows a known differential amplifier in two polarity variants; FIG. 2 shows a differential amplifier constructed according to the invention, with current source transis35 tors connected in series; and FIG. 3 shows a differential amplifier constructed according to the invention, with current source transistors connected in parallel.

FIG. 1 shows two circuit diagrams for the two polarity variants of the known differential amplifier. In both variants, the differential amplifier is composed of a first and a second amplifier branch, which consist, in each case, of a series connection of a current source transistor and a control transistor. The current source transistors are connected to one another at their gate electrodes G in order to form a current mirror. The current source transistor in the first amplifier branch is constructed with its drain electrode D, which has a connection to the gate electrodes, as a current mirror input. The drain electrode of the current source transistor in the second amplifier branch forms both the current mirror output and the differential amplifier output A.

In the first variant N of the differential amplifier (left hand circuit diagram), a current source transistor Qll, Q21, constructed as a P-channel MOS field effect transistor (abbreviated to P-channel MOSFET), is connected in series in each case in the two amplifier branches to a control transistor Sil, S21, constructed as an N-channel MOS field effect transistor (abbreviated to N-channel MOSFET). The current source transistors Qll, Q21 and the control transistors SI, S21 are in each case connected to one another at their drain electrodes D. At their source electrodes S, the current source transistors are connected to a voltage potential VCC (e.g. + 5 volt) and the control transistors are connected to a further voltage potential VEE (e.g. 0 volt), which is more negative than the voltage potential VCC.

The gate electrodes G of the control transistors Sil, S21 are constructed as differential amplifier inputs, the gate electrode G of the control transistor Sil located in the first amplifier branch being designated as positive differential amplifier input El, and the gate electrode of the control transistor S21 arranged in the second amplifier branch being designated as negative differential amplifier input E2.

The second variant P of the known differential amplifier (right-hand circuit diagram) differs from the first variant N only in that the control transistors Sll, S21 are constructed as P-channel MOSFETs and the current source transistors Qll, Q21 are constructed as N-channel MOSFETs, and are connected to the voltage potential VCC or the further voltage potential VEE.

FIG. 2 represents a circuit diagram of a differential amplifier constructed according to the invention, in which the amplifier branches each have a CMOS inverter consisting of control transistors Sll, S12; S21, S22, which is connected in series between two current source transistors Qll, Q12; Q21, Q22.

The CMOS inverter of every amplifier branch consists in each case of a control transistor Sll, S21, constructed as an N-channel MOSFET, and a further control transistor S12, S22, constructed as a P-channel MOSFET, which are connected to one another both via their drain electrodes D and via their gate electrodes G. The gate electrodes form a respective differential amplifier input El, E2, and the drain electrodes of the CMOS inverter arranged in the second amplifier branch form the differential amplifier output A.

In both amplifier branches, the further control transistor S12, S22 is connected with its source electrode S via the drain-source section of a current source transistor Qll, Q21, constructed as a P-channel MOSFET, to a voltage potential VCC (e.g. 5 volt), and the control transistor Sll, S21 is connected via a further current source transistor Q12, Q22, constructed as an N-channel MOSFET, to a further voltage potential VEE (e.g. 0 volt), which is more negative than the voltage potential VCC.

The gate electrodes of all current source transistors Qll, Q12, Q21, Q22 of the differential amplifier are connected to one another and to the drain terminals of the control transistors Sll, S12 located in the first amplifier branch, which drain terminals form a centre tap of the CMOS inverter.

Assuming a uniform transistor dimensioning, in which the current sources and control transistors of the first amplifier branch are constructed to be of the same size as the corresponding current sources or control transistors of the second amplifier branch, and in which the ratio between P-channel and N-channel MOSFETs is the same for all control and current source transistors, there would be a differential amplifier in which, as in the known differential amplifier, the gain from the positive amplifier input El to the amplifier output A is smaller in absolute terms than the gain from the negative amplifier input E2 to the amplifier output A. This difference in the gains, which forms as a result of the dependency of the drain-source voltages on current, represents the cause of the common-mode gain components of the known differential amplifier.

In the differential amplifier constructed accord15 ing to the invention, it is now possible for the two gains to be varied independently of one another and without influencing other operating points by dimensioning the transistors.

If, for example, the two current source transis20 tors Qll, Q12 are constructed in the first amplifier branch to be equally larger by a common factor, (i.e. the internal resistance thereby becomes smaller), there is an increase in the gain from the positive input El to the amplifier output A, without the gain from the negative input E2 to the amplifier output A thereby being influenced. The reason for this is that the driving component formed by the CMOS amplifier becomes larger by comparison with the feedback components in the first amplifier branch, which feedback components are formed by the current source transistors.

In general terms, it may be said that by preserving the ratio between P-channel and N-channel MOS field effect transistors, the gain of a particular amplifier input can be increased or decreased by varying the ratio between control and current source transistors in the pertinent amplifier branch.

FIG. 3 represents a circuit diagram for a differential amplifier constructed according to the invention having current source transistors connected in parallel to the control transistors forming a CMOS inverter.

The differential amplifier constructed according to the invention is likewise composed of a first and a second amplifier branch. In both amplifier branches, a control transistor Sil, S21, constructed as an N-channel MOSFET, and a further control transistor S12, S22, constructed as a P-channel MOSFET, are connected in each case to one another via their drain and gate electrodes D, G to form a CMOS inverter. The source electrode S of the control transistor Sil, S21 is connected to a further voltage potential VEE (e.g. 0 volt), and the source electrode S of the further control transistor S12, S22 is connected to a more positive voltage potential VCC (e.g. volt). Furthermore, in both amplifier branches a current source transistor Qll or Q21, constructed as a Pchannel MOSFET and a further current source transistor Q12 or Q22, constructed as an N-channel MOSFET, are connected to one another in each case via their drain and gate electrodes D, G, and connected with their source electrodes S to the voltage potential VCC or the further voltage potential VEE.

The gate electrodes of the control transistors S12, Sil of the first amplifier branch form the positive amplifier input El, and the gate electrodes of the control transistors S21, S22 of the second amplifier branch form the negative amplifier input E2.

All the current source transistors Qll, Q12, Q21, Q22 of the differential amplifier are connected to one another at their gate electrodes, and connected to the drain electrodes of the control transistors Sil, S12 and current source transistors Qll, Q12 arranged in the first amplifier branch. In the second amplifier branch, the drain electrodes of the control transistors S21, S22 and of the current source transistors Q21, Q22 are connected to one another and form the amplifier output A.

In this differential amplifier, κ as well, the gains of the amplifier inputs can be varied independently of one another. For this purpose, it is necessary to vary the ratio between the control and current source transistors for the amplifier branch appertaining to the particular amplifier input. However, in this process a reduction in the current source transistors leads to an increase in the gain appertaining to the amplifier input concerned.

Claims (5)

1. Patent Claims

1. Integrable differential amplifier with a first and a second amplifier branch, which in each case have a current source field effect transistor (Qll, Q21), connected with its drain-source section to a voltage potential (VCC), and a control field effect transistor (Sil, S21), constructed in a manner complementary to said current source field effect transistor, whose drainsource section serves to form a current path between the current source FET (Qll, Q21) and a further voltage potential (VEE), and whose gate electrode is constructed to form an amplifier input assigned to the particular amplifier branch, and with a centre tap provided in the current path between the current source FET (Qll, Q21) and control FET (Sil, S21), which in the first amplifier branch is connected to the gate electrodes of both current source FETs (Qll, Q21), and in the second amplifier branch is constructed as amplifier output (A), characterized in that the amplifier branches each have a further control FET (S12, S22), constructed in a manner complementary to the control FET (Sil, S21), which is connected with the control FET (Sil, S21) to a CMOS inverter forming the centre tap.

2. Integrable differential amplifier according to Claim 1, characterized in that the amplifier branches each have a further current source FET (Q12, Q22), constructed in a manner complementary to the current source FET (Qll, Q21), whose gate electrode is connected to that of the current source FET (Qll, Q21), and whose drain-source section is connected in series to that of the current source FET (Qll, Q21).

3. Differential amplifier according to Claim 2, characterized in that the CMOS inverter is connected via one of the current source FETs (Qll, Q12; Q21, Q22) in each case to the voltage potentials (VCC, VEE).

4. Differential amplifier according to Claim 2, characterized in that the drain-source sections of the current source FET (Qll, Q21) and of the further control FET (S12, S22) are connected in parallel, and in that the drain-source sections of the control FET (Sil, S21) and of the further current source FET (Q12, Q22) are connected in parallel and are connected to the further voltage potential (VEE).

5. An integrable differential amplifier according to any preceding claim substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.