JPS63211906A - Analog value inverter circuit - Google Patents
Analog value inverter circuitInfo
- Publication number
- JPS63211906A JPS63211906A JP62044705A JP4470587A JPS63211906A JP S63211906 A JPS63211906 A JP S63211906A JP 62044705 A JP62044705 A JP 62044705A JP 4470587 A JP4470587 A JP 4470587A JP S63211906 A JPS63211906 A JP S63211906A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- mosfet
- gate
- channel mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 230000003321 amplification Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
- H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＣＭＯ５−ＩＣをアナログ値処理する回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for processing analog values in a CMO5-IC.
従来ＣＭＯ８−ＩＣに於て、アナログ電圧値を反転増巾
する場合は、差動増巾を用いたオペアンプが使用されて
いた。第３図は従来のオペアンプ回路である。In the conventional CMO8-IC, when inverting and amplifying an analog voltage value, an operational amplifier using differential amplification has been used. FIG. 3 shows a conventional operational amplifier circuit.
６０１．５０４は電流制限用のトランジスタで、定電流
源として働＜、６ｏｉ、３０２，６０３，６０５゜６０
６で差動アンプを構成し、６０２，６０５と６０６゜６
０６はカレントミラーとなっている。601.504 is a current limiting transistor, which works as a constant current source.
6 constitutes a differential amplifier, 602, 605 and 606°6
06 is a current mirror.
入力は６０２と６０６のゲートに逆相になるよう配分し
て加えられる。差動アンプの出力は３０７のゲートに加
えられ、３０４と３０７でバッファアンプを構成してい
る。Inputs are distributed and applied to gates 602 and 606 so that they are in opposite phases. The output of the differential amplifier is applied to the gate of 307, and 304 and 307 constitute a buffer amplifier.
第４図に従来の単体のＭＯＳＦＥＴを示す。この出力特
性を第５図と第６図に示す。第５図は、ゲート電圧を一
定とした場合の１．、−Ｖ。、特性、第６図はＶＤ、を
一定とした場合の工。＠−Ｖ、＠特性である。FIG. 4 shows a conventional single MOSFET. This output characteristic is shown in FIGS. 5 and 6. FIG. 5 shows 1. when the gate voltage is constant. , -V. , characteristics, Figure 6 shows the characteristics when VD is constant. @-V, @characteristic.
第６図から明らかなように、ゲート電圧の増加にともな
い、ソース・ドレイ／電流は急げきに変化する。この単
体のトランジスタをコンプリメンタリに使用し、第１０
図に示すごとくインバータ回路を構成すると、その出力
は第１１図に示すごとく急げきに変化する。As is clear from FIG. 6, as the gate voltage increases, the source/drain/current changes rapidly. This single transistor is used complementary, and the 10th
When the inverter circuit is configured as shown in the figure, its output changes rapidly as shown in FIG.
しかしながら、例えばアクティブパネルを用いた液晶テ
レビのド°ライバーＩＣにおいて、前記オペアンプを各
出力に持たせると素子数が多いのでＩＣ内におけるオペ
アンプの面積率が大きくなるという欠点があった。However, for example, in a driver IC for a liquid crystal television using an active panel, if the operational amplifier is provided for each output, there is a drawback that the area ratio of the operational amplifier within the IC becomes large because the number of elements is large.
本発明の目的は、ＩＣ内におけるアナログ処理部の面積
を小さくし、さらには出力値の補正を含むアナログ処理
回路を提供するものである。An object of the present invention is to provide an analog processing circuit that reduces the area of an analog processing section within an IC and further includes correction of output values.
本発明の構成は、入力電圧がゲートに（われるＭＯＳＦ
ＥＴと、出力電圧がゲートにくわれるＭＯＳＦＥＴから
なり、出力が帰還されることにより、素子の１７ ＝ア
リティーを持たせることを特徴としている。The structure of the present invention is that the input voltage is applied to the gate of the MOSFET.
It consists of an ET and a MOSFET to which the output voltage is applied to the gate, and is characterized by having 17 = arity of the element by feeding back the output.
第７図は本発明のアナフグ値インバータ回路の片チャネ
ル側を示す。同様に特性を第８図と第９図に示す。第８
図は、ゲート電圧を一定とした場合のＩＤ、−■Ｄ、特
性、第９図はＶｏｇを一定とした場合のＩＤ、−■。、
特性である。第９図から明らかなように、ゲート電圧の
増加にともない、ソース・ドレイン電流はリニアに変化
する。FIG. 7 shows one channel side of the analog puff value inverter circuit of the present invention. Similarly, the characteristics are shown in FIGS. 8 and 9. 8th
The figure shows the ID, -■D, characteristics when the gate voltage is constant, and FIG. 9 shows the ID, -■ when the Vog is constant. ,
It is a characteristic. As is clear from FIG. 9, the source-drain current changes linearly as the gate voltage increases.
この回路をコンプリメンタリに使用したものが本発明の
構成となる。The configuration of the present invention is one in which these circuits are used complementaryly.
第１図は本発明のアナログインバータ回路の一実施例の
回路図である。第１図において１０１゜１０３はＰチャ
ネルＭＯ３ＦＥＴ、１０２゜１０４はＮチャネルＭＯＳ
ＦＥＴである。FIG. 1 is a circuit diagram of an embodiment of an analog inverter circuit according to the present invention. In Fig. 1, 101°103 is a P-channel MO3FET, and 102°104 is an N-channel MOS.
It is an FET.
入力電圧１０５は、１０１と１０２のゲートに加わり、
その出力１０６は１０６と１０４のゲートに加わること
によりフィードバックがかかりている。Input voltage 105 is applied to the gates of 101 and 102;
The output 106 is fed back by being applied to the gates 106 and 104.
上記本発明の回路の出力特性は第１２図に示すごとくリ
ニアとなる。The output characteristics of the circuit of the present invention are linear as shown in FIG.
以上の説明で明らかなように、本発明によればアナログ
電圧の入力に対し、ゲイン−１のアンプが容易に構成さ
れ、液晶ドライバーのような多ビン出力のＩＣに組み込
んだ場合、面積を小さくすることができる。As is clear from the above explanation, according to the present invention, an amplifier with a gain of -1 can be easily constructed for analog voltage input, and when incorporated into a multi-bin output IC such as a liquid crystal driver, the area can be reduced. can do.
さらに、帰還量を調整することにより■ゎ、）／２付近
において、ゲインを調整することが可能でありγ補正等
にも使用可能である。Furthermore, by adjusting the amount of feedback, it is possible to adjust the gain in the vicinity of ■ ゎ, )/2, and it can also be used for γ correction, etc.
又、本発明の回路構成は第２図に示す構成でもよい。Further, the circuit configuration of the present invention may be the configuration shown in FIG.
第１図、第２図は本発明の実施例の回路図、第３図は従
来の技術のオペアンプの回路図塾←÷。
第４図は従来の技術の単体のＭＯＳＦＥＴの回路図、第
５図、第６図は第４図に示した回路の特性を示す図、第
７図は本発明で用いた回路の片チャネル側の回路図で、
第８図、第９図はその特性を示す図、第１０図は従来の
インバーター回路の回路図、第１１図は第１０図のイン
バーター回路の出力特性を示す図、第１２図は本発明で
用いた回路の出力特性を示す図である。
１０１．１０６．６０１．６０２．６０６．６０４・・
・・・・ＰチャネルＭＯＳＦＥＴ。
１０２．１０４．６０５．６０６，６０７・・・・・・
ＮチャネルＭＯＳＦＥＴ。
特許出願人 シチズン時計株式会社
第１図
第４図
第５図
第６図
第７図
ドレイン（Ｄ）
第８図
第９図
第１ｏ図
第１１図Figures 1 and 2 are circuit diagrams of an embodiment of the present invention, and Figure 3 is a circuit diagram of a conventional operational amplifier. Figure 4 is a circuit diagram of a single MOSFET according to the prior art, Figures 5 and 6 are diagrams showing the characteristics of the circuit shown in Figure 4, and Figure 7 is one channel side of the circuit used in the present invention. In the circuit diagram of
8 and 9 are diagrams showing the characteristics thereof, FIG. 10 is a circuit diagram of a conventional inverter circuit, FIG. 11 is a diagram showing the output characteristics of the inverter circuit of FIG. FIG. 3 is a diagram showing the output characteristics of the circuit used. 101.106.601.602.606.604...
...P-channel MOSFET. 102.104.605.606,607...
N-channel MOSFET. Patent applicant Citizen Watch Co., Ltd. Figure 1 Figure 4 Figure 5 Figure 6 Figure 7 Drain (D) Figure 8 Figure 9 Figure 1o Figure 11
Claims (1)
於て、入力電圧がゲートにかかるＰチャネルＭＯＳＦＥ
ＴとＮチャネルＭＯＳＦＥＴと、回路の出力電圧がゲー
トに帰還されるＰチャネルＭＯＳＦＥＴとＮチャネルＭ
ＯＳＦＥＴを有することを特徴とするアナログ値インバ
ータ回路。(1) In an inverter circuit using MOS transistors, the input voltage is applied to the gate of P-channel MOSFE
T and N-channel MOSFETs, P-channel MOSFETs and N-channel M to which the output voltage of the circuit is fed back to the gate.
An analog value inverter circuit comprising an OSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62044705A JPS63211906A (en) | 1987-02-27 | 1987-02-27 | Analog value inverter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62044705A JPS63211906A (en) | 1987-02-27 | 1987-02-27 | Analog value inverter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63211906A true JPS63211906A (en) | 1988-09-05 |
Family
ID=12698834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62044705A Pending JPS63211906A (en) | 1987-02-27 | 1987-02-27 | Analog value inverter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63211906A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0412566A2 (en) * | 1989-08-10 | 1991-02-13 | Siemens Aktiengesellschaft | Integrable differential amplifier |
| US6175252B1 (en) | 1998-05-20 | 2001-01-16 | Nec Corporation | Driver circuit |
-
1987
- 1987-02-27 JP JP62044705A patent/JPS63211906A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0412566A2 (en) * | 1989-08-10 | 1991-02-13 | Siemens Aktiengesellschaft | Integrable differential amplifier |
| EP0412566A3 (en) * | 1989-08-10 | 1991-07-03 | Siemens Aktiengesellschaft | Integrable differential amplifier |
| US6175252B1 (en) | 1998-05-20 | 2001-01-16 | Nec Corporation | Driver circuit |
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