JPH0146950B2 - - Google Patents

Info

Publication number
JPH0146950B2
JPH0146950B2 JP55118988A JP11898880A JPH0146950B2 JP H0146950 B2 JPH0146950 B2 JP H0146950B2 JP 55118988 A JP55118988 A JP 55118988A JP 11898880 A JP11898880 A JP 11898880A JP H0146950 B2 JPH0146950 B2 JP H0146950B2
Authority
JP
Japan
Prior art keywords
bit line
potential
coupled
memory
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55118988A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5634188A (en
Inventor
Kei Tsuan Shiu
Jei Shimonseson Kaaru
Emu Horuto Uiriamu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JPS5634188A publication Critical patent/JPS5634188A/ja
Publication of JPH0146950B2 publication Critical patent/JPH0146950B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP11898880A 1979-08-27 1980-08-27 Mos random access memory Granted JPS5634188A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/070,132 US4247917A (en) 1979-08-27 1979-08-27 MOS Random-access memory

Publications (2)

Publication Number Publication Date
JPS5634188A JPS5634188A (en) 1981-04-06
JPH0146950B2 true JPH0146950B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-10-11

Family

ID=22093331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11898880A Granted JPS5634188A (en) 1979-08-27 1980-08-27 Mos random access memory

Country Status (3)

Country Link
US (1) US4247917A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5634188A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3030994A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1109655B (it) * 1978-06-28 1985-12-23 Cselt Centro Studi Lab Telecom Memoria di massa allo stato solido organizzata a bit autocorrettiva e riconfigurabile per un sistema di controllo a programma registrato
JPS56130885A (en) * 1980-03-18 1981-10-14 Fujitsu Ltd Address buffer circuit
DE3029108A1 (de) * 1980-07-31 1982-02-18 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierter halbleiterspeicher
US4503522A (en) * 1981-03-17 1985-03-05 Hitachi, Ltd. Dynamic type semiconductor monolithic memory
JPS5891594A (ja) * 1981-11-27 1983-05-31 Fujitsu Ltd ダイナミツク型半導体記憶装置
US4503344A (en) * 1982-04-09 1985-03-05 Honeywell Inc. Power up reset pulse generator
US4542483A (en) * 1983-12-02 1985-09-17 At&T Bell Laboratories Dual stage sense amplifier for dynamic random access memory
JPS61239493A (ja) * 1985-04-05 1986-10-24 Fujitsu Ltd 半導体記憶装置
JPS62197990A (ja) * 1986-02-25 1987-09-01 Mitsubishi Electric Corp 半導体記憶回路
US6496402B1 (en) * 2000-10-17 2002-12-17 Intel Corporation Noise suppression for open bit line DRAM architectures
US7513564B2 (en) 2003-07-01 2009-04-07 Honda Motor Co., Ltd. Skeleton structural member for transportation equipment
US8456946B2 (en) 2010-12-22 2013-06-04 Intel Corporation NAND logic word line selection

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4086662A (en) * 1975-11-07 1978-04-25 Hitachi, Ltd. Memory system with read/write control lines
US4038646A (en) * 1976-03-12 1977-07-26 Intel Corporation Dynamic mos ram
US4028557A (en) * 1976-05-21 1977-06-07 Bell Telephone Laboratories, Incorporated Dynamic sense-refresh detector amplifier
US4081701A (en) * 1976-06-01 1978-03-28 Texas Instruments Incorporated High speed sense amplifier for MOS random access memory
US4130897A (en) * 1977-08-03 1978-12-19 Sperry Rand Corporation MNOS FET memory retention characterization test circuit with enhanced sensitivity and power conservation
DE2739086C2 (de) * 1977-08-30 1986-01-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Betrieb eines dynamischen Halbleiter-Speicherelementes und Schaltungsanordnung zur Durchführung des Verfahrens
US4158241A (en) * 1978-06-15 1979-06-12 Fujitsu Limited Semiconductor memory device with a plurality of memory cells and a sense amplifier circuit thereof
US4198697A (en) * 1978-06-15 1980-04-15 Texas Instruments Incorporated Multiple dummy cell layout for MOS random access memory

Also Published As

Publication number Publication date
DE3030994A1 (de) 1981-03-19
DE3030994C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-09-28
US4247917A (en) 1981-01-27
JPS5634188A (en) 1981-04-06

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