JPH0144070B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention divides the screen of a screen into a plurality of sections vertically and horizontally, generates an electron beam for each section, and deflects it within each section. The present invention relates to an image display device that displays images.

Conventional configurations and their problems Traditionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes are extremely long and thin compared to the screen size. It was impossible to create a full-sized television receiver. In addition, EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements.
All of them are insufficient in terms of performance such as brightness, contrast, and color display, and have not yet been put into practical use.

Therefore, in order to achieve a flat display device using electron beams, the present applicant filed a patent application in 1983-
No. 20618 (Japanese Unexamined Patent Publication No. 57-135590) proposed a new display device.

This method generates an electron beam for each section when the screen is vertically divided into multiple sections, and displays multiple lines by deflecting each electron beam vertically for each section. Furthermore, it is divided into a plurality of sections in the horizontal direction, and the phosphors such as R, G, and B are sequentially emitted in each section, and the electron beams are directed to the phosphors such as R, G, and B. The overall television image is displayed by controlling the irradiation amount using color video signals.

However, in the conventional display devices mentioned above, even though the image display element itself can be made thinner, the processing circuit for controlling and driving it has an analog circuit configuration, making it difficult to implement large-scale ICs. Therefore, there was a problem in that the processing circuit portion became large and the entire display device could not be made thinner or smaller.

Purpose of the Invention In view of the above-mentioned problems, the present invention makes it possible to easily integrate the processing circuit for controlling and driving the image display element as described above into an IC, making it compact, and making the entire device thin. An object of the present invention is to provide an image display device that can be reduced in size and size.

Structure of the Invention The present invention is characterized in that a circuit for processing signals for controlling and driving an image display element is digitalized. That is, the video signal for display is A/D converted into a digital video signal, stored in an image memory for each pixel, and then read out from the image memory and pulse width modulated according to the content of the digital video signal. Convert it to a signal and apply it to the control electrode. On the other hand, for the deflection signal for deflecting the electron beam in the vertical and horizontal directions, the deflection waveform is A/D converted and stored in the deflection memory in advance as a digital deflection signal, and the horizontal and vertical synchronization of the television signal is The signals are read out from the deflection memory in synchronization, converted into D/A, and applied to the deflection electrodes. Both the video signal processing circuit and the deflection signal processing circuit are controlled by timing pulses synchronized with the horizontal and vertical synchronization signals and color subcarriers extracted from the television signal. Both circuits are operated in a synchronized state.

By doing this, the processing circuit for controlling and driving the image display element can be almost completely digitalized, and it can easily be made into a large-scale IC and can be made compact, allowing for thin image display. Together with the element, a thin and small image display device can be realized.

DESCRIPTION OF EMBODIMENTS Hereinafter, a first explanation will be given of a control and drive processing circuit used in an image display device according to an embodiment of the present invention.
This will be explained in detail with reference to FIGS.

First, a basic configuration example of the image display element used here will be explained with reference to FIG.

This display element is arranged in order from the back to the front.
A back electrode 1, a line cathode 2 as a beam source, vertical focusing electrodes 3, 3', a vertical deflection electrode 4, a beam flow control electrode 5, a horizontal focusing electrode 6, a horizontal deflection electrode 7, a beam accelerating electrode 8 and a screen plate 9. and are housed within the evacuated interior of a flat glass bulb (not shown).

A line cathode 2 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of line cathodes 2 (here, 2-2-4
(Only books shown) provided. In this embodiment, it is assumed that 15 pieces are provided. 2 of them
Let's say I~2yo. These line cathodes 2 are, for example, 10
It consists of an oxide cathode material for thermionic emission coated on the surface of a tungsten wire with a diameter of ~20 μφ.
These line cathodes 2A to 2Y are heated so as to generate a thermionic electron beam by passing an electric current through them, and as will be described later, the electron beams are emitted from the upper line cathode 2A for a certain period of time. controlled to emit. The back electrode 1 suppresses generation of electron beams from line cathodes 2 other than the line cathode 2 controlled to emit the constant electron beam, and directs the generated electron beams only in the forward direction. It has the effect of pushing out. The back electrode 1 may be formed by a coating of a thin electrical material applied to the inner surface of the rear wall of the glass bulb. Further, instead of the back electrode 1 and the line cathode 2, a planar electron beam emitting electrode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 10 facing each of the line cathodes 2I to 2Y, and extracts the electron beam emitted from the line cathode 2 through the slit 10, and directs the electron beam in the vertical direction. focus on. An electron beam for one horizontal line (360 pixels) is extracted at the same time.

In the figure, only one section in the horizontal direction is shown. The slit 10 may be provided with crosspieces at appropriate intervals in the middle, or with small intervals in the horizontal direction (intervals that are almost touching).
The through hole may be substantially configured as a slit by a row of a large number of through holes arranged side by side. The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally in the middle of each of the slits 10, and are each composed of conductors 13 and 13' provided on the upper and lower surfaces of an insulating substrate 12. has been done. And the opposing conductors 13, 13'
A vertical deflection voltage is applied between them to deflect the electron beam in the vertical direction. In this embodiment, the electron beam from one line cathode 2 is vertically deflected to a position corresponding to 16 lines by a pair of conductors 13, 13'. The 16 vertical deflection electrodes 4 constitute 15 pairs of conductors corresponding to each of the 15 line cathodes 2, and in the end, the electron beams are drawn so as to draw 240 horizontal lines on the screen 9. to deflect.

Next, the control electrodes 5 are composed of conductive plates 15 each having a vertically long slit 14, and a plurality of control electrodes 15 are arranged in parallel in the horizontal direction at predetermined intervals. In this embodiment, 180 conductive plates 15a-15n for control electrodes are provided. (9 in the diagram)
(only books shown). Each of the control electrodes 5 separates and extracts the electron beam by two picture elements in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, the conductive plates 15a to 15n for the control electrode 5 are
With this arrangement, 360 pixels can be displayed per horizontal line. In addition, in order to display images in color, each picture element is displayed using phosphors of three colors, R, G, and B, and each control electrode 5 has two picture elements of R, G, and B. Each video signal is applied sequentially.

In addition, 180 conductive plates 15a to 1 for control electrodes 5
5n, 180 sets of video signals for one line (2 picture elements per set) are simultaneously applied, and the video for one line is displayed at one time.

The horizontal focusing electrode 6 is composed of a conductive plate 17 having a plurality of vertically long slits 16 (180 slits 16) facing the slits 14 of the control electrode 5, and collects electrons for each picture element divided in the horizontal direction. Each beam is focused horizontally into a narrow electron beam.

The horizontal deflection electrode 7 is made up of a plurality of conductive plates 18, 18' arranged vertically on both sides of the slit 16, and each electrode 18, 18' has six levels of horizontal deflection. A voltage is applied to horizontally deflect the electron beam for each pixel, and on the screen 9 two sets of R,
The G and B phosphors are sequentially irradiated to emit light. In this embodiment, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode 8 is composed of a plurality of conductive plates 19 provided horizontally at the same position as the vertical deflection electrode 4, and accelerates the electron beam so that it collides with the screen 9 with sufficient energy.

The screen 9 is constructed by coating the back surface of a glass plate 21 with a phosphor 20 that emits light when irradiated with an electron beam, and adding a metal back layer (not shown). The phosphor 20 is arranged for each slit 14 of the control electrode 5, that is, for each horizontally divided electron beam.
Two pairs of phosphors in each of the three colors R, G, and B are provided, and are applied in stripes in the vertical direction. In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view in Fig. 2, one section partitioned by these two has R, G, and B phosphors 20 for two pixels in the horizontal direction, and 16 lines in the vertical direction. It has a width of
For example, the size of one section is 1 in the horizontal direction.
mm, and the vertical direction is 10 mm.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

Further, in this embodiment, only two pairs of two picture elements are provided with R, G, and B phosphors 20 for one control electrode 5, that is, one electron beam, but of course, one picture element or two pairs of two picture elements are provided. Three or more picture elements may be provided, and in that case, R, G, and B video signals for one picture element or three or more picture elements are sequentially applied to the control electrode 5, and horizontal deflection is performed in synchronization with this. Ru.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen 9 with an electron beam to emit raster light will be described.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element,
-V ₁ to the back electrode 1, and -V 1 to the vertical focusing electrodes 3 and 3'.
DC voltages of V ₃ , V ₃ ', V ₆ to the horizontal focusing electrode 6, V ₈ to the accelerating electrode 8, and V ₉ to the screen 9 are applied.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and displays a vertical synchronization signal V and a horizontal synchronization signal H.

The vertical deflection drive circuit 40 includes a vertical deflection counter 25, a memory 27 for storing vertical deflection signals, and a digital-to-analog converter 39 (hereinafter referred to as a DA converter). Vertical deflection drive circuit 4
As the zero input pulse, the vertical synchronizing signal V and horizontal synchronizing signal H shown in FIG. 4 are used. The vertical deflection counter 25 (8 bits) is reset by the vertical synchronizing signal V and counts the horizontal synchronizing signal H. This vertical deflection counter 25 counts an effective scanning period (here, a period of 240H) excluding the vertical retrace period in the vertical period, and this count output is supplied to the address of the memory 27. The memory 27 outputs vertical deflection signal data (here, 8 bits) corresponding to each address, and is converted by the DA converter 39 into vertical deflection signals v and v' shown in FIG. This circuit has a memory address that stores vertical deflection signals corresponding to each line for 240H, and by storing regular data in the memory every 16H.
A 16-step vertical deflection signal can be obtained.

On the other hand, the line cathode drive circuit 26 receives the vertical synchronization signal V
Using the output of the vertical deflection counter 25, line cathode drive pulses I to Y are created. FIG. 5a shows the relationship between the vertical synchronizing signal V, the horizontal synchronizing signal H, and the lower five bits of the vertical deflection counter 25. FIG. 5b shows a method of creating line cathode drive pulses 1' to 16' every 16H using these signals. In Figure 5,
LSB indicates the lowest bit, and (LSB+1) means the bit one higher than the LSB.

The first line cathode drive pulse I' consists of the vertical synchronizing signal V and the output of the vertical deflection counter 25 (LSB+
4) can be created using an R-S flip-flop, etc., and the line cathode drive pulses LO' to YO' can be created using a shift register, and the line cathode drive pulses LO' to YO' are output from the vertical deflection counter 25 (LSB+2).
It can be obtained by using the inverted version of the clock as a clock and transmitting it. These drive pulses I'~Yo' are inverted and made low potential only during each pulse period, and converted into line cathode drive pulses I~Yo that are at a high potential of about 20 volts during other periods, and each line cathode 2 I~
Added to 2yo.

Each line cathode 2i to 2yo is heated by a current flowing through it during the high potential period of the drive pulses I to YO, and the heated state is maintained so that electrons can be emitted during the low potential period of the drive pulses I to YO. Ru. As a result, electrons are emitted from the 15 line cathodes 2i to 2yo only during the 16H period when low potential drive pulses are applied to each of them. During the period when a high potential is applied,
Looking at the potential at the position of the line cathode 2 determined by the bias voltages applied to the back electrode 1 and the vertical focusing electrode 3, the high potential applied to the line cathodes 2I to 2Y is more positive. Therefore, no electrons are emitted from the line cathodes 2i to 2yo. Thus, in the line cathode 2, electrons are sequentially emitted from the upper line cathode 2a toward the lower line cathode 2y every 16H period during the effective vertical scanning period.

The emitted electrons are pushed forward by the back electrode 1, pass through the opposing slits 10 of the vertical focusing electrode 3, and are focused in the vertical direction to form a flat electron beam.

Next, the relationship between the line cathode drive pulses y to y and the vertical deflection signals v and v' will be explained using FIG. 6. The vertical deflection signals v and v' change by 1H during the 16H period of each line cathode pulse y to y, and change in 16 steps. The vertical deflection signals v and v' both have a center voltage of _V4 , and are configured to change in opposite directions so that v increases sequentially and v' decreases sequentially. These vertical deflection signals v and v' are applied to electrodes 13 and 13' of the vertical deflection electrode 4, respectively, and as a result, the electron beams generated from the respective line cathodes 2a to 2o are deflected in 16 steps in the vertical direction. As mentioned above, on the screen 9, one electron beam is deflected so as to sequentially draw a raster line of 16 lines one line at a time from the top.

As a result of the above, an electron beam is emitted for a period of 16 hours from the top of the 15 line cathodes 2I to 2Y, and each electron beam is sequentially emitted for one line from the top to the bottom within 15 sections in the vertical direction. As a result, the electron beam is vertically deflected one line at a time on the screen 9 from the first line at the upper end to the 240th line at the F end, thereby drawing a raster of 240 lines in total.

The electron beam thus vertically deflected is horizontally deflected by 180 degrees by the control electrode 5 and the horizontal focusing electrode 6.
It is divided into sections and taken out. Figure 1 shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 5, and horizontally focused by a horizontal focusing electrode 6 into a single narrow electron beam, which is then controlled by horizontal deflection means described below. The light is then deflected in six steps in the horizontal direction and is sequentially irradiated onto each of the R, G, and B phosphors 20 corresponding to two picture elements on the screen 9. FIG. 2 shows the vertical and horizontal divisions. The phosphors corresponding to each of 15a to 15n of the control electrode 5 are R, G, and B for two picture elements, but for convenience of explanation, one picture element is
Let R ₁ , G ₁ , B ₁ be R ₂ , G ₂ , B ₂ .

Next, the horizontal deflection drive circuit 41 is composed of a horizontal deflection counter (11 bits), a memory 28 storing horizontal deflection signals, and a DA converter 38. As shown in FIG. 7, the input pulses of the horizontal deflection drive circuit 41 are synchronized with the vertical synchronizing signal V and the horizontal synchronizing signal H, and a pulse 6H having a repetition frequency six times that of the horizontal synchronizing signal H is used.

The horizontal deflection counter 28 is reset by the vertical synchronizing signal V and counts the horizontal six times pulse 6H. This horizontal deflection counter 28 is
6 times during 1H, 260H x 6/H = 1440 during 1V
The count output is supplied to an address in the memory 29. From the memory 29, horizontal deflection signal data according to the address (in this case, 8
bit) is output, and the DA converter 38 outputs the seventh
It is converted into horizontal deflection signals such as h and h' shown in the figure. This circuit has memory addresses for storing horizontal deflection signals corresponding to each of 6 x 240 lines, and by storing 6 pieces of regular data for each line in the memory, 6 step waves are generated in 1H period. horizontal deflection signals can be obtained.

This horizontal deflection signal is a pair of horizontal deflection signals h and h' that change in 6 steps as shown in FIG. 7, both have a center voltage of V ₇ , and h gradually decreases.
h' increases in sequence and changes in opposite directions. These horizontal deflection signals h, h' are applied to electrodes 18 and 18' of the horizontal deflection electrode 7, respectively.
As a result, each of the horizontally divided electron beams is transmitted to the R, G, B of the screen 9 during each horizontal period.
It is horizontally deflected so that R, G, and B (R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ ) phosphors are sequentially irradiated with H/6 each. Thus, in the raster of each line, the electron beam is horizontally divided into R ₁ , G ₁ ,
The phosphors 20 of B ₁ , R ₂ , G ₂ , and B ₂ are sequentially irradiated.

Therefore, an electron beam is applied to each horizontal section of each line.
A color television image can be displayed on the screen 9 by modulating the video signals R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ .

Next, the modulation control portion of the electron beam will be explained.

First, the composite video signal applied to the television signal input terminal 23 is applied to the color demodulation circuit 30,
Here, the color difference signals of R-Y and B-Y are demodulated,
Furthermore, they are combined with the luminance signal Y, R,
G and B primary color signals (hereinafter referred to as R, G, and B video signals) are output. These R, G, B video signals are handled by 180 sample and hold circuit sets 31
Added to a to 31n. Each sample and hold circuit set 31a to 31n is for _R1 , _G1 , and _B1, respectively.
It has 6 sample and hold circuits: 1, R ₂ , G ₂ , and B ₂ . These sample and hold outputs are respectively applied to holding memory sets 32a-32n.

On the other hand, the reference clock oscillator 33 is constituted by a PLL (phase locked loop) circuit, etc., and in this embodiment generates a reference clock 6f _SC that is six times the color subcarrier f _SC and a reference clock 2f _SC that is twice the color subcarrier f SC. . The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H.
The reference clock 2f _SC is added to the deflection pulse generation circuit 42, and the signals 6H and H/
6 signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ are obtained. On the other hand, the reference clock 6f _SC is applied to the sampling pulse generation circuit 34, where it is delayed by one clock cycle by a shift register, so that the effective horizontal scanning period (approximately 50 μsec) of the horizontal period (63.5 μsec) is delayed. In the meantime, 1080 sampling pulses R _a1 to B _o2 are sequentially generated, and then one transfer pulse t is generated. This sampling pulse R _a1 - R _o2 is one of the images to be displayed.
It corresponds to each picture element when a line is divided into 360 picture elements in the horizontal direction, and its position is controlled so that it is always constant with respect to the horizontal synchronizing signal H.

These 1080 sampling pulses R _a1 to B _o2 are each connected to 180 sample and hold circuit sets 31a.
31n, and as a result, R ₁ , G ₁ , B ₁ , R for each two picture elements when one line is divided into 180 are added to each sample and hold circuit set 31a to 31n. ₂ , _G2 , and _B2 are individually sampled and held. The sample-held 180 pairs of R ₁ , G ₁ , B ₁ , R ₂ , G ₂ ,
After the sample and hold for one line is completed, the _B2 video signal is transferred all at once to 180 sets of memories 32a to 32n by a transfer pulse t, where it is held for the next horizontal period. This retained R ₁ , G ₁ ,
The signals of B ₁ , R ₂ , G ₂ , and B ₂ are sent to the switching circuit 35.
Added to a~35n. Switching circuit 35
a to 35n are R ₁ , G ₁ , B ₁ , R ₂ , G ₂ ,
It is composed of a tri-state or analog gate having _B2 individual input terminals and a common output terminal that sequentially switches and outputs them.

The output of each switching circuit 35a to 35n is
180 sets of pulse width modulation (PWM) circuits 37a to 3
7n, and here the reference pulse signal is pulse width modulated according to the magnitude of the sampled and pre-held R ₁ , G ₁ , B ₁ , G ₂ , B ₂ video signals and is output. It is desirable that the repetition period of the reference pulse signal is sufficiently smaller than the pulse width of the signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ ,
For example, a ratio of about 1:10 to 1:100 is used.

The output of the pulse width modulation circuits 37a to 37n is used as a control signal for modulating the electron beam to the 180 conductive plates 15a to 15 of the control electrode 5 of the display element.
n separately. Each of the switching circuits 35a to 35n receives a switching pulse r ₁ applied from the switching pulse generation circuit 36,
Switching is controlled simultaneously by g ₁ , b ₁ , r ₂ , g ₂ , and b ₂ . The switching pulse generation circuit 36 generates a signal switching pulse from the deflection pulse generation circuit 42 mentioned above.
controlled by r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ ,
Each horizontal period is divided into six, and the switching circuits 35a to 35n are switched by H/6, and R ₁ , G ₁ , B ₁ ,
Switching signals r _{1 ,} g _{1 ,} b ₁ , r ₂ , b _{2 ,} Generate g ₂ .

What should be noted here is that the switching circuit 3
R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ in 5a to 35n
video signal supply switching and water flake deflection drive circuit 4
The irradiation switching horizontal deflection of the electron beams R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ to the phosphor by 1 is synchronously controlled so that both the timing and the sequence coincide completely. It is that you are. As a result, when the electron beam is irradiating the R ₁ phosphor, the amount of the electron beam is controlled by the R ₁ video signal, and also for G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ . Similarly controlled, each picture element's R, G, B ₁ , R ₂ , G ₂ ,
B ₂ The emission of each phosphor is caused by the R ₁ , G ₁ , B ₁ ,
Each picture element is controlled by the R ₂ , G ₂ , and B ₂ video signals, and each picture element is displayed by emitting light according to the input video signal. Such control is performed simultaneously for 180 sets of one line (2 picture elements each) to display an image of 360 picture elements per line, and then sequentially for 240 lines starting from the upper line to display the image on the screen 9. One image will be displayed.

The above-mentioned all-digital operations are repeated for each field of the input television signal, and as a result, a moving television image is projected on the screen 9 in the same way as in a normal television receiver. .

As described above, television images are displayed on this display device. Note that pulse amplitude modulation may be performed instead of pulse width modulation.

Next, the specific configuration of the drive circuit is shown in FIG. 8, and each pulse timing is shown in FIGS. 9 and 10.

The reference clock oscillator 33 is a 6f _SC oscillator 43, 1/
It is composed of a PLL circuit consisting of a 6 frequency divider 44 and a phase comparator 45, and uses the color subcarrier f _SC (3.58 MHz) and the 6 f _SC clock, which is phase clocked, as a reference for all the clocks. This 6f _SC clock is input to the 1/3 frequency divider 46 of the sampling pulse generation circuit 34, and the 2f _SC clock
Generates video signal sampling clock _RCK .
_RCK is further input to a 2-clock delay device 47 whose clock is clock 6f _SC to generate a G video signal sampling clock _GCK , which is further input to a 2-clock delay _device 48 to generate a B video signal. Generates signal sampling clock _BCK . That is, R _CK ,
G _CK and B _CK all have a frequency of 2f _SC , and constitute a three-phase clock in which G _{CK and R CK are} delayed in phase by 120 degrees with respect to G _CK , respectively.

Next, the analog R, G, and B video signals are sent to the three A for sample and hold circuits 31a to 31n.
- input to D converters 49R, 49G, and 49B, respectively. In this example, each A-
Assume that D conversion is performed. A-D converter 49R,
The clocks of 49G and 49B are as described above.
_RCK , _GCK , _BCK . As a result, the analog
The RGB video signal is sampled at a frequency of 2f _SC and converted to a digital signal, and its phase is
R, G, and B are sampled in the order of 120 degrees apart. This digital video signal is input to hold latches 50R, 50G, and 50B.
This latch can, for example, be 8 bits x 360 each.
It can be configured with stage shift registers. As clocks at this time, the aforementioned R _CK , G _CK , and B _CK are each synthesized with a blanking pulse and used. That is, this is a gated clock for only the effective video signal period of one horizontal period, and corresponds to the aforementioned sampling pulses Ra ₁ to Bn ₂ . By sampling 360 picture elements each for R, G, and B, it is possible to configure a sample-and-hold circuit for 1H.

These R, G, and D digital video signals are each divided into 180 sets of processing circuits 51a...5 each consisting of two picture elements.
1i...Input to 51n. This processing circuit 51a~
51n are memory sets 32a to 32n, switching circuits 35a to 35n, and PWM circuits 37a to 37.
Contains n. Each of the memory groups 32d to 32n is composed of six sets of 8-bit memories _Ri1 to _Bi2 , and each of the switching circuits 35a to 35n is composed of six tristate buffers Ri1 to Bi2, and each of the switching circuits 35a to 35n is composed of six tristate buffers _Ri1 to _Bi2 , Each of the circuits 37a to 37n includes an 8-bit presettable counter 52, an R-S flip-flop 53, and an output driver 54. First, the 8-bit memories Ri ₁ to Bi ₂ are connected to the aforementioned 1H latch 50R.
A digital video signal is input from 50B. These memories Ri ₁ to Bi ₂ may be simple data latches. The data latch pulse is a pulse triggered by a horizontal synchronizing signal, and its generating means will be described later. Next, the 8-bit outputs of the memories Ri ₁ -Bi ₂ are respectively input to the trisler buffers Ri ₁ -Bi ₂ , gated by six-phase switching pulses r ₁ -b _2, and output. The phase is shown in FIG. The output is input as preset data to an 8-bit presettable counter 52. This counter 52 is preset by a data load pulse, and its clock is an up counter with 2f _SC , and its carry output is used as the set input of the R-S flip-flop 53. The reset input of this R-S flip-flop 53 has six pulses during one horizontal period, and its phase is fixed. In other words, this R/S flip-flop 53 and counter 5
2 constitutes a pulse width modulation circuit corresponding to an 8-bit digital video signal. The output waveform contains six pieces of information during one horizontal period, that is,
Ri ₁ , Gi ₁ , Bi ₁ , Ri ₂ , Gi ₂ , and Bi ₂ are output in sequence.
This is applied via the driver 54 to the control electrodes 15a to 15n of the image display element.

Next, each pulse generating means will be explained.

The deflection pulse generation circuit 42 inputs the clock _RCK of the 2f _SC frequency described above and resets the horizontal synchronization signal with an output shaped by the waveform shaping circuit 55.
It consists of a bit counter 56, a demultiplexer 57 which receives its 9-bit output as input, and a pulse generating R-S flip-flop group 58. From the relationship 2f _SC = 455f _H , this counter 56
Therefore, any horizontal phase is uniquely determined as 9-bit data. Demultiplexer 5
7 and using the R-S flip-flop group 58, it is possible to generate switching pulses r ₁ to b _{2 and} the like having the above-mentioned pulse widths at a predetermined phase of the horizontal period width. Furthermore, by using gates such as the DR gate 59, multiphase pulses can be freely configured.

Next, the vertical and horizontal deflection circuits 40 and 41 will be explained. These include deflection address counters 25 and 28, deflection data memories 27 and 29,
D-A converters 39, 38 and drivers 60, 6
The configuration consists of 1. Horizontal deflection counter 28
is a 4-bit counter which uses the horizontal pulse H as the reset pulse, the 6H pulse from the OR gate 59 as the clock, and the vertical pulse V as the reset pulse. The number of bits in the memories 27 and 29 for each deflection data may be determined depending on the resolution, and may be realized with about 8 bits, for example. Its data content can be independently and freely controlled by the microprocessor 62. The deflection data read out at a predetermined timing is generated as a staircase wave deflection voltage in the D-A converters 39 and 38, and the deflection data is generated as a staircase wave deflection voltage in the DA converters 39 and 38.
1 through the vertical deflection electrode 13,1 of the image display element.
3' and horizontal deflection electrodes 18, 18'.

Finally, the line cathode drive circuit 26 will be explained. In this case, a 4-bit counter 63 using the horizontal pulse H as a clock and the vertical pulse as a reset pulse outputs a 16H cycle pulse as a carry output, and the 4-bit output of a 4-bit counter 64 using this as a clock is sent to a demultiplexer 65.
Input to obtain 15 phase drive pulses. This is connected to the line cathode 2 of the image display element via the driver 66.
The counters 63 and 64 that supply signals A to 2Y may be omitted and the output of the vertical deflection counter 25 may be used.

Effects of the Invention As described above, according to the present invention, the entire system can be digitalized, high-density integrated circuit elements indispensable for flat image display devices can be realized, and the device as a whole can be extremely thin. It can be made small in size.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view of an image display element used in an image display device according to an embodiment of the present invention, and FIG.
The figure is an enlarged view of the phosphor screen of the image display element, Figure 3 is a block diagram of the drive circuit for driving the image display element, and Figures 4, 5, 6, and 7 are the same. Waveform diagrams of various parts to explain the operation of the drive shaft circuit, Figure 8 is a detailed block diagram of the drive circuit of the image display device, and Figures 9 and 10 are waveform diagrams to explain the operation of the device. It is a diagram. 2, 2 I to 2 Y... Line cathode, 4... Vertical deflection electrode, 5... Beam flow control electrode, 7... Horizontal deflection electrode, 9... Screen plate, 10... Slit, 1
4... Slit, 15, 15a to 15n... Conductive plate, 18, 18'... Conductive plate, 20... Phosphor,
23...Input terminal, 24...Synchronization separation circuit, 25
... Vertical deflection counter, 26 ... Line cathode drive circuit, 27 ... Memory, 28 ... Horizontal deflection counter, 29 ... Memory, 30 ... Color demodulation circuit,
31a to 31n...sample hold circuit, 32
a to 32n...Memory, 33...Reference clock oscillator, 34...Sampling pulse generation circuit, 3
5a to 35n... Switching circuit, 36... Switching pulse generation circuit, 37a to 37n...
PWM circuit, 38...D/A conversion circuit, 39...
D/A conversion circuit, 40...Vertical deflection drive circuit, 4
1... Horizontal deflection drive circuit, 42... Deflection pulse generation circuit, 43... Deflection pulse generation circuit.

Claims (1)

[Claims] 1. A screen coated with a phosphor that emits light when irradiated with an electron beam, an electron beam source that generates an electron beam for each vertical section of the screen divided vertically into a plurality of sections, and the above-mentioned a horizontal separating means for separating the electron beam generated by the electron beam source into each of the plurality of horizontal divisions of the screen on the screen and irradiating the electron beam onto the screen; An electrostatic deflection electrode that deflects the electron beam in multiple steps vertically and horizontally between It is equipped with an image display element having a control electrode that controls the emission intensity of each picture element, and an A/D converter that converts a video signal for image display into a digital video signal.
a D conversion circuit, an image memory for storing the digital video signal for each pixel, and reading out the digital video signal for each pixel from the image memory and converting it into a pulse width modulation signal or a pulse amplitude modulation signal. and a digital control means for applying the voltage to the control electrode of the image display element, and storing a digital deflection signal obtained by A/D converting a vertical deflection signal and a horizontal deflection signal for deflecting the electron beam in the vertical and horizontal directions. deflection memory,
a digital deflection means that sequentially reads out the digital deflection signal from the deflection memory in synchronization with a vertical synchronization signal and a horizontal synchronization signal, converts it from D/A, and applies it to the deflection electrode; and the image memory;
a timing pulse generation circuit that generates timing pulses synchronized with a vertical synchronization signal, a horizontal synchronization signal, and a color subcarrier and supplies them to each of the above circuits so as to operate the digital control means, the deflection memory, and the digital deflection means in synchronization with each other; An image display device comprising: