JPH0143872Y2 - - Google Patents

Info

Publication number
JPH0143872Y2
JPH0143872Y2 JP13931183U JP13931183U JPH0143872Y2 JP H0143872 Y2 JPH0143872 Y2 JP H0143872Y2 JP 13931183 U JP13931183 U JP 13931183U JP 13931183 U JP13931183 U JP 13931183U JP H0143872 Y2 JPH0143872 Y2 JP H0143872Y2
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor chip
external lead
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13931183U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6048252U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1983139311U priority Critical patent/JPS6048252U/ja
Publication of JPS6048252U publication Critical patent/JPS6048252U/ja
Application granted granted Critical
Publication of JPH0143872Y2 publication Critical patent/JPH0143872Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1983139311U 1983-09-08 1983-09-08 リ−ドフレ−ム Granted JPS6048252U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983139311U JPS6048252U (ja) 1983-09-08 1983-09-08 リ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983139311U JPS6048252U (ja) 1983-09-08 1983-09-08 リ−ドフレ−ム

Publications (2)

Publication Number Publication Date
JPS6048252U JPS6048252U (ja) 1985-04-04
JPH0143872Y2 true JPH0143872Y2 (US07943777-20110517-C00090.png) 1989-12-19

Family

ID=30312289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983139311U Granted JPS6048252U (ja) 1983-09-08 1983-09-08 リ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPS6048252U (US07943777-20110517-C00090.png)

Also Published As

Publication number Publication date
JPS6048252U (ja) 1985-04-04

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