JPH0143508B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation circuit, and is particularly suitable for use in a thermal head drive circuit of a thermal telephone facsimile device.

A method of adding gradation to an image transmitted by a thermal telephone facsimile device is known. As the transmission signal, a so-called pulse amplitude modulation signal is used, in which pixel signals of "1" and "0" sent serially for each line of the image are amplitude-modulated according to the gradation. . PCM signals are also being considered as another transmission method. In order to receive such a transmission signal and form a multi-tone image using a thermal head,
A commonly used method is to control the voltage level or amount of current applied to a thermal head in accordance with input information to adjust the amount of heat in the thermal head.

FIG. 1 is a block diagram of such a conventional system. When a pulse amplitude modulation signal as described above is used as an input signal, this input signal is converted into a digital signal in the A/D converter 1 and stored in the memory 2. From the memory 2, one line of the image or a signal obtained by dividing one line into several blocks is read out simultaneously (parallel), converted to a voltage level by the D/A converter 3, and then supplied to each thermal head. . Therefore, D/A converters 3 are required for each head, and the total number of D/A converters 3 is equal to the number of pixels in one line or the number of pixels divided into several blocks.

In addition, as the D/A converter 3, a current addition type simple D/A converter using a weighted resistance circuit, a D/A converter combining a ladder resistance circuit and an OR amplifier, a sequential comparison type D/A converter, etc. A D/A converter or the like is used. The one that uses a weighted resistor circuit has the disadvantage that the gradation of each pixel varies due to variations in resistance, and the one that uses a ladder resistor circuit has the disadvantage that it is necessary to adjust the gain of each operational amplifier. is extremely complicated. Furthermore, an IC-based D/A converter is expensive.

Therefore, it has been proposed to digitize the pixel forming circuit for multi-gradation images (for example, Japanese Patent Laid-Open No. 54
−105912). This published specification states that input gradation image data and the output of a counter that counts the reference clock are compared in a comparison circuit, and a pulse density signal corresponding to the gradation is obtained based on the matching output. has been done.

According to such a configuration, it is possible to control the thermal head etc. using only digital binary information and obtain a gradated image, but when a large number of resistance elements of the thermal head are arranged in parallel, In this case, the number of comparison circuits equal to the number of elements is required, and the circuit configuration becomes extremely complicated.

In view of this problem, the present invention greatly simplifies the circuit configuration, and basically creates a gradation printing pulse forming circuit for a single element even when a large number of printing head elements are provided in parallel. It is an object of the present invention to use this method to simultaneously supply gradation printing pulses to a large number of elements in parallel.

The pulse width modulation circuit of the present invention includes a memory RAM 1 that stores a plurality of gradation data to be pulse width modulated.
1, a first counter 7 that sequentially generates reference gradation data from the minimum reference gradation to the maximum reference gradation according to the first clock pulse CP, and a second counter 7 having a frequency sufficiently higher than that of the first clock pulse. a second counter 12 which is driven by a clock pulse CK of 1 and generates an address signal for the plurality of gradation data; one gradation of the reference gradation data generated by the first counter 7; a comparator C that sequentially generates a comparison output by comparing all of the plurality of gradation data read out from the memory 11 according to the address signal from the counter 12 of the above, and repeats this for each reference gradation; a latch circuit 14 having an address corresponding to the plurality of gradation data, receives the comparison output of the comparator, sequentially inputs it into the corresponding address, and obtains pulse width modulation output corresponding to the plurality of gradation data in parallel from the corresponding address; Equipped with.

According to this configuration, one comparator C operates in a time-division manner and cooperates with the latch circuit to form simultaneously parallel pulse width modulation signals corresponding to a plurality of gradation data, so that the circuit configuration is simplified.

The present invention will be explained below based on examples.

FIG. 2 is a fundamental circuit diagram of a thermal head drive circuit of a thermal facsimile to which the pulse width modulation circuit of the present invention can be applied. The thermal head is equipped with, for example, 1280 heating resistance elements for one line.
As shown in Fig. 2, 20 blocks of 64 resistive elements R1-1 to R1-64, R2-1 to R2-64...
..., R20-1 to R20-64. Each heating resistance element includes segment drive transistors Q1-1, Q1-2...Q1-64... and diodes D1-1, D1-2...D1-64.
A driving current is supplied through each of them. 64 resistive elements R1-1... are commonly connected and grounded, and each segment transistor Q1-1...
The collectors of 64 transistors are commonly connected to block drive transistors Q1, Q2, . . . , Q20.

Each block drive transistor Q1, Q2...
are sequentially driven in a time division manner by timing signals T1, T2... (FIG. 3, B, C...) supplied from the timing circuit 4, and a line image for one line is formed from T1 to T20. . Note that the timing circuit 4 is formed in synchronization with the line synchronization pulse SYNC (FIG. 3A) included in the image transmission signal a. Also, the segment drive transistor Q in each block
1-1, Q1-2... are comparators C1, C
2... Driven by the output of C64. The output of each comparator C1-C64 is commonly connected to the bases of the segment drive transistors of the 20 blocks.

The input image transmission signal a is, for example, a pulse amplitude modulation signal. This input signal a is supplied to the A/D converter 1 and converted into a digital signal.
The output (serial) of the A/D converter 1 is supplied to the memory 2, where it is divided by the number of elements in one block.
Converted to 64 parallel data d1 to d64,
It is supplied to each comparator C1 to C64. Note that each of the data d1 to d64 is a binary code corresponding to the number of gradations n. Note that the input image transmission signal is
In the case of a PCM signal, the input signal is directly supplied to the memory 2 without going through the A/D converter 1 and is converted into parallel.

On the other hand, by dividing the output of the oscillator 5 by a frequency divider 6, a clock pulse CP is obtained.
This clock pulse CP is supplied to the counter 7,
The output of counter 7 is output from each comparator C1 to C64.
are supplied in parallel. Assuming that the driving time of one block is T as shown in FIG. 3, the frequency of the clock pulse is f, and the number of gradations is n, f is set as f=n/T. That is, the count value within the driving time of one block is made to match the total number of gradations.

The counter 7 is reset by a reset pulse t from the timing circuit 4 immediately before driving each block. The output of the counter 7 is the gradation data d1 supplied to the comparators C1 to C64.
When it is smaller than ~d64, Fig. 3 D, E...
...As shown in F, the outputs of the comparators C1 to C64 are at a high level. and counter 7
When the output of the comparator becomes larger than the gradation data d1 to d64, the output of the comparator drops to a low level as shown in FIG. 3D, E...F. Therefore, a pulse width modulation signal corresponding to the gradation is obtained from the output of the comparators C1 to C64, which turns on the transistors Q1-1 to Q1-64, and turns on each of the resistive elements R1-1 to R1. -64 is heated. Note that the drive pulse width is T/n, 2T/n...nT/n depending on the gradation data. Since the heat generation temperature of each resistive element is proportional to the width of the energizing pulse, a line drawing of one block in one line displaying gradation can be obtained. Next, the second block, the third block, etc. are sequentially scanned, and when 20 blocks are completed, line feed is performed to form the next line drawing.

According to the drive circuit shown in Fig. 2, since there is no need to use a D/A converter, the cost of the circuit can be reduced, and variations in coloring due to variations in the resistance of the D/A converter can be prevented. There is no D/
There is also no need to adjust the gain of the operational amplifier of the A converter. Furthermore, when used in another system with different gradations, the number of gradations can be easily changed by simply changing the frequency division ratio of the frequency divider 6 or the output frequency of the oscillator 5.

Next, FIG. 4 shows an embodiment of a thermal head drive circuit to which the pulse width modulation circuit of the present invention is applied. The drive circuit shown in FIG. 2 requires comparators C1 to C64 with 64 segments in one block, which makes the circuit complex and increases the cost. FIG. 4 shows an arrangement that eliminates this drawback.

In FIG. 4, the image transmission signal a is converted into a digital signal by the A/D converter 1 in the same way as in FIG. be done. The contents of RAM 11 are read out by a 6-bit address counter 12. The operating clock CK of this address counter 12 is the oscillator 1.
3, whose frequency f _A is the clock pulse of the counter 7 that forms the count value according to the number of gradations.
It is set to 64 times or more the frequency of CP (f _A /f>64). That is, while the count value of the counter 7 increases by one, 64 addresses are generated from the address counter 12, and 64 gradation data are stored in the RAM 1.
It is read from 1.

The output of the RAM 11 is supplied to a comparator C and compared with the count value of the counter 7. The operation of comparator C is the same as in Figure 2. When the count value of counter 7 is smaller than the gradation data of the output of RAM 11, a high level output is obtained, and when the count value becomes larger than the gradation data, it becomes low. Flip to level. The output of comparator C is supplied to a 64 element latch circuit 14. This latch circuit 14
The addresses for the 64 elements are determined by the output address of the address counter 12, and the latch elements are selected in synchronization with the comparison operation of the comparator C (or the read operation from the RAM).

In this way, while the count value of the counter 7 increases by one, 64 pieces of gradation data are compared, and this operation is repeated the number of times (n×
64 pieces) are performed. When the output of the comparator C becomes low level in accordance with the gradation data stored in the RAM 11, the output of the latch element corresponding to this data becomes low level. As a result, 64 pulse width modulation pulses similar to those shown in FIG. 3D, E...F are obtained in parallel from the latch circuit 14, and these pulses are used as drive pulses for each resistor segment to be applied to the transistor Q1 in FIG. -1, Q1-2...
These are supplied to the bases of Q1-64, respectively.

In the embodiment of FIG. 4, a RAM 11, a latch circuit 14, an address counter 12 and an oscillator 13 are used.
However, since only one comparator C is required, the circuit configuration becomes relatively simple and a lower cost system can be constructed.

Next, FIG. 5 is a partial block diagram of a thermal head drive circuit showing a modification of the embodiment of FIG. 4. Generally, the color density characteristics of thermal paper are not linear with respect to head temperature. For example, the high concentration side has a characteristic that the change in concentration is smaller for the same change in head temperature compared to the low concentration side. On the other hand, on the other hand, the concentration change may be smaller on the lower concentration side. Furthermore, due to the heat capacity of the thermal head, the color development limit may not be reached unless a certain amount of current is passed through the head. Furthermore, the visual characteristics of the shading of the human eye are not uniform on the high-density side and the low-density side. Therefore, if the gradation change and the drive pulse width are set in a proportional relationship as in the embodiment shown in FIG. 4, the gradation of the image on the transmitting side may not be correctly reproduced on the receiving side.

For this reason, in the modified example shown in FIG.
The gradation and drive pulse width are made to change nonlinearly. This can be achieved by varying the period of the clock pulse CP supplied to the counter 7 in FIG. 4 according to a suitable variation curve.

In FIG. 5, a timing pulse t (FIG. 6A) with a period T obtained from the timing circuit 4 of FIG. 2 is supplied to a monomulti 8, from which a pulse b shown in FIG. 6B is obtained. This pulse b is supplied to an integrator 9, and a triangular wave c shown in FIG. 6C is formed. This triangular wave is supplied to a voltage controlled oscillator 10, from which a frequency modulated clock pulse CP as shown in FIG. 6D is obtained. Note 1
The total number of clock pulses in the block drive period T is:
As in FIG. 4, it is equal to the number of gradations. This clock pulse is supplied to the comparator C in the same manner as in FIG. 4, and is compared with the gradation data output from the RAM 11.

As a result, pulse width modulated drive pulses similar to those shown in FIG. 3D, E...F are obtained from the comparators C. The pulse width of this drive pulse increases as the gradation goes higher (higher density side). That is, the temperature change rate of the thermal head becomes large on the high-density side, and as a result, a multi-gradation image is obtained in which the coloring characteristics of the thermal paper are corrected. Note that the amount of heat generated by the thermal head is proportional to the integral value of the drive pulse width, so as shown in Figure 6, the amount of heat generated by the clock pulse
When the frequency of the CP is changed in a triangular waveform (linear equation), the heat generation characteristics of the head follow a square curve.

The heat generation characteristics of the head can be arbitrarily changed by the control voltage waveform supplied to the voltage controlled oscillator 10, and a triangular wave having a slope opposite to that of the triangular wave shown in FIG. 6C may be used as the control voltage. Other curves, polygonal lines, etc. may be used as the control voltage.

As described above, the present invention compares the output of a counter that counts clock pulses with digital gradation data having gradation information, and determines the comparison output level when the reference gradation data of the counter output and the gradation information match. By changing this, a pulse width modulated signal can be obtained even with gradation information. Also, while the count value of the counter increases by one, all gradation data is read out from the memory, and the comparator sequentially compares it with one reference gradation data output from the counter, and compares it with the latch element group corresponding to the data number. The comparison result is stored in the corresponding address, and a pulse width modulation signal for forming gradated printing dots is obtained from each latch output. Therefore, instead of using a D/A converter to express gradations at the signal level as in the past, multi-gradation dot printing can be performed using pulse width modulation, so the gradations associated with D/A conversion can be printed using pulse width modulation. Variations in color are less likely to occur, and high-quality printed images can be obtained with good reproducibility. In addition, basically only one comparator is required, which is the main part of the circuit that generates the pulse width modulation signal, and the memory that stores the gradation data and the latch circuit that stores the comparator output are synchronously controlled by the address. Since the comparators are substantially time-divisionally operated to obtain the pulse width modulation signals for forming a large number of printed dots simultaneously and in parallel, the circuit configuration is simple and the cost is low.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional thermal head drive circuit for multi-gradation image facsimile, FIG. 2 is a theoretical block diagram of a thermal head drive circuit for facsimile to which the present invention can be applied, and FIG. 4 is a block diagram of a thermal head drive circuit showing an embodiment of the present invention, FIG. 5 is a block diagram of main parts showing a modification of FIG. 4, and FIG. 5 is a signal waveform diagram of each part in FIG. 5. FIG. In addition, in the symbols used in the drawings, 1...A/D
converter, 5, 13... oscillator, 7... counter,
11...RAM, 12...Address counter, 1
4...Latch circuit, C...Comparator.

Claims (1)

[Scope of Claims] 1. A memory for storing a plurality of gradation data to be pulse width modulated, and a memory for sequentially generating reference gradation data from a minimum reference gradation to a maximum reference gradation in accordance with a first clock pulse. a second counter that is driven by a second clock pulse having a sufficiently higher frequency than the first clock pulse and generates an address signal for the plurality of gradation data; A comparison output is sequentially generated by comparing one gradation of the reference gradation data to be read from the memory according to the address signal from the second counter, and each reference gradation data is It has a comparator that repeats this for each gradation, and an address that corresponds to the above plurality of gradation data, receives the comparison output of the above comparator, sequentially takes it into the corresponding address, and from the corresponding address corresponds to the above plurality of gradation data. A pulse width modulation circuit comprising a latch circuit that obtains pulse width modulation outputs in parallel. 2. The first clock pulse supplied to the first counter that generates the reference gradation data is generated by a variable frequency oscillator, and the output frequency of the variable frequency oscillator is controlled so that the pulse width modulation output and the above The pulse width modulation circuit according to claim 1, wherein the pulse width modulation circuit is configured to have a nonlinear relationship with gradation data.