JPS6239963A - Thermal head - Google Patents

Abstract

PURPOSE:To speedify thermosensitive recording and to improve resolution by determining the width of a pulse to drive a heating element using the bit data of a memory element and the pulse-integrating value of strobe clock signal transmitted as a supplied-pulse width information. CONSTITUTION:The output data of a counter circuit 7 and the data of respective 8-bit latch circuits 2 are detected of their coincidence by a coincidence circuit 9. When all the data of the eight bits coincide with each other, the output data becomes H, which is inputted to a pulse duration determining circuit 10, and also, the output gate of the circuit 10 remains in H for a time from the leading edge of the strobe signal 4 which is another input to the time when the output of the circuit 9 becomes H. Therefore, during the said time, a switching element 3 is in ON-state. Accordingly, the pulse duration to drive the heating elements 5 is determined by the gradation data of drive circuit 6 of respective heating elements 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a direct drive type thermal head in a thermal recording system, and more particularly, to a thermal head that can perform density control and gradation recording at high speed and high resolution with a simple configuration. It is something.

[Prior Art] Thermal recording method is simple and has been widely used in recent years. In this method, a heat-generating resistor formed on a substrate is selectively passed through to color the recording paper, and various driving methods are known.

There is a conventional direct drive type thermal head disclosed in Japanese Unexamined Patent Publication No. 59-133081, which is shown as a circuit block diagram in FIG. This is a thermal head in which switching elements are connected to heating elements arranged in a line and integrated into the thermal head, and the recording data is sent to a shift register or latch circuit for one line. It has become.

That is, for example, data for one line is input in series to the shift register (1), and then the contents of the shift register (1) are transferred to the latch circuit (2) using a latch signal.

With the contents of this latch circuit (2), the switching is 0N1.
The 0FF8 state is determined, and the 8 generating elements (5) are energized by the strobe signal (4) and the ON signal, thereby generating heat and recording an image. In addition, the strobe signal (4)
are commonly connected to all bits or arbitrary plurality of pins). Therefore, it is not possible to change the energization time to each heating resistor, that is, the print pulse width, at the same timing. In other words, one line of data transferred to the shift register (1) or latch circuit (2) can only be in a 1 or O state when viewed in bits. The following describes the operation of controlling the density of N gradations using this circuit.
I will explain.

The energy EO applied to the heating element (5) is expressed by the following equation. Here ■ is the recording power supply voltage, R is the heating element (5)
, ROM is the resistance component of 0NI19 of the switching transistor mentioned above, and t is the print pulse width.

Eo = Pot = l2Rt =□・Rt (R+ROM)2 In other words, when ■ and R are constant, the energy EO
The parameters of the change are the resistance component RON and the print pulse width t. Of these, regarding the resistance component RQ)1,
Its own variation is about ±35%, and it is not suitable for high-level gradation control. Therefore, the method of changing the printing pulse width t is arbitrary.

FIG. 6 is a timing chart of a method for changing the printing pulse width t, showing an example of 258 gradations. 25
One line of data with eight gradations of information needs to be sent 256 times (Kl,
2. ...K258). Every time this Kn is sent out, a latch signal is raised and the switching element's 0N10FF$
Change E.

no+ is an example of 2/25B gradation. In this case, K1
In Toni 2, the bit corresponding to Do2 is “1”,
In K3~258, data in which the bit corresponding to 002 is "0", that is, OFF, is transferred. Note that the strobe signal (4) is kept in the ON state during the 25e/256 gradation time period. In this way, the pulse width is arbitrarily changed within the basic pulse width ts and in steps of 1/258.

[Problems to be solved by the invention] Since the conventional thermal head is configured as described above, if it has only one shift register or latch circuit, that is, a memory function for one heating element, the data transfer speed will be low. Regarding f, the following formula basically holds true. Here, N is the number of bits of the serial shift register or the number of bits of the latch circuit, the sentence is the number of floors #A, and t is the maximum value of the print pulse width.

For example, f = 4[MH2l, t = 1. ],
[m5ec], N = 128 If you try to increase the number of gradations, which becomes 232 gradations when bitl, you will increase f but you will need to decrease N or increase t. It's coming. The increase in f is due to the increase in IC that makes up the circuit.
It is determined by the characteristics of MOS Nite 6Hz, bi-C
The current limit is 12.5 MHz for MOS.Furthermore, it is not desirable to increase f from the viewpoint of noise. Furthermore, an increase in t hinders high-speed drawing. Furthermore, a reduction in N results in a reduction in the number of bits of the shift register or latch circuit, resulting in an increase in the number of input data, which leads to the problem of complicating data processing.

This invention was made in order to eliminate the problems of conventional thermal heads as described in "-."
The object of the present invention is to obtain a thermal head that can perform density control and gradation recording with a simple configuration and high resolution.

[Means for solving the problem] The thermal head according to the present invention generates heat from the bit data of the memory element storing image information data and the pulse integrated value of the strobe clock signal transferred as applied pulse width information. The pulse width for driving the elements is determined, and each of the heating elements is driven based on a drive signal of this pulse width.

[Operation] The thermal head according to the present invention includes an m-bit memory element as data for driving one heat generating element, and determines the pulse width for driving the heat generating element based on whether the data matches the output data from the counter circuit.

"Embodiment" An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. Figure 1 is the overall circuit diagram of this embodiment, and Figure 2 is the overall circuit diagram of this embodiment.
Figure 1 shows a timing chart of the circuit shown in Figure 1.
- In the reporter diagram, (1) is an 8 x n-bit shift register, (2) is an 8 x n-bit latch circuit, and (3) is an n-bit shift register.
(4) is a strobe signal that determines the drive timing of the heating element (5), (6) is an 8-bit shift register (1), an 8-bit latch circuit (2), and a switching element (3). The drive circuit (7) for one element of the heating element (5) is configured by integrating the number of pulses of the strobe clock signal (8) predetermined from density characteristics, recording paper characteristics, etc., and outputs the strobe signal ( 4) counter circuit that cancels this integration; (8)
is a strobe clock signal to the counter circuit (7), which has a predetermined number of pulses determined by heating element characteristics, density characteristics, recording paper characteristics, etc., and is transferred as applied pulse width information; Exclusive φ Noah circuit (81
) and an AND circuit (82), and a counter circuit (7
The matching circuit (10) that detects the match between the output of the latch circuit (2) and the data of the latch circuit (2) is composed of a flip-flop, and the heating element ( 5) is a pulse time determining circuit that determines the driving pulse and is connected to the input gate of the switching element (3).

Next, the operation of controlling the density of vertical gradations using this embodiment will be explained. FIG. 2 is a timing chart showing the case of 256 gradations in the configuration of FIG. 1.

Now, the drive circuit (8) for each heating element (5)
The configuration consists of a shift register (1) that receives 8-bit serial data input, and an 8-bit latch circuit (2) connected to the 8-bit shift register (1). The amount of information in the 8-bit shift register (1) is:
2B=258, and the data of 258 gradations is "o"
, 1'' can be expressed as 8 bits.

Therefore, the gradation data per element of each heating element (5) is set as 8 bits), and the data of the number of heating elements (n pieces) x 8 bits is transferred sequentially as serial data, and the data is transmitted as a latch signal. By leading to the latch circuit (2), 256 gradation data of each heating element (5) of one printing line can be stored.

Here, when the pulse input of the strobe clock signal (8) is made, the counter circuit (7) starts counting the strobe clock signal (8).
) changes depending on the number of pulse inputs. This counter circuit is configured as 28=2513 counters. Now, the output data of this counter circuit (7) and the data of each 8-bit latch circuit (2) are subjected to coincidence detection by a coincidence circuit (8), and when all of the 8-bit data match, the output data is becomes "H" and is input to the pulse time determining circuit (10), and the pulse continues from the rise of the strobe signal (4), which is another input, until the output of the matching circuit (8) becomes "H". The output gate of the inter-plane determining circuit (10) maintains an "H" output.

Therefore, the switching element (3) is 'ON' during this period.
" state, and the pulse time to drive the heating element (5) is determined by the gradation data of the drive circuit (6) of each heating element (5). Also, the strobe signal (4) is activated by the counter circuit at its rising edge. (7) is cleared, and the counter circuit (7) and strobe signal (4) are synchronized.

On the other hand, by arbitrarily changing the 256 pulse intervals of the strobe clock signal (8), the gradation drive pulse time ts can be made nonlinear.

In addition, in the above embodiment, each heating element (5) has 8
Although a case has been shown in which the configuration includes a 8-bit shift register (1) and an 8-bit latch circuit (2), as shown in FIG. 1) and an 8-bit latch circuit (
2), and the timing chart shown in Figure 4).
As shown in FIG. 2, the gradation recording data of one printing line may be held in the latch circuit (2) by eight data transfers and a latch signal.

Alternatively, eight memory elements may be provided for each heat generating element, and the memory elements may be connected in parallel to the memory elements of the next heat generating element.

Furthermore, a matching circuit (9) and a pulse time determining circuit (
In 10), the circuit configuration etc. may be changed as long as the scope of the claims of the present invention is not exceeded, and the same effects as in the above embodiment can be obtained.

[Effects of the Invention] As described in ``2'' below, the thermal head according to the present invention combines bit data of a memory element in which image information data is stored and a pulse integrated value of a strobe clock signal transferred as applied pulse width information. The pulse width for driving the heat generating elements is determined from
In the case of 6 gradations, there is no need to transfer 1 line print data 256 times, and 258 gradations can be achieved by simply transferring 8 times the number of print data for 1 line, and high frequency is not required for data transfer. Moreover, high gradation recording can be performed with extremely simple data transfer, and non-linear gradation control can be performed to perform high-grade gradation control recording, which has the effect of increasing the speed and resolution of thermal recording.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a thermal head according to an embodiment of the present invention, FIG. 2 is a timing chart of FIG. 1, and FIG. 3 is a circuit diagram of a thermal head according to another embodiment of the present invention.
FIG. 4 is the timing chart of FIG. 3, FIG. i5 is a circuit diagram of a conventional thermal head, and FIG. t56 is a timing chart of FIG. 5. In the figure, (1) is a shift register, (2) is a latch circuit, and (5)
is a heating element, (7) is a counter circuit, (8) is a coincidence circuit, and (10) is a pulse time determining circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (7)

[Claims] (1) A thermal head that uses a direct drive method to heat a plurality of heat-generating elements to store heat-sensitive memory, is formed by a memory element with m bits per element, and data transferred as image information to this memory element is a storage means for storing, an integration means for integrating the number of pulses of the strobe clock signal transferred as applied pulse width information, and a coincidence detection for detecting a match between the integrated value of the integration means and data in m bits of the storage means. a thermal device comprising means for determining a pulse width for driving the heating element based on the coincidence detection by the coincidence detection means, and driving the heating element with a drive signal having this pulse width. head. (2) The thermal head according to claim 1, wherein the integrating means is constituted by a counter circuit that counts 2^m. (3) The coincidence detecting means includes a plurality of exclusive NOR circuits to which the output bits of the integrating means and m bits per element of the storage means are respectively input, and each of the plurality of exclusive NOR circuits. Claims 1 and 2 further include an AND circuit into which outputs are input and which takes an AND condition for each output, and a pulse width for driving each heating element is determined based on the output of the AND circuit. The thermal head according to either item 1 or 2. (4) The storage means is configured to include one shift register circuit and m latch circuits for each heating element. The thermal head described in any of the above. (5) The thermal head according to any one of claims 1 to 4, wherein the storage means is constructed by cascading m-bit memory elements. (6) The storage means is constructed by connecting a memory element of one heat generating element in parallel to a memory element consisting of m bits of the next heat generating element. The thermal head according to any one of Item 5. (7) The integration means is configured such that a single integration unit performs integration with respect to the storage means in which data for driving a plurality of heating elements is stored.
The thermal head according to any one of items 6 to 6.