JPS61227074A - Thermal head driving circuit - Google Patents

Abstract

PURPOSE:To enable favorable heat accumulation control and density gradation recording, by generating a printing output for a period of time according to image data. CONSTITUTION:The image data 12 are held in a latch 14. A printing signal 20 causes a counter 17 to starts counting enable clocks 18. The count output is supplied to a comparator 16 as input data one one side, whereas image data converted to a pulse width held in the latch 14 are supplied to the comparator 16 as input data on the other side, and the two pieces of input data are compared with each other. The comparator 16 continues generating an output until the output from the counter 17 becomes larger than the image data. As a result, a printing output is generated by a gate circuit 19, a driver 22 is turned ON, and an electric current is passed to a heating element 21, thereby performing printing. When the output from the counter 17 becomes larger than the image data, supply of current to the resistor 21 is stopped. Accordingly, the density of recorded images is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thermal head drive circuit used in a high-speed, high-sensitivity thermal head.

[Technical background of the invention and its problems]

Recently, improvements in office efficiency have been considered under the name of office automation, and in order to achieve this, various types of
A device is being used.

Incidentally, in such OA equipment, a thermal recording device typified by a thermal transfer recording device is often used as an output terminal device because it makes little noise during recording, has a simple mechanism, and is easy to maintain. These thermal recording devices are relatively easy to colorize, and the colors are vivid, so they have begun to be used as color printers, and more recently, there has been considerable research into halftone expression using thermal recording devices.
For example, there is the area gradation method that binarizes image data using a dithering method or the like to express halftones, or the density gradation method that obtains image density by controlling the amount of heat generated according to the image data and changing the area of one recorded pixel. Halftone recording such as toning is also being considered.

However, such a thermal recording apparatus has a drawback that when recording a binary image, the density of the recorded image becomes non-uniform due to the heat storage effect of the heating resistor constituting the thermal head.

The reason for this is that as the cycle of energization to the head becomes shorter as the recording speed increases, new energization is performed before the heat generated in the previous energization cycle has been sufficiently dissipated. As this accumulation of heat progresses,
There is a considerable temperature difference between the heating resistor that is continuously energized and the heating resistor that is energized for the first time, resulting in a large difference in image density.

Therefore, in order to cope with the heat accumulation effect of such a thermal head, it has been considered to control the energy applied to each heating resistor of the thermal head. That is,
This idea is to apply a short energizing pulse to a heating resistor that has been repeatedly energized, or to a heating resistor that is mostly energized even when energized for the first time, and to a heating resistor that is not energized. Although long energizing pulses are applied to the heating resistors, the width of the energizing pulses for each heating resistor must be changed frequently depending on the situation.

On the other hand, when recording density gradations as described above, it is necessary to finely change the width of the current pulse to the heating resistor in order to produce many gradations. In particular, when performing density gradation recording at high speed, the pulse width must be changed with even higher precision in consideration of the influence of heat accumulation.

Therefore, a thermal head drive circuit as shown in FIG. 13 has been considered as a thermal head drive circuit that can realize these conditions.

In the figure, 1 is a shift register and 8I of this register 1
Image data 2 converted into binary data is applied to the N terminal. Since the image data in this case is thermally controlled, it consists of a plurality of bits, for example, 4 bits as shown in FIG. 14(a).

First, only the first bit of this image data is given to the SIN terminal of the shift register 1 as image data 2, and this is sequentially transferred within the shift register 1 in synchronization with the clock signal 3.

Then, when the first bits of image data corresponding to the total number of heat generating resistors of the thermal head are transferred, a latch signal 4 is applied and the data transferred to the shift register 1 is transferred to the latch 5.

In this state, when the print signal 6 is applied, this print signal 6 and the output of the latch 5 are applied to the gate circuit 71. Therefore, if the first bit of the image data is @"l#, the output of the latch 5 will be "1", so the print signal 6 will be output as is from the gate circuit 7, the driver 8 will be turned on, and a current will flow through the heating resistor 9. flows and printing is performed, while @0
”, the output of latch 5 is @0, so gate circuit 7
The output remains at 0, no current flows through the heating resistor 9, and no printing is performed.

When the printing of the first bit of the image data is completed in this way, the second bit is then transferred to shift register 1 and printed as described above, and the third and fourth bits are subsequently printed in the same manner. The printing of one bit is completed.

In this case, as shown in FIG. 14(a), when the first bit data D is "1", the pulse width of the print signal is T.

The pulse width of the print signal when the second bit data D is @1'' is T2, and the pulse width of the print signal when the third bit data D3 is ``l'' is T4, and the pulse width of these print signals is For example, the ratio is T, :T, :T, :T, ==1:2:
If the ratio is set to 4:8, printing with a maximum of six density gradations can be performed using 4-bit image data. FIG. 14(b) shows an energizing pulse supplied to the heating resistor 9 when the 4-bit image data is 1011, for example.

Next, FIG. 15 shows a timing chart for actually driving the line thermal head. In this case, in the line thermal head, if a current is passed through all the resistors at once, a very large current will flow and a power supply with a correspondingly large capacity will be required. Therefore, an example is shown in which the entire head is divided into two blocks in advance.

FIG. 4(a) shows image data, and the first bit of image data is first given to the shift register 1 in synchronization with the clock shown in FIG. 2(b). When the data transfer of the first bit is completed, the latch signal shown in FIG.
The bit-th image data is transferred to the latch 5, and then the print signal shown in FIG. 2(d) is applied, and the first bit data @11 is printed. This printing has a pulse width T1 as shown in FIG. 14(a). Further, at the same time, the second bit data is supplied together with the clock signal. - When the data transfer of the second bit is completed and the printing of TI is completed, the latch signal is applied again, the image data of the second bit is transferred to the latch 5, and the second pulse @T! is printed, and at the same time data transfer of the third bit is performed.

By repeating this operation four times, printing of the first block is completed. Furthermore, by printing the second block in the same manner, data printing for one line is completed. In this case (4
indicates the print signal in the second block.

Therefore, in the case of the above-mentioned two-block drive, eight data transfers and eight printing operations are required in such a conventional thermal head drive circuit to perform 16 types of pulse width control using 4-bit image data. However, in this case, it takes a considerable amount of time to print one line of data, and in addition to this, the following disadvantages occur.

That is, for example, if the printing cycle of one line is 1m5ec,
Considering the case of the two-block drive shown in Fig. 15 described above for an A4-width line thermal head with a resolution of 16 dots per line, the printing pulse width per block in this case is 0.5 m5ec; between 2
048 bits of image data must be transferred four times, and therefore it is not possible to transfer data within this time unless a data transfer clock signal of 15 MHz or higher is used. Therefore, it is conceivable to divide one block into four parts, that is, to divide only the image input terminals of the entire thermal head into eight parts, thereby making it possible to transfer data with a data transfer lock of about 4 hours or more. However, at present, there is no thermal head that guarantees data transfer of 4 MHz or higher, and the maximum is about 2 MHz. However, when using such a thermal head, it is necessary to prepare 16 input terminals to the thermal head drive unit, and increasing the number of input ports in this way means that the line for supplying data to the thermal head is If the amount of data increases, or in order to output data to the thermal head RAD, one line of data is divided into 16 pieces, and a buffer memory or the like is required to hold the data. will become larger.

Further, even if data transfer is guaranteed with a clock signal of about 4 MHz and data transfer is possible by dividing the whole into eight, a time of 128 μsec is required for one data transfer. In this case, the time required for one printing cannot exceed at least the data transfer time. This is because if an energization pulse shorter than the time for one data transfer is used, there will be a period of non-printing between the first and second printing, which will be troublesome when calculating the amount of heat storage. Therefore, if the shortest energizing pulse width is taken as the width of the data transfer time, in this case, energizing pulses of 128 μsec or less cannot be used. Also, this 1
If printing is performed eight times using a 28 μsec current pulse, the printing time for one line will be approximately 1,024 msec. Therefore, in such printing, a periodic period of 1 m5ec is achieved only when all the pulse widths of T1 to T4 described above are the same. However, if the pulse widths of Ti to T4 are all equal, only four types of energizing pulses can be obtained at most. This is particularly true in the case of high-speed driving, which results in a considerable amount of heat accumulation, which not only makes it impossible to sufficiently control the heat accumulation with about four types of pulse width modulation, but also makes it almost impossible to express density gradations.

For these reasons, conventional thermal head drive circuits not only cannot achieve high-speed data printing, but also cannot reliably perform heat storage control or density gradation recording to obtain a good degree of release.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a thermal head drive circuit that can speed up data printing, and perform heat storage control and density gradation recording with good power. purpose.

[Summary of the Invention] The thermal head drive circuit according to the present invention sets multi-bit image data having density information by one data transfer, generates print output for a time corresponding to this image data, and uses this output to Printing is performed by energizing the heating resistor.

〔Effect of the invention〕

According to this invention, since a plurality of bits of image data are set in one data transfer, the data transfer time can be significantly shortened, and the data printing speed can be increased accordingly. Moreover, since the energization of the heat generating resistor can be controlled by printing output for a length of time according to the image data, recording densities of multiple gradations can be achieved, making it possible to perform density gradation recording including highly accurate heat storage control. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration diagram of the same embodiment.

In Figure 1ζ, 11 is a shift register, and this register 1
1, multiple bits of image data 12 having density information are provided in synchronization with a clock signal 13.

A latch 14 is connected to the shift register 11. This latch 14 holds the contents of the shift register 1 in response to a latch signal 15.

A comparator 16 is connected to the latch 14. A counter 17 is connected to this comparator 16. Here, the counter 17 counts an enable clock 18 independent of the clock signal 13. As a result, the comparator 17 is made to always generate an output @1'', and the count output of the counter 17 is latch 1.
We use something that outputs @O'' when the value exceeds the content of 4.

A gate circuit 19 is connected to the comparator 17.

The gate circuit 19 is supplied with a print signal 20, and the print signal 20 and the comparator 17 output @
While l'' is being generated, a print output @l'' is generated and the driver 22 of the heating resistor 21 of the thermal head is turned on.

On the right, the print signal 20 is also given to the counter 17 so as to clear the same counter 17.

Next, the operation will be explained using the timing chart shown in FIG. Here, FIG. 2 shows a timing chart when the thermal head drive circuit shown in FIG. fs1 is applied to a line head.

By the way, line thermal heads are generally 2000 to 4
There are as many as 000 heating resistors. For this reason, energizing these heat generating resistors at once requires a fairly large capacity power source, so normally several blocks are energized.

In FIG. 2, it is divided into two blocks.

First, a first line of multiple bits of image data 12 having density information is provided to the shift register 11 in synchronization with a clock signal 13 . In this case, the image data 12 is not an image density signal obtained from a scanner or a television signal, but is the image data supplied according to the density characteristics of the printer converted into data of the printing pulse width supplied to the heating resistor. be. In other words, in general, in thermal printers, the pulse width supplied to the heating resistor and the printed image density have a non-linear relationship as shown in Figure 3. Therefore, if the image data is directly used as the energizing pulse width, the desired energizing pulse width will be obtained. It is not possible to obtain the desired concentration.

Therefore, based on the relationship shown in FIG. 3, the image data is converted into pulse width data I of the thermal printer, and this is supplied as image data 12.

Such image data 12 is transferred within one multi-bit shift register in synchronization with a clock signal 13. In this case, data is transferred to the @1 block and the second block.

When all the data of each block i has been transferred, a latch signal 15 is applied and the transferred image data 1
2 are all transferred to the latch 14 and held there.

In this state, a print signal 201 for printing the first block of the first line is first applied. The print signal 201 in this case has the same pulse width as the maximum print pulse supplied to the heating resistor 21, that is, the print pulse output by the thermal head that produces the maximum image density.

Further, at the same time as the print signal 201 is applied, the image data 12 of the second line is transferred to the shift register 11. The reason why the data of the next line is transferred while the image data 12 of the ta1 line is held in the latch 14 is to improve the printing speed per line.

On the other hand, the print signal 201 causes the counter 17 to be enabled for counting. Then, the counter 17 starts counting the enable clock 18. The count output of this counter 17 is given as one input data of the comparator 16. At this time, the image data converted into the pulse width held in the latch 14 is given to the comparator 16 as the other input data, and is compared with the output of the counter 17. In this case, the comparator 16 generates an output "11" until the output of the counter 17 becomes larger than the image data converted into a pulse width, and sets the output to "O" when the output of the counter 17 exceeds the image data. ing.

Therefore, until the count output of the counter 17 becomes larger than the image data, the comparator 16 outputs '''
l# continues to be generated and is applied to the gate circuit 19 together with the print signal 201. As a result, the gate circuit 19
A print output of "1" is generated, the driver 22 is turned on, current flows through the heating resistor 21, and printing is performed. and,
Thereafter, when the count output of the counter 17 becomes larger than the image data, the comparator 16 outputs °0#, the gate circuit 19 also outputs a printout of 10'', and the power to the heating resistor 21 is cut off.

In this way, the @1” output of the comparator 16 and the print signal 2
01 controls the power at which the driver 22 of each heating resistor 21 is switched, thereby controlling the density of the recorded image on each heating resistor 21. This means, for example, that the heating resistor 21
If a small value is set as the image data 12 for , the output of the comparator 16 will become O before the count value of the counter 17 is small, so the heating resistor 21 in this case is only energized for a short time. If this is not done, the image density will be low. Conversely, if you set the image data 12 to a large value for the heating resistor 21 on which you want to record a dark image point, the output of the comparator 16 will remain at 1 m until the count value of the counter 17 reaches a large value l. Therefore, the driver 22 is in the on state for a long time, and the heating resistor 21
In J, current flows for a long time and the image density becomes high.

In this manner, printing of the fal block is performed while controlling the recording density at each heating resistor 21.

When the printing of the first block is completed, the printing signal 202 of the second block is outputted, and the printing of the second block is also carried out in the same manner, and the printing of the first line is completed. .

, -9 is also 7. In this case, the data of the second line is transferred to the shift register 11 at the same time as the first line is printed. Then, when the data transfer for the second line is completed and the data printing for the first line is completed, the latch signal 15 is applied again and the data for the second line is transferred to the latch 14. Thereafter, in the same manner, the printing of the second line is carried out and at the same time the data of the third line is transferred, and such a process is repeated for all the lines to complete the printing of all the lines.

Note that in the above, the pulse width of the print signal 20 is set to be the same as the print pulse that maximizes the image density, but in reality, the pulse width of the print signal 20 is the same as the print pulse that maximizes the image density.
It is preferable that the count capacity is equal to or less than 7. That is, when the counter 17 is, for example, 8 bits, it is preferable that the print signal has a length equal to or less than the period of the enable clock 18 times 255. This has the advantage that the pulse width supplied to each heating resistor 21 can be continuously changed.

According to such an embodiment, data is transferred only once regardless of the number of bits of image data, and the pulse width for energizing each heating resistor can be selected in units of the cycle length of the enable clock. In other words, even if 8 bits are used for image data, for example, it is possible to select a maximum of 2565 pulse widths in one data transfer. This means that the drive speed can be dramatically increased compared to the conventional 8-bit image data, which required eight data transfers, and it is also possible to continuously achieve recording densities as many as 256 gradations. It is possible to perform density gradation images as well as highly accurate heat storage control.

By the way, an actual thermal printer cannot express a recorded image with as many as 256 gradations; for example, even when sublimation ink is used, only 32 gradations can be expressed. However, when the thermal head is operated at high speed, the density of the image becomes considerably different between the start and end of printing due to the influence of heat accumulation in the thermal head. In such a case, fairly fine control of the energizing pulse width is required, and more types of gradations than the number of gradations that can actually be printed are used. For example, if it is desired to output an image with 32 gradations, 64 types or 128 types are required. Further, fine pulse width control is also required when expressing a density gradation image using the dither method or the like instead of the density gradation method. However, even in these cases, if a device having the features of the above embodiments is used, all of the above conditions can be satisfied and good control with high accuracy can be expected.

On the other hand, there is a conventional device that uses about 4 types of energizing pulses to obtain up to 16 types of control, but since this requires data transfer 4 times, only 4 types of energizing pulses can be used at high speeds. Moreover, the length between each of the four types of pulse widths also changes digitally in stages, making it impossible to control them sufficiently. However, even in such a case, if the above-described embodiment is used, all of the above-mentioned disadvantages can be eliminated and good control can be performed.

Next, FIG. 4 is a schematic configuration diagram showing another embodiment of the present invention.

In this case, in FIG. 4, the shift register 11 in FIG. 1 is removed, and other parts are the same as in FIG. 1, and the same parts are given the same reference numerals.

By doing this, the circuit configuration can be simplified, although the speed increase will be sacrificed to some extent. That is, in this case, image data 12
is transferred to the shift register constituted by the latch 14, and then the tP character multiplication signal 20 is output, and when printing is completed, the timing is such that the data of the next line is transferred.
The printing cycle is determined by data transfer time + printing time. For this reason, the printing cycle is somewhat delayed, but the circuit configuration can be simplified since there is no shift register.

However, if you use a line thermal head that divides the entire head into two blocks, such as the line thermal head described in Fig. 2, it is possible to achieve a printing cycle equivalent to that of the one in Fig. M1. During this time, the second block is printing the previously transferred data, and when the data transfer of the first block is completed and the printing of the second block is completed, the minute degree prints the first block and at the same time prints the second block. Transfers data for the next line of the block. By doing this, the printing cycle of one line is determined by the longer of the data transfer time and the printing time, and can be made substantially the same as that in FIG. 1.

Next, FIG. 5 (alΦ) is a schematic configuration diagram showing only the essential parts of still another embodiment of the present invention.

By the way, in FIG. 1 mentioned above, restrictions are set in advance on the pulse width of the print signal 20. That is, the pulse width at this time is made equal to or less than the count capacity of the counter 17. On the other hand, in another embodiment, in addition to the counter 17, a 7-lip flop 23 and a gate 24 are provided, so that when the value of the counter 17 reaches the maximum value, no further print signal 20 is output. That is, the Q output of the flip-flop knob 23, which was set to @1" before the print signal 20 was output, is inverted to @0" by the carry signal 25 that is output when the value of the counter 17 reaches the maximum. By passing this signal and the print signal 20 through an AND gate 24, the print signal 20 cannot be output.

This has the advantage that the signals can be generated without worrying too much about the relationship between the print signal 20 and the enable clock 18, and it is also possible to prevent damage to the thermal head due to circuit malfunction.

Next, FIG. 6 is a schematic configuration diagram showing still another embodiment of the present invention.

In this case, in FIG. 6, latch 14 of FIG. The comparator 16 and the counter 17 are replaced with a counter 17 and a flip-flop 23, and the other parts are the same as in FIG. 1, and the same parts ζ are given the same reference numerals.

In this way, the scale of the circuit elements can be reduced by about 1 compared to the one shown in FIG. In such a circuit, image data 12 is first transferred to shift register 1 in synchronization with clock signal 13.
1 is transferred. When the transfer of all data is completed, the LD signal 26 is output and the transferred data of the shift register 11 is loaded into the counter 17. Here, the LD signal 26
is for setting a value in the counter 17 and is the same as the latch signal 15 described above. When the pulse width converted image data is set in the counter 17, the print signal 20
is given. Since this signal 20 is applied to the EN terminal of the counter 17, the counter 17 enters the count enable state and opens the count. In this case, if a down counter is used that outputs a carry signal when the value set as the counter 17 becomes 1'', then the counter 1
7 outputs a carry signal 25 when the enable clock 18 is counted down by a preset value, and this signal 25 is applied to the flip 70 knob 23. This flip-flop 23 remains "1" until the print signal 20 is applied and the carry signal 25 is output from the counter 17, and the driver 22 is turned on during this time. Note that, after the print signal 18 is output, the flip-flop 23 outputs the -H carry signal 25 and becomes "0", and no matter how many times the carry signal 25 is output thereafter, the flip-flop 23 remains at 10" until the print signal 20 disappears. This makes it unnecessary to strictly consider the relationship between the enable clock 18 and the print signal 20, as described in FIG.

Next, FIG. 7 is a schematic configuration diagram showing still another embodiment of the present invention.

In this case, FIG. 7 is a modification of FIG. 6, and the same parts as in FIG. 6 are given the same reference numerals. By the way, the print signal 20 described so far is actually mostly responsible for setting the count enable state, and although it sets the maximum energization pulse width, it does not directly set the energization pulse width to the heating resistor 21. In other words, since the energizing pulse width is determined by the time from when the print signal 20 is output until the value of the counter 17 reaches a certain value, a long width print pulse as shown in the timing chart of FIG. All you need is a start pulse to start the process. FIG. 7 is based on this idea, and after the transferred image data 12 is set in the counter 17 by the LD signal 26, a print start signal 27 is output. The output of the flip-flop 23 becomes 1m due to this signal 27, and the output of the driver 22
is turned on and energization of the heating resistor 21 is started. At the same time, the counter 17 enters the count enable state and starts counting the enable clock 18.

Then, when the clock 18 is counted by the value indicated by the image data set in the counter 17 in advance, the counter 1
A carry signal 25 is output from 7 and the flip-flop 2
As soon as the output of 3 is @O'', the power supply to the heating resistor 21 is stopped. By doing so, the circuit can be designed without considering the relationship between the enable clock 18 and the print signal 20 as described above. Note that this print start signal 2
7 is not limited to being supplied from the outside as shown in FIG. 7, but may be generated within the circuit. This signal 27 also indicates that the image data 12 is transferred from the shift register 11 to the counter 17.
For example, the 8th
As shown in FIG. 8(a), the output of the monostable altivibrator 28 triggered by the rising edge of the LD signal 26 may be used, or as shown in FIG. 8(b), delay elements such as flip-flops 29 and 30 may be used. It may also be an output using . However, in the case of FIG. 8(b), since the LD signal 26 uses the enable clock 18 as the CK signal of the flip-flop 29, a signal with a longer cycle than the clock 18 is required. This allows the LD signal 26 to be used in place of the print start signal 27, which has the advantage of reducing the number of external signal lines. In addition, the reset signal 31 shown in FIG. 7 is used to set the output of the flip-flop 23 to @0'', and is used to prevent current from flowing to the heating resistor 21 when the power is turned on, or to turn on the current regardless of image data during the power-on. This signal 31 is useful, but it is hardly needed for normal operation and is only needed when the power is turned on. By providing a normal power-on reset circuit 32, there is no need to provide an external reset signal 31.In other words, the circuit shown in FIG. 7 uses the circuits shown in FIG. There is no need to supply it from the outside, and it can be simplified accordingly.

Furthermore, the shift register αυ shown in FIGS.
It can be omitted as in the figure.

Generally, a counter αη has a parallel input terminal and a parallel output terminal, so by connecting the parallel output terminal to the parallel input terminal ζ of the next counter αη and further supplying a clock signal to the LD terminal, data transfer is performed using a shift register. This is because the counter α force itself can be used instead of r11). By doing so, the circuits shown in FIGS. 6 and 7 can be further simplified.

Next, FIG. 9 is a schematic diagram showing another embodiment of the present invention.

In this case, the fX9 diagram is provided with a data selector 33 in place of the comparator 16 in FIG. 1, and the counter 17 is removed, and the same parts as in FIG. 1 are otherwise given the same reference numerals.

In this case, one line of image data 12 is transferred within a multi-bit shift register 11 in synchronization with a clock signal 13. When the transfer of all the image data is completed, the latch signal 15 is then applied, and the transferred image data 1
2 are all transferred to the latch 14 and held there. In this state, the print signal 20 is applied, and at the same time, the data select signal 34 of the data selector 33 is applied to the SEL terminal. The data select signal 34 in this case is composed of a plurality of bits, and one bit is selected from the plurality of bits of image data supplied from the latch 14.

In response to such a select signal 34, the data selector 3
3 is selected, and this data is given to the gate circuit 19 together with the print signal 20. Then, the gate circuit 19 is given the print signal 20 and the data selector 3
Only when the output from 3 is @1, a print output "11" is generated, and this output @1 turns on the driver 22 and energizes the heating resistor 21. Of course, even if the print signal 20 is output, the data is not output. When the output of the selector 33 is @0#, the driver 22 remains off and no current is applied.The first printing is thus performed.

Next, the second print signal 20 is applied, and at the same time, the data select signal 34 is applied. In this case, the second select signal 34 has different contents from the first select signal, and the data selector 33 extracts 1-bit data different from the first select signal from the image data. The data output from the data selector 33 is applied to the gate circuit 19 along with the print signal 20 as in the first time, and the heating resistor 21 is energized or de-energized. When the M2@th printing is completed, the third printing signal 20 and data select signal 34 are applied, and the third printing is performed. Thereafter, the same process is repeated and energization is performed for the same number of bits as the image data. Therefore, for example, if the image data is 8 bits, a 3-bit signal is used as the data select signal 34, and the print signal 20 is output a maximum of 8 times, but the pulse width of the print signal 20 at this time is changed each time. If different values are used, it is possible to achieve a recording density of up to 256 gradations as described in FIG.

In this way, one line of data is printed, and then all lines are printed in the same manner.

(3) The circuit shown in FIG. 9 can be further simplified by omitting the shift register αυ as in the case shown in FIG.

Next, FIG. 10 is a schematic configuration diagram showing still another embodiment of the present invention.

In this case, Fig. 10 is the same as Fig. 9, except that the latch 14 and data selector 33 in Fig. 9 are replaced with a parallel-in/serial-out shift register 35. is attached.

By using this arrangement, the scale of the circuit elements can be reduced compared to that shown in FIG. In this circuit, first, image data 12
is transferred through the shift register 11 in synchronization with the clock signal 13. When the transfer of all data is completed, the LD signal 26 is output, and the transfer data of the shift register 11 is loaded into the parallel-in/serial-out shift register 35. When image data is set in the shift register 35, a print signal 20 is applied. This signal 20 is applied to the gate circuit 19 together with the output of the shift register 35. Here, shift register 35 is shift register 1
A plurality of bits of the image signal 12 given from 1 is loaded by the LD signal 26, and at the same time, 1 bit of the image data is output. For example, image data 12
When is 8 bits, when data is first loaded, the 8th bit (MSB) data is output at the same time. As a result, the first print signal 20
MS output from the shift register 35 when
The energization of each heating resistor 21 is controlled by the B data. When the first printing is completed, the print signal 20 is inverted and applied to the CK terminal of the shift register 35, so the data shift is performed at the moment the print signal ends, and the next data (for example, the 7th bit-th data) is output. Next, the second print signal 2
When 0 is given, each heating resistor 21 is energized based on the data at this time, and after this printing is completed, the next data (for example, the 6th bit data) is output from the shift register 35. It will be output. Thereafter, data printing of one line is completed in the same manner by energizing the number of bits of the image data set in the shift register 35 or less (for example, eight times or less if the image data is 8 bits).

Next, FIG. 11 is a schematic configuration diagram showing still another embodiment of the present invention.

In this case, FIG. 11 is the same as FIG. 9 except that the gate circuit 19 of FIG. 9 is removed, and the same parts are given the same reference numerals.

That is, in this circuit, the data selector 33 has an output enable OEN.

In this way, if the output enable OEN becomes @1, the data selector 33 will always be @ regardless of the input signal.
0'', and only when the output enable OBN is @0'', the data selector 33 outputs the 1-bit value specified by the data select signal 34. Therefore, if the inverted signal of the print signal 20 is given to the output enable, the heating resistor 21 will be energized only when the print signal 20 is given and the output of the data selector 33 is @1''. The circuit 19 can be omitted.This circuit can also be further simplified by omitting the shift register αυ as in FIG.

Next, FIG. 12 is a schematic configuration diagram showing still another embodiment of the present invention.

In this case, the gate circuit 19 of FIG. 1O is removed from FIG. 12, and the other parts are the same as FIG. 10, and the same parts are given the same reference numerals.

By using such a circuit as the shift register 35 having an output enable OEN, the gate circuit 19 can be omitted as explained in FIG. 11.

Further, some of the shift registers (35) used in the circuits of FIGS. 10 and 12 have parallel OUT terminals. In such a case, if the parallel OUT terminal and the next parallel IN terminal are connected in cascade and a clock signal is supplied to the LD terminal, the shift register α1) of the circuits shown in Figs. 10 and 12 can be changed. do not need.

This greatly simplifies the circuit.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of the present invention, and FIG.
The figures are timing charts for explaining the same embodiment, FIG. 3 is a diagram showing the relationship between image data and energizing pulses, and FIG.
The figure is a schematic configuration diagram showing another embodiment of the present invention, and FIG.
a) (BL is a schematic block diagram showing only the essential parts of further embodiments of the present invention, FIGS. 6 and 7 are schematic block diagrams showing still other embodiments of the present invention, respectively. Figure 8 (al
(b) +CI is a schematic block diagram showing the circuit used in FIG. 7, and FIGS. 9, 1O, 11, and 12 are schematic block diagrams showing still other embodiments of the present invention, respectively. ,
Fig. 13 is a schematic configuration diagram showing an example of a conventional thermal head drive circuit, Fig. 14 (a) (bl is a diagram for explaining the same device, and Fig. @15 is a timing chart for explaining the same device) 1...Shift register 2...Image data 3...
・Clock signal 4...Latch signal 5...Latch 6...Print signal 7...Gate circuit
8... Driver 9... Heating resistor 11
...Shift register 12...Image data 13
...Lock signal 14...Latch 15...
・Latch signal 16... Connoisseur size controller 17...
Counter 18... Enable clock 19-... Gate circuit 20. 201, 202... Print signal 21.
・Heating resistor 22 ・Driver 23 ・
...Flip-flop 24--Gate 25
・・・Carry signal 26・, LD signal 27・
...Print start signal 28...Multi-vibrator
29.30...Flip-flop 3
1... Reset signal 32... Power-on reset circuit 33... Data selector 34... Data select signal 35... Shift register Fig. 3 3j! Figure 13 V Figure 14 (a)

Claims (5)

[Claims] (1) A first means for setting a plurality of bits of image data having density information by one data transfer and generating a print output for a time period corresponding to the set image data; A thermal head drive circuit characterized by comprising a heating resistor that is driven and energized by an output. (2) The first means includes a multi-bit shift register to which multi-bit image data is transferred in synchronization with a clock signal, and a multi-bit latch that holds the data transferred to the shift register. A thermal head drive circuit according to claim 1. (3) A patent characterized in that the first means has a counter that counts the enable clock, and a comparator that compares the count output of this counter with image data and generates an output until the count output becomes larger than the image data. A thermal head drive circuit according to claim 1 or 2. (4) The thermal head drive circuit according to claim 3, wherein the first means includes a flip-flop that prevents generation of the print output when the value of the counter reaches a maximum value. . (5) The first means has a data selector that selects image data bit by bit based on a data select signal, and a print signal that is generated as a print output together with the data of each bit selected by the data selector. A thermal head drive circuit according to claim 1 or 2.