JPH0136350Y2 - - Google Patents

Info

Publication number
JPH0136350Y2
JPH0136350Y2 JP6435583U JP6435583U JPH0136350Y2 JP H0136350 Y2 JPH0136350 Y2 JP H0136350Y2 JP 6435583 U JP6435583 U JP 6435583U JP 6435583 U JP6435583 U JP 6435583U JP H0136350 Y2 JPH0136350 Y2 JP H0136350Y2
Authority
JP
Japan
Prior art keywords
operational amplifier
output
amplifier
resistor
limiter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6435583U
Other languages
Japanese (ja)
Other versions
JPS59169118U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6435583U priority Critical patent/JPS59169118U/en
Publication of JPS59169118U publication Critical patent/JPS59169118U/en
Application granted granted Critical
Publication of JPH0136350Y2 publication Critical patent/JPH0136350Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は、演算増幅器を使つたダイオードリミ
ツタ付きパワーアンプに関する。
[Detailed Description of the Invention] The present invention relates to a power amplifier with a diode limiter using an operational amplifier.

この種の従来構成は、第1図に示す構成にされ
ている。演算増幅器OAはその反転入力端子に利
得演算用入力抵抗R1を介して入力信号が印加さ
れ、出力端子は電流制限用出力抵抗R2を介して
プツシユプル接続の一対の相補パワートランジス
タTr1,Tr2の共通ベース入力とされる。パワー
トランジスタTr1,Tr2はPNP型とNPN型の対に
され、夫々のコレクタは出力電流制限用抵抗R
3,R4を介して正負直流電源に接続され、両エ
ミツタは互いに接続されてパワーアンプの出力端
とされる。この出力端からは利得演算用帰還抵抗
R5を介して演算増幅器OAの反転入力端子に接
続される。また、出力端と正負直流電源との間に
夫々リミツタ値設定用可変抵抗器VR1,VR2
が接続される。可変抵抗器VR1,VR2の出力
端は夫々リミツタ用ダイオードD1,D2を介し
て演算増幅器OAの反転入力端子に接続される。
ダイオードD1はパワーアンプ出力の負極性側を
制限し、ダイオードD2は出力の正極性側を制限
する方向で接続される。
A conventional configuration of this type is shown in FIG. The operational amplifier OA has an input signal applied to its inverting input terminal via an input resistor R1 for gain calculation, and an output terminal of a pair of complementary power transistors Tr 1 and Tr 2 connected in a push-pull manner via an output resistor R2 for current limiting. Common base input. The power transistors Tr 1 and Tr 2 are a pair of PNP type and NPN type, and each collector has an output current limiting resistor R.
3 and R4 to the positive and negative DC power supplies, and both emitters are connected to each other to serve as the output end of the power amplifier. This output terminal is connected to the inverting input terminal of the operational amplifier OA via a feedback resistor R5 for gain calculation. In addition, variable resistors VR1 and VR2 for setting limiter values are connected between the output terminal and the positive and negative DC power supplies, respectively.
is connected. The output terminals of the variable resistors VR1 and VR2 are connected to the inverting input terminal of the operational amplifier OA via limiter diodes D1 and D2, respectively.
The diode D1 is connected in a direction to limit the negative polarity side of the power amplifier output, and the diode D2 is connected in a direction to limit the positive polarity side of the output.

こうした構成において、パワーアンプ利得は抵
抗R1,R5で決められ、正負リミツタ値は可変
抵抗器VR1,VR2の夫々の分圧比で決められ
る。ここで、正負リミツタ値の最小値はダイオー
ドD1,D2の順方向電圧(えん層電圧)で制限
され、この電圧以下の設定ができない欠点があつ
た。また、ダイオードD1,D2のえん層電圧は
温度によつて変動し、この変動分がリミツタ値の
変動分として現われる問題があつた。
In this configuration, the power amplifier gain is determined by the resistors R1 and R5, and the positive and negative limiter values are determined by the voltage division ratios of the variable resistors VR1 and VR2, respectively. Here, the minimum value of the positive and negative limiter values is limited by the forward voltage (enlayer voltage) of the diodes D1 and D2, and there is a drawback that it is not possible to set the voltage below this voltage. Further, there is a problem in that the layer voltages of the diodes D1 and D2 vary depending on the temperature, and this variation appears as a variation in the limiter value.

本考案の目的は、最小リミツタ値を零ボルトま
で制御できしかも温度変動の少ないパワーアンプ
を得ることを目的とする。
The object of the present invention is to obtain a power amplifier that can control the minimum limiter value down to zero volts and has little temperature fluctuation.

第2図は本考案の一実施例を示す回路構成図で
ある。同図が第1図と異なる部分は、可変抵抗器
VR1,VR2を演算増幅器OAの出力端子と正負
直流電源間に接続した点にある。
FIG. 2 is a circuit diagram showing an embodiment of the present invention. The difference between this figure and Figure 1 is the variable resistor.
VR1 and VR2 are connected between the output terminal of operational amplifier OA and the positive and negative DC power supplies.

本実施例において、ダイオードD1,D2のえ
ん層電圧分は夫々トランジスタTr1,Tr2のベー
ス・エミツタ間電圧として補償され、パワーアン
プ出力のリミツタ値としては零ボルトまで設定可
能になる。また、ダイオードD1,D2の温度に
よるえん層電圧の変動分はトランジスタTr1
Tr2のベース・エミツタ間電圧の温度による変動
として補償され、ダイオードD1,D2とトラン
ジスタTr1,Tr2をほぼ同じ温度になるよう配置、
例えばダイオードD1,D2をトランジスタに接
触させる配置にして温度変動によるリミツタ値の
変動を少なくできる。
In this embodiment, the cap layer voltages of the diodes D1 and D2 are compensated as the base-emitter voltages of the transistors Tr 1 and Tr 2 , respectively, and the limiter value of the power amplifier output can be set up to zero volts. Also, the variation in the en-layer voltage due to the temperature of the diodes D1 and D2 is caused by the transistors Tr 1 ,
The diodes D1 and D2 and the transistors Tr 1 and Tr 2 are arranged so that they are at almost the same temperature, which is compensated for as a temperature-related variation in the base-emitter voltage of Tr 2 .
For example, by placing the diodes D1 and D2 in contact with the transistors, it is possible to reduce fluctuations in the limiter value due to temperature fluctuations.

以上のとおり、本考案によれば最小リミツタ値
を零ボルトまで設定できしかも温度変動の少ない
出力を得ることができる。
As described above, according to the present invention, the minimum limiter value can be set to zero volts, and an output with little temperature fluctuation can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のパワーアンプ回路構成図、第2
図は本考案の一実施例を示す回路構成図である。 OA……演算増幅器、VR1,VR2……可変抵
抗器、D1,D2……ダイオード、Tr1,Tr2
…トランジスタ。
Figure 1 is a conventional power amplifier circuit configuration diagram, Figure 2
The figure is a circuit configuration diagram showing an embodiment of the present invention. OA...Operation amplifier, VR1, VR2...Variable resistor, D1, D2...Diode, Tr 1 , Tr 2 ...
...transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力抵抗を介して入力信号が印加される演算増
幅器と、この演算増幅器の出力端子と直流電源と
の間に接続されたリミツタ値設定用可変抵抗器
と、この可変抵抗器の出力端と上記演算増幅器の
反転入力端子との間に接続されたダイオードと、
上記演算増幅器の出力端子からの出力をベース入
力とするプツシユプル接続の一対の相補パワート
ランジスタと、このトランジスタの両エミツタ出
力端と上記演算増幅器の反転入力端子との間に接
続された帰還抵抗とを備えたことを特徴とするダ
イオードリミツタ付きパワーアンプ。
An operational amplifier to which an input signal is applied via an input resistor, a variable resistor for setting a limiter value connected between the output terminal of this operational amplifier and a DC power supply, and a variable resistor for setting a limiter value connected between the output terminal of this variable resistor and the above calculation a diode connected between the inverting input terminal of the amplifier;
A pair of complementary power transistors connected in a push-pull manner, each of which has an output from the output terminal of the operational amplifier as its base input, and a feedback resistor connected between both emitter output terminals of the transistors and an inverting input terminal of the operational amplifier. A power amplifier with a diode limiter.
JP6435583U 1983-04-28 1983-04-28 Power amplifier with diode limiter Granted JPS59169118U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6435583U JPS59169118U (en) 1983-04-28 1983-04-28 Power amplifier with diode limiter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6435583U JPS59169118U (en) 1983-04-28 1983-04-28 Power amplifier with diode limiter

Publications (2)

Publication Number Publication Date
JPS59169118U JPS59169118U (en) 1984-11-12
JPH0136350Y2 true JPH0136350Y2 (en) 1989-11-06

Family

ID=30194534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6435583U Granted JPS59169118U (en) 1983-04-28 1983-04-28 Power amplifier with diode limiter

Country Status (1)

Country Link
JP (1) JPS59169118U (en)

Also Published As

Publication number Publication date
JPS59169118U (en) 1984-11-12

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