JPH0132695B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital arithmetic circuit, and particularly to an arithmetic method suitable for a multi-frequency signal receiver.

SUMMARY OF THE INVENTION An object of the present invention is to provide an arithmetic method that can obtain sufficiently accurate arithmetic results under extremely wide input conditions while reducing the hardware of the arithmetic circuit.

The input condition is, for example, the dynamic range, and also includes polarity, frequency, signal form, speed, and other conditions.

Generally, a certain calculation method has input conditions suitable for that method, and if the input exceeds the range of the conditions, it is preferable to apply another method. In such cases, several circuits with different arithmetic methods are connected in parallel, and an input monitoring circuit is installed to determine which arithmetic circuit is suitable for calculating the input at that time. By monitoring the input and making appropriate choices, it is possible to obtain sufficient characteristics for a very wide range of input conditions.

Furthermore, if all the operations of the digital arithmetic circuit were to be performed by one arithmetic circuit, that arithmetic circuit would require an enormous amount of hardware. For this reason, the arithmetic circuit is made up of multiple circuits with different approximation conditions.
Depending on the input conditions, by selecting the output of the arithmetic circuit that approximates the input conditions, it is possible to reduce the hardware and perform calculations with the required accuracy.

For example, when calculating the square root of the sum of squares of orthogonal components in a multifrequency signal receiver using discrete Fourier transform technology, the input is an address, and the square root of the sum of squares corresponding to the value of that address is calculated using a ROM (read-only memory). ) requires a huge amount of ROM capacity.

If we try to obtain the square root of the sum of the squares of two 16-bit inputs using the ROM output, the input will be 32 bits, so we will need 2 ³² = 4294967296 words x 16 bits, and there is no way we can do that with just the ROM. It is not possible to realize an arithmetic circuit.

For this reason, the output of an adder that adds the absolute values of orthogonal components, and the output of a ROM that uses a part of the input of the adder as an address and outputs the square root of the sum of squares corresponding to the value of that address, are stored in that ROM. If the selection is made based on the output of an input level monitoring circuit that determines whether the input corresponding to the written output is input to that address, the ROM capacity can be reduced and calculations with the necessary precision can be achieved. It can be performed.

In other words, when the input level is high and the calculation accuracy up to orthogonal components is high, the absolute value sum method is used, which has somewhat inferior approximation accuracy but is suitable for a wide dynamic range, and when the input level is low and the calculation accuracy up to orthogonal components is high, If the value is only low, by using a calculation method that reads the square root of the sum of squares using a ROM with excellent approximate accuracy, the hardware of the calculation circuit can be made smaller and sufficient characteristics can be obtained for all input conditions. Can be done.

In order to achieve the above-mentioned object, the present invention performs a calculation of the sum of absolute values for two input data showing orthogonal components in a calculation method used in a multi-frequency signal receiver using discrete Fourier transform technology. a memory that outputs the square root calculation result of the sum of squares stored in advance for the partial input data using a portion of each of the two data as an address; an output selection circuit that selects and outputs the output and the output of the memory; and an output selection circuit that monitors the levels of the two input data, selects the output of the digital adder when the input is a high level, and selects the output of the digital adder when the input is a low level. The present invention is characterized by comprising an input monitoring circuit that controls the output selection circuit to select the output of the memory with respect to a group of bits corresponding to the output of the memory.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a multifrequency signal receiver using discrete Fourier transform technology.

The input 1 of the receiver is multiplied by a wind function generated by a wind function generator 2 in a multiplier 3, and input to a discrete Fourier transform circuit 4 for each signal frequency to be received. The input to this circuit 4 is multiplied by an orthogonal function, which is the core of the discrete Fourier transform, generated by orthogonal function generators 5 and 6, respectively, by multipliers 7 and 8, and the result is kept constant by integrators 9 and 10. Each period is integrated. After that, the absolute value circuit 11,1
2 to take the absolute value of the orthogonal component of the discrete Fourier transform. The outputs are respectively input to the arithmetic circuit 13, and the arithmetic result of the square root of the sum of squares of the orthogonal components described above is output. The output logic circuit 14 determines the magnitude of the output of each circuit 4, for example, determines the circuit 4 whose output exceeds a certain value, or compares the magnitude of the output of each circuit 4, and outputs the reception frequency result to a terminal. Output to 15.

FIG. 2 is a block diagram showing one embodiment of the present invention, and this embodiment can be applied to the arithmetic circuit 13 of the discrete Fourier transform circuit 4 of FIG. 1 described above. The absolute values of orthogonal components of multiple bits are input to the two input terminals I ₁ and I ₂ respectively, and the first arithmetic circuit
Input into P ₁ . This arithmetic circuit _P1 is a commonly known arithmetic and logic unit or adder and outputs the result of addition of the values of inputs _I1 and _I2 , which is supplied to an output selection circuit S. The second arithmetic circuit _P2 is
It is ROM. The inputs I ₁ and I ₂ are each divided into several bits, and the middle signals 101 and 11 are
Only 1 is input as the address of this ROM. This ROM stores the number bits of the square root of the sum of the squares of the inputs _I1 and _I2 , which are calculated assuming that the values of the upper bit groups 102 and 112 and the lower bit groups 100 and 110 of the input are all zero. The output is connected to an output selection circuit S. The input monitoring circuit V detects the upper bit groups 102 and 11 of inputs _I1 and _I2 .
2 and determines whether the values of 102 and 112 are both zero, and its output is connected to the control input of the output selection circuit S.

The output selection circuit S normally outputs the output of the arithmetic circuit P ₁ to the output terminal O, but the output of the input monitoring circuit V determines that the values of 102 and 112 for inputs I ₁ and I ₂ are both zero. Only if the calculation circuit
Only the bit group corresponding to the output of _P2 is sent to the arithmetic circuit.
Select from the output of P ₂ , and the other bit groups are used by the arithmetic circuit.
Output the output of _P1 to output terminal O.

In this example, if the input is 16 bits,
In order for the second arithmetic circuit _P2 using ROM to perform arithmetic operations on all the dynamic ranges of the inputs, the inputs _I1 and _I2 are both 16 bits, so the input is 32 bits, and the capacity of the ROM is As mentioned above, a capacity of 2 ³² = 4294967296 words x 16 bits is required, which cannot be easily realized.

In Figure 2, 102 and 112 are 8 bits,
101, 111 are 8 bits, 100, 110 are 0
In terms of bits, the second arithmetic circuit _P2 has a 16-bit input, that is, a capacity of 2 ¹⁶ =65536 words x 9 bits, which is a feasible capacity.

And the first calculation circuit using the absolute value sum method
Even if the input is 16 bits, the P ₁ can approximate the sum of squares with the required accuracy using a single 16-bit adder, and can be used in complex logical operation circuits or large capacity
Does not require ROM.

In other words, the square root z of the sum of squares of x and y is z=√ ² + ² , and if x is zcosα, then y=√ ² − ² = z√1− ² = zsinα, and the sum of the squares of x and y is Absolute value sum | x|+|y|=√2zsin(α+π/4) holds, and it also holds true when α is π/2 to 2π, so z≦|x|+|y|≦√2z, and 1 to √2 Although there is an error in the double range, it can be approximated as the square root of the sum of squares.

Therefore, when the input level is high, by calculating an approximate value using an adder, a simple calculation circuit can perform calculations according to the input conditions, and there is no need to use a large-capacity ROM.

As explained above, according to the present invention, it is possible to provide an arithmetic method that can be realized with a small hardware configuration, whereas the hardware configuration of one arithmetic method would be enormous.

Furthermore, there is an effect of obtaining characteristics that cannot be obtained with a single calculation method. In particular, even with calculation methods that were difficult to implement with conventional technology, the output is selected only when the input conditions are suitable for that method, so the hardware configuration can be simplified so that the correct output can be obtained only under those conditions. This has the effect of being easily realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a general multi-frequency signal receiver using discrete Fourier transform technology, and FIG. 2 is a block diagram showing an embodiment of the present invention. I ₁ , I ₂ ... Input terminal, P ₁ , P ₂ ... Arithmetic circuit, V
...Input monitoring circuit, S...Output selection circuit, O...
Output terminal.

Claims (1)

[Claims] 1. An arithmetic method used in a multi-frequency signal receiver using discrete Fourier transform technology, comprising: a digital adder that calculates the sum of absolute values of two input data representing orthogonal components; a memory that outputs the square root calculation result of the sum of squares stored in advance for the partial input data using a portion of each of the two data as an address; an output of the digital adder and an output of the memory; and an output selection circuit that monitors the levels of the two input data and selects the output of the digital adder when the input is a high level, and corresponds to the output of the memory when the input is a low level. an input monitoring circuit that controls the output selection circuit to select an output of the memory with respect to a group of bits.