JPS56156054A - Variable arithmetic system - Google Patents
Variable arithmetic systemInfo
- Publication number
- JPS56156054A JPS56156054A JP6034980A JP6034980A JPS56156054A JP S56156054 A JPS56156054 A JP S56156054A JP 6034980 A JP6034980 A JP 6034980A JP 6034980 A JP6034980 A JP 6034980A JP S56156054 A JPS56156054 A JP S56156054A
- Authority
- JP
- Japan
- Prior art keywords
- arithmetic
- circuit
- input
- circuits
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To obtain a characteristic that could not be secured by an arithemtic system, by connecting plural arithmetic circuits applying different arithemtic systems to a common input and then selecting the arithmetic circuit according to the conditions of the input obtained at a monitor circuit. CONSTITUTION:In the case of two inputs plus three arithmetic circuits, the 1st and 2nd input terminal I1 and I2 are connected in common to an arithmetic circuit P1 of the 1st arithmetic system, an arithmetic circuit P2 of the 2nd arithmetic system, an arithmetic circuit P3 of the 3rd arithmetic system and an input monitor circuit V respectively. The outputs of circuits P1-P3 are connected to an output selecting circuit S. The circuit S is controlled by the output of a circuit V, and either one of these outputs is selected to be sent to an output terminal O.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6034980A JPS56156054A (en) | 1980-05-06 | 1980-05-06 | Variable arithmetic system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6034980A JPS56156054A (en) | 1980-05-06 | 1980-05-06 | Variable arithmetic system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56156054A true JPS56156054A (en) | 1981-12-02 |
JPH0132695B2 JPH0132695B2 (en) | 1989-07-10 |
Family
ID=13139586
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6034980A Granted JPS56156054A (en) | 1980-05-06 | 1980-05-06 | Variable arithmetic system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56156054A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5474350A (en) * | 1977-11-25 | 1979-06-14 | Toshiba Corp | Compressor circuit |
-
1980
- 1980-05-06 JP JP6034980A patent/JPS56156054A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5474350A (en) * | 1977-11-25 | 1979-06-14 | Toshiba Corp | Compressor circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0132695B2 (en) | 1989-07-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB1452920A (en) | Signal equalizers | |
JPS5421152A (en) | Comparison circuit | |
JPS56156054A (en) | Variable arithmetic system | |
GB958884A (en) | General purpose majority-decision logic arrays | |
JPS5261945A (en) | Transistor circuit | |
JPS5627504A (en) | Active antenna system | |
GB1390664A (en) | Circuits utilizing gyrators | |
GB1287845A (en) | ||
JPS55127607A (en) | Free-program type process controller | |
JPS54112134A (en) | Logical operation circuit | |
JPS5592028A (en) | Signal switching circuit | |
JPS55138109A (en) | Input-output control system of sequence controller | |
JPS5748153A (en) | Picture element density converting system | |
JPS5647846A (en) | Parity check system | |
JPS5476048A (en) | Noncyclic variable filter | |
JPS56124930A (en) | Initial program loader system | |
JPS5630328A (en) | Nonbreak circuit | |
JPS5696328A (en) | Logical arithmetic operating device | |
JPS54145449A (en) | Input-output system of electronic computer | |
GB1165584A (en) | Circuit Arrangement for the Automatic Balancing of Pre-Set Current Values which can be Varied Arbitrarily. | |
JPS5453234A (en) | Transmission fault processor controller | |
JPS5460676A (en) | Sequencer | |
JPS5527789A (en) | Transversal filter | |
DE3375545D1 (en) | High power amplifier arrangement | |
JPS57162015A (en) | Common input/output bus controlling system |